CN1244864C - Information processing system with debug function on initializing and its method - Google Patents
Information processing system with debug function on initializing and its method Download PDFInfo
- Publication number
- CN1244864C CN1244864C CN 01102599 CN01102599A CN1244864C CN 1244864 C CN1244864 C CN 1244864C CN 01102599 CN01102599 CN 01102599 CN 01102599 A CN01102599 A CN 01102599A CN 1244864 C CN1244864 C CN 1244864C
- Authority
- CN
- China
- Prior art keywords
- display device
- symbol display
- numeral
- information handling
- handling system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000010365 information processing Effects 0.000 title abstract 2
- 238000012360 testing method Methods 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims abstract description 11
- 230000009471 action Effects 0.000 claims description 11
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 230000007246 mechanism Effects 0.000 abstract description 6
- 230000005540 biological transmission Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Debugging And Monitoring (AREA)
Abstract
The present invention relates to an information processing system with a starting error-eliminating function, which comprises a build-in display mechanism. Before a basic input and output system executes a self-starting test, the display mechanism is firstly initialized. Subsequently, before each testing operation in the process of the self-starting test is executed, the code of each test point is displayed in the display mechanism. Thus, when an error occurs in the process of the self-starting test, the test can be immediately stopped to stop the system. At this point, the code of the test point occurs in the error is displayed on the build-in display mechanism.
Description
Technical field
The present invention relates to a kind of information handling system, have display panel in particularly a kind of, can when the start selftest, show test point code, to carry out the information handling system of error eliminating function.
Background technology
When being reset such as information handling systems such as computers or starting, Basic Input or Output System (BIOS) (BIOS) can be carried out a start selftest (Power-on self-test at hardware, POST), that is, the computing of processor, display card, storer, driver etc. are carried out a series of checkout action.The all designated code of each test point in this hardware testing process.In the existing bios program sign indicating number, before a test point was about to test, its code can be output to a specific I/O mouth (normally port 80h).
In the R﹠D process of information handling system, often need carry out debug to BIOS.The method that present known computer and BIOS manufacturer are adopted is that the housing of computer is taken apart, and uses a kind of interface card with display circuit to be plugged on the motherboard and reach.When having certain part hardware capability to make a mistake in the POST implementation, the test action meeting stops immediately, at this moment, can watch test point code via the double figures seven-segment display on the interface card, and learn the part that makes a mistake.Yet this kind method is very inconvenient in the use, and needs to reserve the next external interface card in a part of motherboard space, and not only wasting space does not also meet the requirement of trend toward miniaturization.
Another kind of existent method is that a subcard with display circuit is external in printer port, exports the test point code of port 80h to reception.Yet following computer will be gradually towards the concept development of interface simplification (Legacy Free), and when the time comes, computer will no longer be provided with printer port, and only have the USB mouth, so promptly can't carry out debug in the mode of above-mentioned external subcard.
Summary of the invention
The object of the present invention is to provide a kind of information handling system with power-on debugging function, it comprises at least: a Basic Input or Output System (BIOS); And a display system, in be built in this information handling system, this display system is used for carrying out start self test program process in this Basic Input or Output System (BIOS) and shows each test point code.
Another object of the present invention is to provide a kind of information handling system, and it comprises: a Basic Input or Output System (BIOS), and it comprises a basic input and output storer and a bridge controller; This basic input and output storer of this bridge controller electric coupling; And a display system, this bridge controller of its electric coupling is used for showing each test point code when this Basic Input or Output System (BIOS) is carried out the start self test program.
Another object of the present invention is to provide a kind of power-on debugging method of information handling system, and it comprises the following step at least: a built-in display system in this information handling system; When the start self test program of this information handling system begins, this display system of initialization; And in this start self test program process, each test point code is shown in this display system.
Another object of the present invention is to provide a kind of power-on debugging method of information handling system, and wherein this information handling system comprises a basic input and output storer, a display system and a bridge controller of linking up this basic input and output storer and this display system; This method comprises the following step at least: when the start self test program of this information handling system begins, and this bridge controller of initialization and this display system; And in this start self test program process, each test point code is shown in this display system.
Brief Description Of Drawings
Fig. 1 is the calcspar of the preferred embodiment of information handling system of the present invention;
Fig. 2 is the action flow chart of start selftest (POST) program of Fig. 1 preferred embodiment; And
Fig. 3 is the preferred embodiment of Fig. 1 shows test point code on indication mechanism a action flow chart.
Embodiment
Hereinafter with reference to embodiment shown in the drawings information handling system and power-on debugging method thereof with power-on debugging function of the present invention is described in further detail.Mentioned information handling system can be desktop computer, portable computer or other similar information treatment facilities among the present invention.
The preferred embodiment of information handling system 10 of the present invention roughly is shown in Fig. 1, and its main framework is identical with existing computer system haply.Processor 12 is connected to storer 14 via north bridge 16, and vga controller 20 is connected to north bridge 16 via pci bus 18.One south bridge 24 also is connected to north bridge 16 via pci bus 18, and is connected with a BIOS ROM 22.Especially, information handling system 10 of the present invention also has an indication mechanism, and it comprises a display device 30 and a display device controller 28, and is connected to the SMBus (Smart Battery Bus) 26 in the south bridge 24.
After the power supply of information handling system 10 is unlocked and is stable, promptly begin to carry out start selftest (POST) process, its action flow chart is shown in Fig. 2.At first, must carry out initialization to south bridge 24, SMBus 26 and display device controller 28, so that display device 30 possesses the function of normal demonstration.Then, promptly begin to carry out a series of hardware check test action at processor, storer, display card or the like.The all designated test point code of each test, this code are looked the design manufacturer of BIOS and are different.As shown in Figure 2, the method according to this invention, the code of demonstration first test point on display device 30 carries out the checkout action to this first test point immediately earlier.If this test result is normal, then continues on display device 30, to show the code of next test point, and immediately this next test point is carried out the checkout action.
So, in above-mentioned start selftest process, when if the test result of certain test point makes a mistake, the test action meeting stops immediately and system is shelved, this moment display device 30 on shown code, just can the system of indicating shelve preceding last test point that is checked through, that is this test point that makes a mistake.Therefore, the user can learn the wrong possible cause that takes place easily, and takes suitable treatment measures.
If the start selftest all are normally errorless as a result, after then in the end a test point inspection finishes, remove the data on the display device 30, and open operating system.
The detailed motion flow that shows test point code on display device 30 is shown in Fig. 3.At first, the code data that desire is shown exports display device controller 28 to via SMBus 26, and checks whether the transmission action of SMBus 26 is finished, and does not then continue to transmit as finishing as yet, after data transmission is finished, promptly is shown on the display device 30.
Though the present invention illustrates as above with reference to accompanying drawing and preferred embodiment, yet the present invention is not limited thereto, variation and modification that any foundation spirit of the present invention is made all should belong to scope of the present invention.
Claims (9)
1. information handling system, it comprises:
One Basic Input or Output System (BIOS), it comprises a basic input and output storer and a south bridge; This basic input and output storer of this south bridge electric coupling, described south bridge comprises a SMbus; And
One numeral or symbol display device are used for showing each test point code with numeral or symbol mode when this Basic Input or Output System (BIOS) is carried out the start self test program;
Numeral or symbol display device controller, its electric coupling should numeral or symbol display device, described south bridge is connected with described numeral or symbol display device controller by described SMBus, is used for when this Basic Input or Output System (BIOS) is carried out start self test program each test point code is sent to described numeral or symbol display device controller to show by described south bridge and SMBus on described numeral or symbol display device.
2. information handling system as claimed in claim 1, wherein, described numeral or symbol display device are the seven-segment displaies of two digits at least.
3. information handling system as claimed in claim 1, wherein, described numeral or symbol display device are the built-in display panels of this information handling system.
4. information handling system as claimed in claim 1, wherein, this information handling system is a computer.
5. the power-on debugging method of an information handling system, wherein this information handling system comprises a basic input and output storer, a numeral or symbol display device and display control unit thereof and links up this basic input and output storer and a south bridge of this numeral or symbol display device, and described south bridge comprises a SMbus; This method comprises the following step at least:
When the start self test program of this information handling system begins, this south bridge of initialization, SMbus and this numeral or symbol display device controller;
Carry out start self test program process;
In this start self test program process, each test point code is sent to described numeral or symbol display device controller by described south bridge and SMBus; With
Described numeral or symbol display device controller control figure or symbol display device show this each test point code with numeral or symbol mode on described numeral or symbol display device.
6. method as claimed in claim 5, wherein, this is shown in the step of this display system with each test point code, is to finish before the test action of each test point in this is carried out.
7. as claim 5 or 6 described methods, it also comprises the following step: after the start self test program of this information handling system is finished, remove this display system.
8. the power-on debugging method of information handling system as claimed in claim 5, wherein, described numeral or symbol display device are the seven-segment displaies of two digits at least.
9. the power-on debugging method of information handling system as claimed in claim 5, wherein, described numeral or symbol display device are the built-in display panels of this information handling system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01102599 CN1244864C (en) | 2001-02-01 | 2001-02-01 | Information processing system with debug function on initializing and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01102599 CN1244864C (en) | 2001-02-01 | 2001-02-01 | Information processing system with debug function on initializing and its method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1368677A CN1368677A (en) | 2002-09-11 |
| CN1244864C true CN1244864C (en) | 2006-03-08 |
Family
ID=4652856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01102599 Expired - Fee Related CN1244864C (en) | 2001-02-01 | 2001-02-01 | Information processing system with debug function on initializing and its method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1244864C (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100389398C (en) * | 2004-11-22 | 2008-05-21 | 英业达股份有限公司 | Testing system and method for positioning problem component in mainboard |
| CN100399266C (en) * | 2005-04-26 | 2008-07-02 | 乐金电子（昆山）电脑有限公司 | System and method for clearing computer fault |
| CN100458692C (en) * | 2005-12-15 | 2009-02-04 | 英业达股份有限公司 | System and method for correcting fault of turn-on self-test |
| CN100401263C (en) * | 2005-12-20 | 2008-07-09 | 英业达股份有限公司 | Error checking system and method after turn-on machine |
| CN100430901C (en) * | 2005-12-31 | 2008-11-05 | 英业达股份有限公司 | BIOS debug method assisted by CMOS memory |
| CN101425030B (en) * | 2007-10-29 | 2011-04-13 | 环旭电子股份有限公司 | Debugging method for basic I/O system |
| CN101826046B (en) * | 2009-03-06 | 2011-12-14 | 纬创资通股份有限公司 | Power-on debugging method of computer |
| CN101887372B (en) * | 2009-05-13 | 2014-06-25 | 微盟电子(昆山)有限公司 | Computer mainboard with built-in configuration display functions in basic input/output system |
| CN101907916A (en) * | 2010-06-18 | 2010-12-08 | 联达科技(厦门)有限公司 | Intelligent protection circuit and method of notebook battery pack |
| KR20150019836A (en) * | 2013-08-16 | 2015-02-25 | 현대모비스 주식회사 | Multimedia device with error detection function while boot time and method thereof |
| CN111045899B (en) * | 2018-10-11 | 2024-02-09 | 环达电脑(上海)有限公司 | Method for displaying BIOS information in early stage of computer system startup self-check |
-
2001
- 2001-02-01 CN CN 01102599 patent/CN1244864C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1368677A (en) | 2002-09-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103970560B (en) | Starting method and electronic device | |
| US7493438B2 (en) | Apparatus and method for enumeration of processors during hot-plug of a compute node | |
| US6553432B1 (en) | Method and system for selecting IDE devices | |
| US8707103B2 (en) | Debugging apparatus for computer system and method thereof | |
| US7822964B2 (en) | Booting apparatus for booting a computer and method therefor and computer with a booting apparatus | |
| CN1244864C (en) | Information processing system with debug function on initializing and its method | |
| JPH0773046A (en) | Method and equipment for emulation of circuit in computer system | |
| CN100412804C (en) | Method and system for recognizing error codes of failure diagnosis card for main board | |
| US7467290B2 (en) | Method and system for providing a modular server on USB flash storage | |
| US7747909B2 (en) | Debug card | |
| US20080021695A1 (en) | ROM emulator and ROM testing method using the same | |
| US7213159B2 (en) | Method for testing and verifying power management features of computer system | |
| US7788557B2 (en) | Baseboard testing interface and testing method thereof | |
| CN104035844A (en) | Fault testing method and electronic device | |
| CN111752623A (en) | Display configuration method and device, electronic equipment and readable storage medium | |
| US20070239976A1 (en) | Message displaying system and method | |
| US20060080473A1 (en) | Apparatus for emulating memory and method thereof | |
| CN110321171B (en) | Startup detection device, system and method | |
| CN113849267A (en) | Virtual display method, system, terminal and storage medium for display card | |
| KR20070089399A (en) | Method for booting control of digital store apparatus | |
| CN109597740B (en) | Display method and device of debugging code and computer equipment | |
| US20230359536A1 (en) | Verification system of basic input output system and verification method thereof | |
| TW501006B (en) | Information processing system with power-on debugging function and the power-on debugging method | |
| CN102298544A (en) | Method for debugging for computer systems | |
| CN101086716A (en) | Computer with status display module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: WEICHUANG ZITONG CO., LTD. Effective date: 20030725 Owner name: HONHQI CO., LTD. Free format text: FORMER OWNER: ACER COMPUTER CO., LTD. |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20030725 Address after: Taiwan, China Applicant after: Acer Inc Co-applicant after: Weichuang Zitong Co., Ltd. Address before: Taiwan, China Applicant before: Acer Computer Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CI01 | Correction of invention patent gazette |
Correction item: Co-patentee Correct: Acer Limited by Share Ltd|Weichuang Zitong Co., Ltd. False: Acer Computer Co., Ltd. Number: 10 Page: 815 Volume: 22 |
|
| CI03 | Correction of invention patent |
Correction item: Co-patentee Correct: Acer Inc|Weichuang Zitong Co., Ltd. False: Acer Computer Co., Ltd. Number: 10 Page: The title page Volume: 22 |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: CO-PATENTEE; FROM: ACER COMPUTER CO., LTD. TO: HONHQI CO., LTD. WEICHUANG ZITONG CO., LTD. |
|
| ERR | Gazette correction |
Free format text: CORRECT: CO-PATENTEE; FROM: ACER COMPUTER CO., LTD. TO: HONHQI CO., LTD. WEICHUANG ZITONG CO., LTD. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060308 Termination date: 20190201 |