CN113972918A

CN113972918A - Interleaved address acquisition method and device, storage medium and electronic equipment

Info

Publication number: CN113972918A
Application number: CN202111262733.9A
Authority: CN
Inventors: 杨汝燕; 陈守金; 邹刚; 黄海莲; 刘波
Original assignee: Chengdu Xinglian Xintong Technology Co ltd
Current assignee: Chengdu Xinglian Xintong Technology Co ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-01-25

Abstract

The application provides an interleaving address obtaining method, an interleaving address obtaining device, a storage medium and electronic equipment, and the method comprises the steps of obtaining a target increment of a current bit pair, wherein the target increment is an increment of a current interleaving address relative to a previous interleaving address, the current interleaving address is an interleaving address of the current bit pair, and the previous interleaving address is an interleaving address of the previous bit pair; and determining the current interleaving address according to the last interleaving address and the target increment. When the target increment and the last interleaving address are obtained, the current interleaving address can be obtained only by adding. The large number of multiplications involved in conventional second layer interleaving is not involved. And because the interleaving address is obtained by real-time calculation, the interleaving address does not need to be stored in advance, and a large amount of storage and logic resources are not occupied.

Description

Interleaved address acquisition method and device, storage medium and electronic equipment

Technical Field

The present application relates to the field of decoding, and in particular, to a method and an apparatus for obtaining an interleaved address, a storage medium, and an electronic device.

Background

In the turbo code decoding of the RCS2, the performance of decoding and the performance of an interleaver are closely related. In the design of the traditional interleaver, pipeline operation is needed, the interleaving/de-interleaving positions are obtained in real time, the interleaving addresses need to be stored in the ROM in advance, and the interleaving/de-interleaving positions are realized by adopting the access addresses of the control ROM.

The interleaving process of the turbo code is generally divided into two layers, the first layer of interleaving is to adjust the order of the bits in the bit pairs according to the positions of the bit pairs in the bit pair sequence, if the bit pairs are odd, the high bits and the low bits of the bit pairs are interchanged, otherwise, the bit pairs are kept unchanged. The interleaving address generation mode in the second layer of interleaving involves a large amount of multiplication and modulus, occupies more logic and clock resources, and becomes a bottleneck limiting the comprehensive speed of turbo coding and decoding.

Disclosure of Invention

An object of the present application is to provide an interleaved address obtaining method, apparatus, storage medium and electronic device, so as to at least partially improve the above problems.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, an embodiment of the present application provides an interleaving address obtaining method, where the method includes:

acquiring a target increment of a current bit pair, wherein the target increment is an increment of a current interleaving address relative to a last interleaving address, the current interleaving address is an interleaving address of the current bit pair, and the last interleaving address is an interleaving address of a last bit pair;

and determining the current interleaving address according to the last interleaving address and the target increment.

In a second aspect, an embodiment of the present application provides an interleaving address obtaining apparatus, where the apparatus includes:

a processing unit, configured to obtain a target increment of a current bit pair, where the target increment is an increment of a current interleaving address relative to a previous interleaving address, the current interleaving address is an interleaving address of the current bit pair, and the previous interleaving address is an interleaving address of a previous bit pair;

and the calculating unit is used for determining the current interleaving address according to the previous interleaving address and the target increment.

In a third aspect, the present application provides a storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the method described above.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: a processor and memory for storing one or more programs; the one or more programs, when executed by the processor, implement the methods described above.

Compared with the prior art, the interleaving address obtaining method, the interleaving address obtaining device, the storage medium and the electronic device provided by the embodiment of the application obtain the target increment of the current bit pair, wherein the target increment is the increment of the current interleaving address relative to the previous interleaving address, the current interleaving address is the interleaving address of the current bit pair, and the previous interleaving address is the interleaving address of the previous bit pair; and determining the current interleaving address according to the last interleaving address and the target increment. When the target increment and the last interleaving address are obtained, the current interleaving address can be obtained only by adding. The large number of multiplications involved in conventional second layer interleaving is not involved. And because the interleaving address is obtained by real-time calculation, the interleaving address does not need to be stored in advance, and a large amount of storage and logic resources are not occupied.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic design diagram of an interleaver of a turbo code of RCS2 according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a schematic flowchart of an interleaved address obtaining method according to an embodiment of the present application;

fig. 4 is a schematic view of the substeps of S105 provided in the embodiment of the present application;

fig. 5 is a flowchart of an interleaved address obtaining method according to an embodiment of the present application;

fig. 6 is a flowchart of an interleaved address obtaining method according to an embodiment of the present application;

FIG. 7 is a block diagram of parallel interleaving real-time computation provided by an embodiment of the present application;

fig. 8 is a block diagram of interleaving and deinterleaving provided by an embodiment of the present application;

fig. 9 is a schematic unit diagram of an interleaved address obtaining apparatus according to an embodiment of the present application.

In the figure: 10-a processor; 11-a memory; 12-a bus; 13-a communication interface; 201-a processing unit; 202-a calculation unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The interleaving address generation mode of the second layer interleaving relates to a large amount of multiplication and modulus, occupies more logic and clock resources, and becomes a bottleneck for limiting the comprehensive speed of turbo coding and decoding. Specifically, referring to fig. 1, the design of the interleaver of the turbo code of the conventional RCS2 is shown in fig. 1. For the second layer interleaving, the interleaving addresses corresponding to all the code lengths are stored in the same ROM in a segmented mode in advance, the initial position of interleaving address storage is determined according to the code lengths during interleaving, and the change of the ROM address is controlled by using input enable. For the first layer interleaving, due to the parity criterion of the interleaver, the order of the bit pairs can be controlled by the lowest bits of the interleaving address at the time of serial-to-parallel conversion without judging the parity position where the bit pairs are located. And finally, after two layers of interleaving, storing data in one RAM block, and directly reading the data from the RAM during calling.

Because the DVB-RCS2 supports a great number of code lengths and code rates, which reach more than 30, if all the codes are stored, a great amount of storage resources are consumed, and if all the codes are stored, 700Kbits of storage resources are needed through calculation. Considering parallel operation, if the interleaving address needs to be accessed simultaneously, the multiplication is also needed, and the total consumption reaches 1.4 Mbits. This is unacceptable for most hardware implementations and severely impacts the range of applications for turbo code decoding.

In order to overcome the defect of the conventional second layer interleaving, an embodiment of the present application provides an interleaving address obtaining method. And a new method for outputting and calculating the interleaving position is explored, the interleaving position information does not need to be stored additionally, and the interleaving and de-interleaving position information is obtained efficiently and in real time. Meanwhile, interleaving and deinterleaving are combined because of the precedence sequence in the iteration process, and the interleaving and deinterleaving are properly transformed to obtain the position information of the next deinterleaving and are cached when the interleaving position is calculated by utilizing the algorithm characteristics of the deinterleaving and the interleaving. Under the condition of not increasing logic resources, the functions of interleaving and deinterleaving are realized simultaneously. The method brings important economic benefits and meets practical requirements on engineering realization and efficient turbo code decoding realization. In the scheme of the application, the interleaving/de-interleaving algorithm is properly changed, and a novel model is adopted, so that the interleaving and de-interleaving positions required by decoding can be calculated in real time. Through evaluation, the interleaving address obtaining method provided by the embodiment of the application consumes less logic resources, only dozens of lookup tables are needed, and a special RAM is not needed to be stored due to the interleaving position obtained through real-time calculation.

Specifically, the embodiment of the application provides an electronic device which can be a computer or a server device. Please refer to fig. 2, a schematic structural diagram of an electronic device. The electronic device comprises a processor 10, a memory 11, a bus 12. The processor 10 and the memory 11 are connected by a bus 12, and the processor 10 is configured to execute an executable module, such as a computer program, stored in the memory 11.

The processor 10 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the interleaved address fetching method may be performed by hardware integrated logic circuits or instructions in software in the processor 10. The Processor 10 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.

The Memory 11 may comprise a high-speed Random Access Memory (RAM) and may further comprise a non-volatile Memory (non-volatile Memory), such as at least one disk Memory.

The bus 12 may be an ISA (Industry Standard architecture) bus, a PCI (peripheral Component interconnect) bus, an EISA (extended Industry Standard architecture) bus, or the like. Only one bi-directional arrow is shown in fig. 2, but this does not indicate only one bus 12 or one type of bus 12.

The memory 11 is used for storing programs, for example, programs corresponding to the interleaving address obtaining device. The interleaving address obtaining means includes at least one software functional module which can be stored in the memory 11 in the form of software or firmware (firmware) or solidified in an Operating System (OS) of the electronic device. The processor 10, upon receiving the execution instruction, executes the program to implement the interleaved address acquisition method.

Possibly, the electronic device provided by the embodiment of the present application further includes a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

It should be understood that the structure shown in fig. 2 is merely a structural schematic diagram of a portion of an electronic device, which may also include more or fewer components than shown in fig. 2, or have a different configuration than shown in fig. 2. The components shown in fig. 2 may be implemented in hardware, software, or a combination thereof.

Referring to fig. 3, an interleaved address obtaining method provided in an embodiment of the present application may be applied to, but is not limited to, an electronic device shown in fig. 2, and includes: s105 and S106.

And S105, acquiring the target increment of the current bit pair.

The target increment is the increment of the current interleaving address relative to the last interleaving address, the current interleaving address is the interleaving address of the current bit pair, and the last interleaving address is the interleaving address of the last bit pair.

It will be appreciated that the current bit pair is a bit pair other than the first bit in the sequence of bit pairs, e.g., bits 2 through N-1, where N is the code length of the sequence of bit pairs. The last bit pair is the bit pair in the sequence of bit pairs that is ranked before the current bit pair. For example, the current bit pair is the second bit in the bit pair sequence, and the last bit pair is the 1 st bit in the bit pair sequence.

S106, determining the current interleaving address according to the last interleaving address and the target increment.

It is understood that in the case of obtaining the target increment and the last interleaving address, only addition is needed to obtain the current interleaving address. The large number of multiplications involved in conventional second layer interleaving is not involved. And because the interleaving address is obtained by real-time calculation, the interleaving address does not need to be stored in advance, and a large amount of storage and logic resources are not occupied.

To sum up, the interleaving address obtaining method provided in the embodiment of the present application obtains a target increment of a current bit pair, where the target increment is an increment of a current interleaving address relative to a previous interleaving address, the current interleaving address is an interleaving address of the current bit pair, and the previous interleaving address is an interleaving address of the previous bit pair; and determining the current interleaving address according to the last interleaving address and the target increment. When the target increment and the last interleaving address are obtained, the current interleaving address can be obtained only by adding. The large number of multiplications involved in conventional second layer interleaving is not involved. And because the interleaving address is obtained by real-time calculation, the interleaving address does not need to be stored in advance, and a large amount of storage and logic resources are not occupied.

Referring to table 1, table 1 shows interleaving parameters of DVB-RCS2 partial code length.

Code length N	P0	P1	P2	P3	P4
						112	13	1	0	1	1
168	17	16	6	3	5
						224	25	10	15	4	15
¹⁶00	53	1	10	7	1
						¹⁷⁷⁶	59	3	8	5	1
²¹⁵⁶	65	0	3	7	0
						²³⁹⁶	81	1	2	5	2

Table 1 interleaving rules used for the second layer interleaving are as follows:

where IndexChanged indicates the position of the interleaver output, i.e. the interleaving address, mod indicates modulo the code length N, and P0, P1, P2, P3, and P4 are parameters in table 1 at different code lengths. P uses four data (0, 4 × P2, 4 × P1 × P0+4 × P3, 4 × P1 × P0+4 × P4) in a circular sequence when sequentially computing the interleaved address output. It can be seen from the calculation of the interleaver that if the calculation is direct, multiple multiplications and additions are involved, and a modulo operation is also performed.

After careful analysis of the interleaving algorithm, the inventors found that there are rules that can be utilized by machine learning, and specifically, after the code length N of a bit pair sequence is determined, the input value P of the interleaver in the interleaving algorithm has only four determined values, respectively (0, 4 × P2, 4 × P1 × P0+4 × P3, 4 × P1 × P0+4 × P4). It will be appreciated that after the sequence number j of the bit pairs is modulo 4, the above four values are selected in a cyclic order as the input values to the interleaver, j being counted incrementally from 0 to (N-1), N being the number of bit pairs in the sequence of bit pairs, and finally as the final output of the interleaving by mod (P0 x j + P +3, N). Since there is a regularity in both the input values P and j, there is also a regularity in the final output of the interleave, which is correlated with the last interleaved output value each time the output position of the next interleave (P0 × j + P +3) is calculated. The fixed difference of the current interleaving address relative to the last interleaving address, namely the target increment, can be summarized through the law.

Through careful analysis, the inventor finds that, when calculating the interleaving address of the current bit pair, the input value P of the previous bit pair and the input value P of the current bit pair are determined, and an increment can be added on the basis of the previous P to obtain the current value of P.

For example, the code length is 112, P0 13, P1 1, P2 0, P3 1, and P4 1.

If the interlace calculation formula: p0+ P +3, so:

j is 0, and the output interleaving position is (P is 0, j is 0) is 3;

j is 1, and the output interleaving position is (P4P 2, j is 1) 13 + 1+ 3-16;

j is 2, and the output interleaving position is (P4P 1P 0+ 4P 3, j 2) 56+ 13P 2+3 is 85;

j is 3, and the output interleaving position is (P4P 1P 0+ 4P 4, j is 3) 56+ 13P 3+3 is 98;

j is 4, and the output interleaving position is (P is 0, j is 4) is 0+13 is 4+3 is 55;

specifically, j is 0, (P is 0, j is 0);

and (3) pushing out: the interleaving address is 3;

let interv0 be 3; init0_ add is 0, and init0_ add represents a target increment corresponding to the interleaving address of the bit pair with j being 0;

j＝1，(P＝4*P2，j＝1)；

and (3) pushing out: the interleaving address is 4 × P2+ P0+ interv0 is 16;

let interv1 equal 16; init1_ add-interv 1-interv 0-13, init1_ add represents a target increment corresponding to the interleaving address of the bit pair whose j is 1;

j＝2，(P＝4*P1*P0+4*P3，j＝2)；

and (3) pushing out: the interleaving address is 4 × P1 × P0+4 × P3-4 × P2+ P0+ interv1 ═ 85;

let interv2 be 85; init2_ add-interv 2-interv 1-69, init2_ add represents a target increment corresponding to the interleaving address of the bit pair whose j is 2;

j＝3，(P＝4*P1*P0+4*P4，j＝3)；

and (3) pushing out: the interleaving address is 4 × P1 × P0+4 × P4-4 × P1 × P0-4 × P3+ P0+ interleaving 2 × 98;

let interv3 be 98; init3_ add-interv 3-interv 2-13, init3_ add represents a target increment corresponding to the interleaving address of the bit pair whose j is 3;

j＝4，(P＝0，j＝4)；

and (3) pushing out: the interleaving address-4 × P1 × P0-4 × P4+ P0+ interv3 ═ 0+13 × 4+3 ═ 55;

let interv4 be 55; init4_ add-interv 4-interv 3-43, init4_ add represents a target increment corresponding to an interleaving address of a bit pair whose j is 4.

It can be concluded from the derivation that the next interleaved output is always fixed, with an increment added to the previous interleaved output. As long as 4 different interleaving increments in 4 different interleaving formula outputs are known for each code length, the next value can be derived from the last interleaving output. Therefore, for each code length interleaver, it only needs to know the four initial parameters, init1_ add, init2_ add, init3_ add, and init4_ add, to find all the interleaved output data.

Therefore, the process of calculating the interleaving output in the interleaver becomes an addition operation, and the data of the variable which is increased each time is controlled during calculation. Since a negative number appears in the increment, the code length is N, and therefore, the negative number is directly modulo to obtain the increment value of the positive number.

On the basis of fig. 3, for the content in S105, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 4, where S105 includes S105-1 and S105-2.

S105-1, performing modulus operation on the serial number of the current bit pair to 4 to obtain a modulus operation result.

It will be appreciated that the current bit pair is a bit pair other than the first bit in the sequence of bit pairs, for example, bits 2 through N-1. Modulo refers to the remainder of the division of the acquired sequence number by 4, e.g., 0, 1, 2, and 3.

S105-2, the interleaving address increment matched with the modulus result is screened out from the interleaving address increment table to be used as the target increment.

The interleaving address increment table comprises interleaving address increments corresponding to different modulus results.

It is understood that 0, 1, 2, and 3 correspond to different target increments, respectively. Referring to the above example, the code length is 112, P0 is 13, P1 is 1, P2 is 0, P3 is 1, and P4 is 1. When the modulus result is 1, the target increment is init1_ add, when the modulus result is 2, the target increment is init2_ add, when the modulus result is 3, the target increment is init3_ add, and when the modulus result is 4, the target increment is init4_ add.

From the foregoing analysis, it can be seen that init1_ add, init2_ add, init3_ add and init4_ add corresponding to different code lengths are different, that is, different interleaving address increment tables correspond to different code lengths. In order to accurately obtain the interleaving address, on the basis of fig. 4, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 5, before S105, the interleaving address obtaining method includes: s101 and S102.

S101, acquiring the code length of the bit pair sequence to be interleaved.

Wherein the code length represents the number of bit pairs in the sequence of bit pairs to be interleaved.

Referring to table 1, the code length may be, for example, 112, 168, 224, 1600, 1776, 2156, and 2396, but this example only shows a part, and the code length may be other values.

And S102, matching the corresponding interleaving address increment table according to the code length.

It should be noted that, an interleaving address increment table corresponding to different code lengths may be preset, and the specific obtaining manner refers to the above example, which is not described herein again.

On the basis of fig. 3, regarding how to obtain the interleaving address of the first bit pair in the bit pair sequence to be interleaved, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 6, and the interleaving address obtaining method further includes S104.

And S104, acquiring the interleaving address of the first bit pair in the bit pair sequence to be interleaved according to an interleaving address calculation formula.

Alternatively, the interleave address calculation formula is, for example, P0 × j + P + 3.

When the length of the bit pair sequence is too long, the interleaving efficiency of a single row for the bit pair sequence is low, and as to how to improve the interleaving efficiency, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 6 again, and the interleaving address obtaining method further includes S103.

S103, splitting the bit pair sequence to be interleaved into at least two equal-length sub-paragraphs, and interleaving the at least two equal-length sub-paragraphs in parallel.

Optionally, interleaving is performed on two subsegments of equal length in parallel. In order to output the interleaved position information of the two segments simultaneously, the interleaved output needs to be calculated in real time according to the segment of the sequence number j. Since N is divided into two equal-length segments N/2, j is also divided into 0 (N/2-1) and N/2 (N-1).

For the decoding divided into two sections, the interleaving positions of the decoding are the same as the interleaving output of the incremental, and the only difference is that the starting positions of the interleaving output of the two sections are different.

Therefore, two parallel interleaving outputs can be obtained only by initializing the interleaving outputs of two sections of data into different values.

Taking the example of dividing the bit pair sequence to be interleaved into two sub-segments, a block diagram of parallel interleaving real-time computation is shown in fig. 7: start _ pos1 and start _ pos2 are respectively interleave addresses of starting positions of interleave positions j segmented into two parallel paths.

It can be known from fig. 7 that, in two-way parallel computation, only the interleaving addresses of the start positions of the used parameters are different, but the other parameters are the same, and the incremental addition modules of the computation are completely the same, so that the method can be easily extended to the interleaving structure of the multi-path parallel decoding according to the structure, and what is different is to calculate the interleaving positions of the start positions of the non-multi-path parallel segments in advance, so that the other parameters can be reused. Therefore, the structure has good expansibility and parameter reusability, and only 4 parameters need to be saved in advance.

The embodiment of the present application further provides a de-interleaving method, please refer to the following. By the interleaving address obtaining method provided by the embodiment of the application, how to output the interleaving position in real time is already known. In turbo decoding, interleaving and deinterleaving always require circular switching in each iteration. That is, in each iteration process, two times of decoding are required, when decoding for the first time, the input information is prior probability information of last time de-interleaving, and the posterior probability information obtained by the decoding result is interleaved to become prior probability information and is stored for the second time of decoding. And in the second decoding, the prior probability information of the first decoding result is used, the decoding result obtains the posterior probability information, and the posterior probability information is obtained by de-interleaving and is changed into the prior probability information which is used as the prior probability information input by the first decoding of the next iteration.

From the decoding process, in the iteration process, the prior information is obtained by interleaving or deinterleaving the posterior probability information of the last decoding result. In order to obtain the position of the deinterleave in real time, the inventor analyzes the algorithm of the deinterleave and finds that the deinterleave is just in an inverse relation with the interleaving position information and the access sequence. That is, the interleaved position output result (interleaved address) is used as the access address of the block storage of the write buffer, and the interleaved serial number j of the sequential access is used as the content of the write buffer, and the position information with the interleaved output number of N is inversely stored. Then the buffer is sequentially accessed to obtain interleaved position information. A block diagram embodying interleaving and deinterleaving is shown in fig. 8.

The inventor obtains the interleaving address acquisition method and the computing structure provided by the embodiment of the application in the analysis of the computing formula of interleaving and deinterleaving of DVB-RCS2, and the computing mechanism is a real-time and simple computing structure which can be expanded to any multi-path and parallel interleaving/deinterleaving. The interleaving address acquisition method saves storage resources in implementation, simplifies a calculation formula, provides a feasible and practical implementation structure for a key module interleaving/de-interleaving device in high-speed decoding of turbo code decoding, and has high practical value.

In parallel decoding for turbo, the MAX-LOG-MAP decoding algorithm in a sliding window mode or the modified MAX-LOG-MAP algorithm with the addition of normalization parameters is adopted, and the turbo code for DVB-RCS2 is a tail biting code. The size of the sliding window is usually a small value, the minimum window size is 40, and the decoding loss is less than 0.3 db. In the scheme of the application, the size of the window is combined with the decoding efficiency and the system bandwidth, and the size of the window is reduced as much as possible under the condition of meeting the system bandwidth. Because the smaller the window, the smaller the logic resources required for the operation in the MAX-LOG-MAP algorithm. Because turbo codes are decoded using accumulation iteration, the final data appears to be incremented after multiple iterations of accumulation. Therefore, the larger the window is, the larger the storage bit width is required, so that overflow in the accumulation process is avoided, and the structure of the interleaver is also applicable.

Compared with the prior art, the interleaving address acquisition method provided by the embodiment of the application has at least the following advantages:

the first point is that the method for acquiring interleaving/deinterleaving of turbo codes in real time saves a method for storing interleaving addresses, does not need block rom resources to specially store interleaving position information, outputs the interleaving/deinterleaving position information in real time, consumes less logic resources and only needs dozens of LUTs (look-up tables);

and secondly, the interleaving/de-interleaving real-time acquisition method of the turbo code changes the multiplication and addition operation into simple modular operation after accumulation and summation, thereby simplifying the design.

And thirdly, the interleaving/deinterleaving real-time acquisition method of the turbo code combines interleaving and deinterleaving without increasing logic resources, and outputs interleaving and deinterleaving position information in real time.

And fourthly, the real-time acquisition method of the interleaving/deinterleaving of the turbo code is easy to carry out multi-path parallel calculation, does not obviously increase logic resources, and can be easily expanded to any, multi-path and parallel real-time calculation of the interleaving/deinterleaving.

Referring to fig. 9, fig. 9 is a schematic diagram of an interleaved address obtaining apparatus according to an embodiment of the present application, where optionally, the interleaved address obtaining apparatus is applied to an electronic device as described above.

The interleave address acquisition device includes: a processing unit 201 and a calculation unit 202.

The processing unit 201 is configured to obtain a target increment of a current bit pair, where the target increment is an increment of a current interleaving address relative to a previous interleaving address, the current interleaving address is an interleaving address of the current bit pair, and the previous interleaving address is an interleaving address of the previous bit pair. Alternatively, the processing unit 201 may execute S105 described above.

The calculating unit 202 is configured to determine a current interleaving address according to a previous interleaving address and a target increment. Alternatively, the calculation unit 202 may execute S106 described above.

In a possible implementation manner, the processing unit 201 is further configured to perform modulo operation on the sequence number of the current bit pair by 4 to obtain a modulo result; screening an interleaving address increment matched with the modulus taking result from the interleaving address increment table to be used as a target increment; the interleaving address increment table comprises interleaving address increments corresponding to different modulus results. Alternatively, the processing unit 201 may perform S105-1 and S105-2 described above.

In a possible implementation manner, the processing unit 201 is further configured to obtain a code length of the bit pair sequence to be interleaved, where the code length represents a number of bit pairs in the bit pair sequence to be interleaved; and matching the corresponding interleaving address increment table according to the code length. Alternatively, the processing unit 201 may execute S101 and S102 described above.

It should be noted that the interleaving address obtaining apparatus provided in this embodiment may execute the method flows shown in the above method flow embodiments to achieve the corresponding technical effects. For the sake of brevity, the corresponding contents in the above embodiments may be referred to where not mentioned in this embodiment.

The embodiment of the present application further provides a storage medium, where the storage medium stores a computer instruction and a program, and the computer instruction and the program, when read and executed, execute the interleaving address obtaining method of the foregoing embodiment. The storage medium may include memory, flash memory, registers, or a combination thereof, etc.

The following provides an electronic device, which may be a server or a computer, and as shown in fig. 2, the electronic device may implement the above-mentioned interleaved address obtaining method; specifically, the electronic device includes: processor 10, memory 11, bus 12. The processor 10 may be a CPU. The memory 11 is used for storing one or more programs, and when the one or more programs are executed by the processor 10, the interleaved address acquisition method of the above-described embodiment is performed.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A method for obtaining an interleaved address, the method comprising:

2. The interleaved address deriving method of claim 1 wherein said step of deriving a target increment for a current bit pair comprises:

performing modulus operation on the serial number pair 4 of the current bit pair to obtain a modulus operation result;

screening an interleaving address increment matched with the modulus result from an interleaving address increment table to serve as the target increment;

and the interleaving address increment table comprises interleaving address increments corresponding to different modulus results.

3. The interleaved address retrieval method of claim 2 wherein prior to retrieving the target increment for the current bit pair, the method further comprises:

acquiring a code length of a bit pair sequence to be interleaved, wherein the code length represents the number of bit pairs in the bit pair sequence to be interleaved;

and matching a corresponding interleaving address increment table according to the code length.

4. The interleaved address retrieval method of claim 1 wherein prior to retrieving the target increment for the current bit pair, the method further comprises:

and acquiring the interleaving address of the first bit pair in the bit pair sequence to be interleaved according to an interleaving address calculation formula.

5. The interleaving address obtaining method of claim 4, wherein before obtaining the interleaving address of the first bit pair in the bit pair sequence according to the interleaving address calculation formula, the method further comprises:

and splitting the bit pair sequence to be interleaved into at least two equal-length sub-paragraphs, and interleaving at least two equal-length sub-paragraphs in parallel.

6. An interleaved address retrieval apparatus, comprising:

7. The interleaved address obtaining apparatus of claim 6 wherein the processing unit is further configured to modulo 4 a sequence number of the current bit pair to obtain a modulo result; screening an interleaving address increment matched with the modulus result from an interleaving address increment table to serve as the target increment; and the interleaving address increment table comprises interleaving address increments corresponding to different modulus results.

8. The interleaving address obtaining method according to claim 7, wherein said processing unit is further configured to obtain a code length of a bit pair sequence to be interleaved, wherein said code length represents a number of bit pairs in the bit pair sequence to be interleaved; and matching a corresponding interleaving address increment table according to the code length.

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-5.

10. An electronic device, comprising: a processor and memory for storing one or more programs; the one or more programs, when executed by the processor, implement the method of any of claims 1-5.