CN113948618A - Mini/micro LED chip applying Damascus process and manufacturing method thereof - Google Patents
Mini/micro LED chip applying Damascus process and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of LEDs, in particular to a mini/micro LED chip applying a Damascus process and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: depositing a first passivation layer, polishing, depositing SiNxCorroding the barrier layer, depositing a second passivation layer, etching a welding wire electrode pattern, manufacturing a welding pad electrode, polishing the surface electrode, thinning the sapphire, finally polishing, carrying out invisible cutting and splitting to finish the chip manufacturing. According to the invention, the pad tin electrode of the mini/micro LED is manufactured by adopting a Damascus method, etching of a metal layer is not needed, a thick electrode can be manufactured, the pattern precision is high, negative glue stripping or tin paste brushing at the packaging end can be avoided, and the process stability is improved; the method of combining the magnetron sputtering seed layer and the electroplating can avoid using a metal evaporator, and has no pollutionThe problem of the evaporator and maintenance, and low manufacturing cost.
Description
Technical Field
The invention relates to the technical field of LEDs, in particular to a mini/micro LED chip applying a Damascus process and a manufacturing method thereof.
Background
In the existing mini/micro LED chip, an Au electrode is usually adopted at a bonding pad electrode part, the process is a traditional mode for manufacturing an LED, but for the mini/micro LED chip, a thick tin electrode is usually required at a chip packaging end, and the thickness is usually required to be more than 20 μm.
At present, the thick tin electrode is realized in two ways, one way is to manufacture the thick tin electrode by utilizing the traditional negative photoresist stripping technology at the chip end, and the method has several defects, firstly, a very thick negative photoresist is needed, which brings difficulty to the chip manufacture, and firstly, the photoresist which can reach the thickness is very expensive; secondly, the resolution ratio of the negative photoresist is lower than that of the positive photoresist, and the photoetching precision is more difficult to ensure due to the large thickness; thirdly, because tin is a low-melting-point metal, when the thickness is very thick, the conventional electron beam evaporation is very easy to cause pollution of the evaporation machine, and the maintenance cost of the evaporation machine is greatly increased. In another way, the surface of the electrode is brushed with solder paste at the end of the package, but because the mini/micro LED chip has a very small size and the electrode is also very small, the precision of the steel mesh for brushing the solder paste is required to be very high, which is very difficult for the package of the chip and increases the cost.
In view of the above, it is necessary to find a mini/micro LED chip and a manufacturing method thereof that have stable process, high precision, no pollution, and low cost.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a mini/micro LED chip applying a Damascus process and a manufacturing method thereof, wherein the manufacturing method adopts the Damascus process to manufacture a pad tin electrode of the mini/micro LED, can avoid using negative glue to strip or brushing tin paste on a packaging end, can manufacture a thick electrode, has high precision, improves the stability of the process and is convenient for a client to apply; the mode of combining the seed layer sputtering and the electroplating is adopted, so that the use of a metal evaporator is fundamentally avoided, the problem of pollution to the evaporator is avoided, and the maintenance cost is low.
Before the Damascus process is carried out on the mini/micro LED chip, the procedures of growing an epitaxial layer, bonding the mini/micro LED epitaxial wafer and a sapphire substrate, removing a substrate, manufacturing a table top, manufacturing a P electrode, manufacturing an N electrode and manufacturing an isolation channel are carried out.
The invention provides a method for manufacturing a mini/micro LED chip by applying a Damascus process, which comprises the following steps:
s1, depositing a first passivation layer: using PECVD (plasma enhanced chemical vapor deposition) technology to deposit SiO on the surface of the epitaxial wafer with the manufactured isolation channel2；
S2, polishing a first passivation layer: polishing the first passivation layer by using a surface chemical mechanical polishing technology;
s3, SiN depositionxCorrosion barrier layer: deposition of SiN on the polished first passivation layer by HDPECVD (high-density plasma enhanced chemical physical deposition) techniquex(silicon carbide) and then in SiN using a positive tone lithographic masking techniquexMaking contact hole patterns, and removing the photoresist after etching;
s4, depositing a second passivation layer: SiN after S3 processing using PECVD techniquesxDeposition of SiO on surfaces and contact holes2；
S5, etching a welding line electrode pattern: making contact hole pattern by using photoetching mask technology, using positive photoresist as mask, ICP (photoetching mask) etching to obtain contact hole, in the course of etching, using SiO2And SiNxEtching rateWith different rates, some stopping at SiNxOn the layer, and on the SiNxThe opening part is continuously etched till the P/N electrode, and the photoresist is removed after the pattern etching is finished;
s6, manufacturing a pad electrode: depositing Ti, Au and Ni on the surface in sequence by using a magnetron sputtering technology; then, using TiAuNi as a seed layer, and electroplating an upper pad electrode Sn on the surface by using an electroplating technology;
s7, polishing surface electrodes: polishing to SiO of the second passivation layer by using Damascus process2The layer naturally stops;
and S8, thinning the sapphire, polishing, carrying out laser invisible cutting and splitting, and finishing chip manufacturing.
According to the technical scheme, the solder pad tin electrode of the mini/micro LED is manufactured by adopting the Damascus process, the problem that electrode metal is difficult to etch is avoided, a thick electrode can be manufactured, the size precision is high, and meanwhile, when a contact hole is etched, SiN is usedxAs a corrosion barrier layer, the opening size of the contact hole can be well controlled, and thick SiO is prevented from being etched2In time, the contact hole is deformed due to the side etching; the mode of combining the seed layer sputtering and the electroplating is adopted, so that the use of a metal evaporator can be fundamentally avoided, and the problems of pollution and maintenance of the evaporator are avoided.
Further, in the above technical solution S1, the depositing SiO is performed2The thickness of (2) is 5-6 μm, and the refractive index is controlled to be 1.45-1.46.
Further, in the above technical solution S2, after the polishing treatment, the surface roughness is controlled to be 1 to 5 nm.
Further, in the above technical solution S2, the condition of the surface chemical mechanical polishing process is as follows: working pressure is 1.5-2.5psi, upper disc rotation speed is 100 + -5 rpm, lower disc rotation speed is 90 + -5 rpm, polishing time is 5-8min, and the abrasive material is spherical SiO with diameter of 30-50nm2。
Further, in the above technical solution S4, the depositing SiO is performed2The thickness of (A) is 15-20 μm, and the refractive index is controlled to be 1.45-1.46.
Further, in the above technical solutions S1 and S4, the PECVD technique is performed by a process parameterThe numbers are as follows: the reaction gas is SiH4And N2O, flow ratio of 1:4, carrier gas N2The radio frequency power is 50-60W and the cavity pressure is 90-110Pa, accounting for 50% of the total gas flow. The chemical mechanical polishing method is adopted in the technical scheme, so that the problems of poor pattern appearance, difficulty in controlling photoetching conditions, difficulty in removing photoresist and the like caused by negative photoresist stripping can be solved.
Further, in the above technical means S6, the thicknesses of Ti, Au, and Ni are 30nm, 50nm, and 100nm, respectively.
Further, in the above technical means S6, the thickness of the pad electrode Sn is greater than 20 μm. The thickness of the tin electrode of the bonding pad manufactured in the technical scheme is more than 20 mu m, so that the packaging requirement of a mini/micro LED chip can be met.
Furthermore, in the above technical solution S8, the thickness is reduced by mechanical grinding to a thickness of 80-100 μm.
The invention also provides a mini/micro LED chip applying the Damascus process, which is prepared by the Damascus process manufacturing method.
Compared with the prior art, the invention has the following beneficial effects:
1. the method adopts the Damascus method to manufacture the tin electrode of the bonding pad of the mini/micro LED, does not need to etch a metal layer, avoids the problem that the electrode metal is difficult to etch, has the advantages of the Damascus process, can manufacture a thick electrode, has high pattern precision, can avoid using negative glue to strip or brushing tin paste at a packaging end, improves the stability of the process, and is convenient for the application of a client.
2. The invention adopts a mode of combining the magnetron sputtering seed layer and the electroplating, can fundamentally avoid using a metal evaporator, and has no problems of polluting the evaporator and maintaining.
3. The invention utilizes positive photoresist and oxide film (SiO)2) In combination, the resolution of the pattern can be improved.
4. The invention utilizes the chemical mechanical polishing method to avoid the problems of poor pattern appearance, difficult control of photoetching conditions, difficult photoresist stripping and the like caused by using negative photoresist stripping.
5. The manufacturing method has the advantages of stable process, high dimensional precision, no pollution to an evaporation machine and low cost.
Drawings
FIG. 1 is a schematic cross-sectional structure diagram of the structure obtained in S1 in the method for manufacturing a mini/micro LED chip by using a damascene process according to the present invention;
FIG. 2 is a schematic cross-sectional structure diagram of the structure obtained in S2 in the method for manufacturing the mini/micro LED chip by using the damascene process;
FIG. 3 is a schematic cross-sectional structure diagram of a structure obtained after SiNx is deposited and a photolithography film is coated on S3 in the method for manufacturing a mini/micro LED chip by applying a Damascus process;
FIG. 4 is a schematic cross-sectional structure diagram of a structure obtained after a contact hole is etched and a photoresist film is removed by S3 in the method for manufacturing a mini/micro LED chip by applying a Damascus process;
FIG. 5 is a schematic cross-sectional structure diagram of the structure obtained in S4 in the method for manufacturing a mini/micro LED chip by using a damascene process according to the present invention;
FIG. 6 is a schematic cross-sectional structure diagram of the structure obtained in S5 in the method for manufacturing a mini/micro LED chip by using a damascene process according to the present invention;
FIG. 7 is a schematic cross-sectional structure diagram of the structure obtained in S6 in the method for manufacturing a mini/micro LED chip by using a damascene process according to the present invention;
FIG. 8 is a schematic cross-sectional structure view of the structure obtained in S7 in the method for manufacturing a mini/micro LED chip using a damascene process according to the present invention.
Number designations in the schematic drawings illustrate that:
1. an epitaxial layer; 2. a sapphire substrate; an N electrode; a P electrode; 5. a first passivation layer; SiNx(ii) a 7. Photoresist; 8. a second passivation layer; a TiAuNi seed layer; 10. and a pad electrode Sn.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be understood that the terms "first", "second", etc. are used to define the components, and are used only for the convenience of distinguishing the corresponding components, and if not otherwise stated, the terms have no special meaning, and thus, should not be construed as limiting the scope of the present application.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Referring to fig. 1 to 8, it should be noted that the drawings provided in the present embodiment are only schematic illustrations of the basic idea of the present invention, and only show the components related to the present invention rather than drawn according to the number, shape and size of the components in actual implementation, the shape, number and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The invention provides a method for manufacturing a mini/micro LED chip by applying a Damascus process, which specifically comprises the following steps:
s01, growing an epitaxial layer: on a GaAs substrate, a GaAs buffer layer, a GaInP corrosion stop layer, a GaAs ohmic contact layer, a GaInP electrode protection layer, an AlGaInP current extension layer, an AlInP confinement layer, a first AlGaInP waveguide layer, a multi-quantum well structure (MQW), a second AlGaInP waveguide layer, an AlInP confinement layer, a transition layer, and a GaP window layer are epitaxially grown in this order using MOCVD (metal organic chemical vapor deposition) technology.
Specifically, the thickness of the AlGaInP current spreading layer is controlled to be between 3 and 3.5 mu m; the thickness of the first AlGaInP waveguide layer is 100nm +/-5 nm; the thickness of the second AlGaInP waveguide layer is 90nm +/-5 nm; the thickness of the GaP window layer is 9 μm.
S02, bonding an epitaxial layer and a sapphire substrate: 3 mu m of SiO is respectively deposited on the lower surface of the GaAs substrate of the epitaxial layer and the surface of the sapphire substrate2Then to SiO2After the layers are surface polished, the epitaxial layers are bonded to the sapphire. Specifically, the surface of the epitaxial layer is roughened before deposition of SiO2, wherein the roughening solution is an iodic acid solution, the iodic acid solution comprises iodic acid, sulfuric acid, hydrofluoric acid and water, and the roughening depth is 0.3-0.5 μm.
S03, removing the substrate: using NH4OH:H2O2:H2And removing the substrate by using the solution with the volume ratio of O being 1:5: 5.
Specifically, the reaction is stopped until the GaInP etch stop layer is stopped, and then the GaInP etch stop layer is rinsed with hydrochloric acid until removed, and after the GaInP etch stop layer is removed, the GaAs ohmic contact layer is exposed.
S04, manufacturing a table top: ICP etching is used.
Specifically, firstly, a mesa pattern is manufactured by using a photoetching mask technology, a photoresist is used as a mask, an ICP is used for etching the mesa, the depth of the mesa is controlled to be 5.5-6.5 mu m, and the etching gas is Cl2/BCl3/HBr。
S05.P electrode manufacturing: and manufacturing the P electrode by using a negative photoresist stripping technology.
Specifically, a P electrode pattern is made by using photoresist, then metal is evaporated to the surface of wafer by using an electron beam evaporation technology, and then the photoresist is removed; the metal on the photoresist is removed along with the photoresist, so that the metal with a specific pattern is left as an electrode, wherein negative photoresist stripping is adopted to have the characteristic of uniform and consistent electrode patterns, the electrode material comprises Au, AuZn or AuBe, and the thickness is 700-1000 nm.
S06.N electrode manufacturing: and manufacturing the N electrode by negative photoresist stripping and electron beam evaporation technology.
Specifically, GaAs on the surface is etched into a specific shape by using a photolithographic mask etching technique, and then H is used3PO4：H2O2：H2Corroding by using a solution with the volume ratio of O being 1:1:3, stripping by using negative glue, and manufacturing an N electrode by combining an electron beam evaporation technology, wherein the latter half process is consistent with the process of the P electrode; the electrode comprises Au, AuGeNi or AuGe with the thickness of 500-1000 nm.
S07, isolation channel manufacturing: ICP etching is used.
Specifically, firstly, a photoetching mask technology is utilized to manufacture an isolation channel pattern, photoresist is utilized as a mask, ICP is utilized to etch the isolation channel, and the isolation channel is etched till a bonding layer SiO2Wherein the etching gas is Cl2/BCl3/HBr。
S1, depositing a first passivation layer: depositing SiO on the surface of the epitaxial wafer with the isolation channel manufactured by using PECVD technology2(ii) a The schematic cross-sectional structure of the resulting structure is shown in FIG. 1.
In particular, the SiO is deposited using PECVD techniques2The thickness is 5-6 μm, and the refractive index is controlled between 1.45-1.46; the reaction gas used in the PECVD technology is SiH4And N2O, flow ratio of 1:4, carrier gas N2The total gas flow is 50%, the radio frequency power is 50-60W, and the cavity pressure is 90-110 Pa.
S2, polishing a first passivation layer: polishing the first passivation layer by using a surface Chemical Mechanical Polishing (CMP) technology; the schematic cross-sectional structure of the resulting structure is shown in fig. 2.
Specifically, during polishing, the working pressure is 1.5-2.5psi, the upper disc rotating speed is 100 plus or minus 5rpm, the lower disc rotating speed is 90 plus or minus 5rpm, and the polishing time is 5-8 min; the abrasive material uses spherical SiO with diameter of 30-50nm2. In general, the ratio of the polishing solution may be: 25g of grinding material, 3g of inorganic base, 140mL of 40% silica gel and 10.5g of additive; after polishing, the surface roughness is controlled to be 1-5 nm.
S3.Deposition of SiNxCorrosion barrier layer: deposition of SiN on the polished first passivation layer by HDPECVD techniquexThen using positive photolithographic masking technique on SiNxManufacturing a contact hole pattern, and removing the photoresist 7 after etching; schematic cross-sectional structures of the resulting structures are shown in fig. 3-4.
S4, depositing a second passivation layer: SiN after S3 processing using PECVD techniquesxDeposition of SiO on surfaces and contact holes2(ii) a The schematic cross-sectional structure of the resulting structure is shown in fig. 5.
In particular, the SiO is deposited using PECVD techniques2The thickness of (A) is 15-20 μm, and the refractive index is controlled to be 1.45-1.46; the reaction gas used for PECVD is SiH4And N2O, flow ratio is 1:4, carrier gas is N2The radio frequency power is 50-60W and the cavity pressure is 9-110Pa, accounting for 50% of the total gas flow.
S5, etching a welding line electrode pattern: making contact hole pattern by using photoetching mask technology, using positive photoresist as mask, ICP etching to obtain contact hole, and in the course of etching, utilizing SiO2And SiNxThe etch rate is different, with a portion stopping on SiNxOn the layer, and on the SiNxThe opening part is continuously etched till the P/N electrode, and the photoresist is removed after the pattern etching is finished; the schematic cross-sectional structure of the resulting structure is shown in fig. 6.
S6, manufacturing a pad electrode: depositing Ti, Au and Ni on the surface in sequence by using a magnetron sputtering technology; then, using TiAuNi as a seed layer, and electroplating an upper pad electrode Sn on the surface by using an electroplating technology; the schematic cross-sectional structure of the resulting structure is shown in fig. 7.
Specifically, the thicknesses of Ti, Au and Ni which are sequentially deposited on the surface by using a magnetron sputtering technology are respectively 0nm, 50nm and 100 nm; and a plating technique, wherein the thickness of the surface plating pad electrode Sn is more than 20 μm. Therefore, the requirement of a thick tin electrode at the packaging end of a mini/micro LED chip can be met.
S7, polishing surface electrodes: polishing to SiO of the second passivation layer by applying Damascus process2The layer naturally stops; the cross-sectional structure of the obtained structure is schematically shown in the figureShown in fig. 8.
Specifically, during polishing, the working pressure is 1.5-2.5psi, the upper disc rotating speed is 100 +/-5 rpm, the lower disc rotating speed is 90 +/-5 rpm, and the grinding material is spherical SiO with the diameter of 30-50nm2Since the metal is in contrast to SiO2Softer, polished to SiO of the second passivation layer2Naturally stopped when SiO except for the metal electrode in the pattern2The Sn and the TiAuNi are ground and planed, and the metal electrode is embedded in SiO2In (1).
And S8, thinning the sapphire, polishing, carrying out laser invisible cutting and splitting, and finishing chip manufacturing. Specifically, mechanical grinding is used for thinning, and the thinning thickness is 80-100 μm; then, CMP polishing is carried out, when in polishing, the working pressure is 1.5-2.5psi, the rotating speed of the upper disc is 100 plus or minus 5rpm, the rotating speed of the lower disc is 90 plus or minus 5rpm, and the polishing time is 5-8 min; the abrasive material uses spherical SiO with diameter of 30-50nm2。
The invention also provides a mini/micro LED chip prepared by the method for manufacturing the LED chip by applying the Damascus process, as shown in figure 8, the mini/micro LED chip comprises a sapphire substrate 2, an epitaxial layer 1 is bonded on the sapphire substrate 2, an N electrode 3 is manufactured at one end of the epitaxial layer 1, a P electrode 4 is manufactured at the other end of the epitaxial layer 1, the N electrode and the P electrode form an epitaxial wafer of the LED, and a first passivation layer 5 and SiN are sequentially deposited on the epitaxial wafer from bottom to topx6. A second passivation layer 8, which is provided with SiN and penetrates through the second passivation layer 8 at the position corresponding to the N electrode 3 and the P electrode 4x6. In the contact hole of the first passivation layer 5, a tiarni seed layer 9 is sputtered on the side wall and the bottom of the contact hole, and a pad electrode Sn10 is embedded in the hollow part of the tiarni seed layer 9.
In conclusion, the bonding pad tin electrode of the mini/micro LED is manufactured by adopting the Damascus method, the metal layer is not required to be etched, the problem that the electrode metal is difficult to etch is avoided, the advantages of the Damascus process are achieved, the thick electrode can be manufactured, the pattern precision is high, negative glue stripping or tin paste brushing at the packaging end can be avoided, and the process stability is improved; the mode of combining the magnetron sputtering seed layer with electroplating is adopted, so that the use of a metal evaporator can be fundamentally avoided, the problems of pollution to the evaporator and maintenance do not exist, and the cost is low.
Finally, it should be emphasized that the above-described preferred embodiments of the present invention are merely examples of implementations, rather than limitations, and that many variations and modifications of the invention are possible to those skilled in the art, without departing from the spirit and scope of the invention.
Claims (10)
1. A method for manufacturing a mini/micro LED chip by applying a Damascus process is characterized by comprising the following steps:
s1, depositing a first passivation layer: depositing SiO on the surface of the epitaxial wafer with the isolation channel manufactured by using PECVD technology2；
S2, polishing a first passivation layer: polishing the first passivation layer by using a surface chemical mechanical polishing technology;
s3, SiN depositionxCorrosion barrier layer: deposition of SiN on the polished first passivation layer by HDPECVD techniquexThen using positive photolithographic masking technique on SiNxMaking contact hole patterns, and removing the photoresist after etching;
s4, depositing a second passivation layer: SiN after S3 processing using PECVD techniquesxDeposition of SiO on surfaces and contact holes2；
S5, etching a welding line electrode pattern: making contact hole pattern by using photoetching mask technology, using positive photoresist as mask, ICP etching to obtain contact hole, and in the course of etching, utilizing SiO2And SiNxThe etch rate is different, with a portion stopping on SiNxOn the layer, and on the SiNxThe opening part is continuously etched till the P/N electrode, and the photoresist is removed after the pattern etching is finished;
s6, manufacturing a pad electrode: depositing Ti, Au and Ni on the surface in sequence by using a magnetron sputtering technology; then, using TiAuNi as a seed layer, and electroplating an upper pad electrode Sn on the surface by using an electroplating technology;
s7, polishing surface electrodes: benefit toPolishing to SiO of the second passivation layer by Damascus process2The layer naturally stops;
and S8, thinning the sapphire, polishing, carrying out laser invisible cutting and splitting, and finishing chip manufacturing.
2. The method for manufacturing a mini/micro LED chip using damascene process as claimed in claim 1, wherein in S1, the deposited SiO is2The thickness of (2) is 5-6 μm, and the refractive index is controlled to be 1.45-1.46.
3. The method for manufacturing a mini/micro LED chip using damascene process as claimed in claim 1, wherein in S2, the surface roughness is controlled to 1-5nm after the polishing process.
4. The method for manufacturing a mini/micro LED chip using damascene process as claimed in claim 1, wherein in S2, the surface chemical mechanical polishing process conditions are: working pressure is 1.5-2.5psi, upper disc rotation speed is 100 + -5 rpm, lower disc rotation speed is 90 + -5 rpm, polishing time is 5-8min, and the abrasive material is spherical SiO with diameter of 30-50nm2。
5. The method for manufacturing a mini/micro LED chip using damascene process as claimed in claim 1, wherein in S4, the deposited SiO is2The thickness of (A) is 15-20 μm, and the refractive index is controlled to be 1.45-1.46.
6. The method for manufacturing a mini/micro LED chip using damascene process as claimed in claim 1, wherein in S1 and S4, the process parameters of the PECVD technique are both: the reaction gas is SiH4And N2O, the flow ratio is 1:4, the carrier gas is N2, which accounts for 50 percent of the total gas flow, the radio frequency power is 50-60W, and the cavity pressure is 90-110 Pa.
7. The method as claimed in claim 1, wherein in S6, the thicknesses of Ti, Au, and Ni are 30nm, 50nm, and 100nm, respectively.
8. The method of claim 1, wherein in S6, the thickness of the pad electrode Sn is greater than 20 μm.
9. The method for manufacturing a mini/micro LED chip using the damascene process as claimed in claim 1, wherein in S8, mechanical grinding is used for thinning, and the thinning thickness is 80-100 μm.
10. A mini/micro LED chip using a damascene process, wherein the mini/micro LED chip is manufactured by the manufacturing method of any one of claims 1 to 9.
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