CN113948125B - Pulse signal generating circuit and resistive random access memory - Google Patents
Pulse signal generating circuit and resistive random access memory Download PDFInfo
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- CN113948125B CN113948125B CN202111422140.4A CN202111422140A CN113948125B CN 113948125 B CN113948125 B CN 113948125B CN 202111422140 A CN202111422140 A CN 202111422140A CN 113948125 B CN113948125 B CN 113948125B
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- 230000008859 change Effects 0.000 claims abstract description 21
- 239000003990 capacitor Substances 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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Abstract
The invention discloses a pulse signal generating circuit, which comprises a resistance change modulation module and a shaping module, wherein the resistance change modulation module is used for modulating an input step signal by utilizing resistance change characteristics according to an input mode signal and a modulation signal and outputting a pulse modulation signal; the shaping module is used for shaping the pulse modulation signal and outputting a pulse signal; therefore, digital adjustable pulses are generated through the resistance change characteristics of the single RRAM, so that the circuit occupies less IO resources, and the cost is low.
Description
Technical Field
The present invention relates to the field of electronic technology, and in particular, to a pulse signal generating circuit and a resistive random access memory.
Background
In the related art, the existing DAC adjustable pulse generating circuit generally generates an adjustable pulse signal by using an analog-to-digital converter, and the analog-to-digital converter occupies more IO ports, i.e. more digital input amounts are needed, and particularly, a high-speed DAC generally needs more than 18 digital IO ports, which results in high cost.
Disclosure of Invention
The present invention aims to solve at least to some extent one of the technical problems in the above-described technology. Therefore, an object of the present invention is to provide a pulse signal generating circuit, which generates digital adjustable pulses through the resistive characteristics of a single RRAM, so that the circuit occupies less IO resources and has low cost.
To achieve the above object, a pulse signal generating circuit according to an embodiment of the present invention includes: the resistance change modulation module is used for modulating an input step signal by utilizing resistance change characteristics according to the input mode signal and the modulation signal and outputting a pulse modulation signal; and the shaping module is used for shaping the pulse modulation signal and outputting a pulse signal.
According to the pulse signal generating circuit provided by the embodiment of the invention, the input step signal is modulated by the resistance change characteristics according to the input mode signal and the modulation signal by the resistance change modulation module, and the pulse modulation signal is output; shaping the output pulse modulation signal by a shaping module to output a pulse signal; therefore, digital adjustable pulses are generated through the resistance change characteristics of the single RRAM, so that the circuit occupies less IO resources, and the cost is low.
In addition, the pulse signal generating circuit according to the embodiment of the present invention may further have the following additional technical features:
optionally, the pulse signal generating circuit further includes an amplifying module, where the amplifying module is connected between the resistance variable modulating module and the shaping module, and the amplifying module is configured to amplify the pulse modulated signal before the shaping module performs shaping processing on the pulse modulated signal.
Optionally, the pulse signal generating circuit further includes a clipping module, where the clipping module is configured to clip the input step signal.
Further, the resistance change modulation module includes: the resistive element is grounded at one end; one end of the first capacitor is connected with the other end of the resistance variable element and is provided with a first node, the other end of the first capacitor receives the step signal, and the first node is used as the output end of the resistance variable modulation module; and the Set/Reset pulse unit is connected with the resistive element and is used for controlling the resistive element and the first capacitor to modulate the step signal according to the mode signal and the modulation signal so as to output the pulse modulation signal through the first node.
Further, the clipping module includes: the anode of the first diode is connected with the other end of the first capacitor, and the cathode of the first diode is grounded; and the anode of the second diode is grounded, and the cathode of the second diode is connected with the other end of the first capacitor.
Further, the amplifying module includes: the positive input end of the amplifier is connected with the output end of the resistance change modulation module; the first resistor is connected between the negative input end and the output end of the amplifier; and one end of the second resistor is connected with the negative input end of the amplifier, and the other end of the second resistor is grounded.
Further, the shaping module includes a first transistor, a second transistor, a third transistor and a fourth transistor, where the control electrode of the first transistor is connected to the control electrode of the second transistor and has a second node, the first end of the first transistor is grounded, the second end of the first transistor is connected to the first end of the second transistor and has a third node, the second end of the second transistor is connected to a preset power supply, the control electrode of the third transistor is connected to the third node after being connected to the control electrode of the fourth transistor, the first end of the third transistor is grounded, the second end of the third transistor is connected to the first end of the fourth transistor and has a fourth node, the second end of the fourth transistor is connected to the preset power supply, the second node is used as an input end of the shaping module, and the fourth node is used as an output end of the shaping module.
Optionally, the first transistor and the third transistor are NMOS transistors, and the second transistor and the fourth transistor are PMOS transistors.
Optionally, the width of the pulse signal is adjusted according to the mode signal.
In order to achieve the above object, a second aspect of the present invention provides a resistive random access memory, which includes the pulse signal generating circuit described above.
According to the resistive random access memory provided by the embodiment of the invention, the digital adjustable pulse is generated through the resistive characteristics of the single RRAM, so that the circuit occupies less IO resources and the cost is low.
Drawings
FIG. 1 is a schematic circuit diagram of a prior art DAC adjustable pulse generation circuit;
FIG. 2 is a schematic circuit diagram of a pulse signal generating circuit according to one embodiment of the present invention;
fig. 3 is a waveform diagram of a pulse signal generating circuit according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In the related art, as shown in fig. 1, the digital input of the DAC adjustable pulse generating circuit is connected to the CPU or the FPGA, and is externally connected or internally connected with a voltage reference, the high-speed DAC is usually a current output type, and is externally provided with I-V conversion, so that the DAC adjustable pulse generating circuit occupies more IO ports, thereby resulting in high cost; therefore, the invention provides a pulse signal generating circuit, which modulates an input step signal by using a resistance change characteristic according to an input mode signal and a modulation signal by using a resistance change modulation module to output a pulse modulation signal; shaping the output pulse modulation signal by a shaping module to output a pulse signal; therefore, the digital adjustable pulse is generated through the resistance change characteristic of the single RRAM, so that the circuit occupies less IO resources and the cost is low.
In order that the above-described aspects may be better understood, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.
The pulse signal generating circuit of the embodiment of the present invention is described below with reference to the drawings.
Referring to fig. 2, a pulse signal generating circuit according to an embodiment of the present invention includes a resistive modulation module 100 and a shaping module 200.
The resistive modulation module 100 is configured to modulate an input step signal according to an input mode signal and a modulation signal by using resistive characteristics, and output a pulse modulation signal.
As an example, as shown in fig. 2, the resistive switching module 100 includes a resistive switching element R5, a first capacitor C1, and a Set/Reset pulse unit; one end of the resistance change element R5 is grounded; one end of the first capacitor C1 is connected to the other end of the resistive element R5 and has a first node TP1, the other end of the first capacitor C1 receives a step signal, and the first node TP1 is used as an output end of the resistive modulation module 100; the Set/Reset pulse unit is connected with the resistive element R5, and is used for controlling the resistive element R5 and the first capacitor C1 to modulate the step signal according to the mode signal and the modulation signal so as to output a pulse modulation signal through the first node TP 1.
As an embodiment, the width of the pulse signal is adjusted according to the mode signal.
In fig. 2, input is a step signal Input, which is a source of generating a pulse signal; mode control is Mode signal input for controlling the addition or subtraction of pulse signal width; modulation is the Modulation signal input; that is, the input modulation signal is matched with the input mode signal, so that the purpose that the width of the pulse signal output by each transmission of one modulation signal is changed according to the setting can be realized, wherein the width of the pulse signal and the value of the first capacitor C1 of the resistive element R5 are in linear relation, and the value of the resistive element R5 can be controlled by the mode signal and the modulation signal.
The shaping module 200 is configured to perform shaping processing on the pulse modulated signal, and output a pulse signal.
As an embodiment, the shaping module 200 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4, where the control electrode of the first transistor Q1 is connected to the control electrode of the second transistor Q2 and has a second node TP2, the first terminal of the first transistor Q1 is grounded, the second terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2 and has a third node a, the second terminal of the second transistor Q2 is connected to the preset power supply VDD, the control electrode of the third transistor Q3 is connected to the third node a after being connected to the control electrode of the fourth transistor Q4, the first terminal of the third transistor Q3 is grounded, the second terminal of the third transistor Q3 is connected to the first terminal of the fourth transistor Q4 and has a fourth node Output, the second terminal of the fourth transistor Q4 is connected to the preset power supply VDD, the second node TP2 is used as the input terminal of the shaping module 200, and the fourth node Output terminal of the shaping module 200 is used as the Output terminal of the shaping module.
Note that, the first transistor Q1 and the third transistor Q3 are NMOS transistors, and the second transistor Q2 and the fourth transistor Q4 are PMOS transistors.
As an embodiment, the pulse signal generating circuit further includes an amplifying module 300, where the amplifying module 300 is connected between the resistance modulation module 100 and the shaping module 200, and the amplifying module 300 is configured to amplify the pulse modulation signal before the shaping module 200 performs the shaping process on the pulse modulation signal.
As shown in fig. 2, the amplifying module 300 includes an amplifier A1, a first resistor R1, and a second resistor R2; the positive input end of the amplifier A1 is connected with the output end TP1 of the resistance change modulation module 100; the first resistor R1 is connected between the negative input end of the amplifier A1 and the output end TP 2; one end of the second resistor R2 is connected with the negative input end of the amplifier A1, and the other end of the second resistor R2 is grounded.
As an embodiment, the pulse signal generating circuit further includes a clipping module 400, and the clipping module 400 is configured to clip an input step signal.
As shown in fig. 2, the including clipping module 400 includes a first diode D1 and a second diode D2; the anode of the first diode D1 is connected with the other end of the first capacitor C1, and the cathode of the first diode D1 is grounded; the anode of the second diode D2 is grounded, and the cathode of the second diode D2 is connected to the other end of the first capacitor C1.
It should be noted that, fig. 3 is a schematic waveform diagram of the pulse signal generating circuit, as shown in fig. 3, the step signal Input is subjected to amplitude limiting modulation and then outputs a pulse modulation signal TP1, the pulse modulation signal TP1 is subjected to amplitude expansion of the waveform by the amplifying module 300 and then outputs a signal TP2, and the signal TP2 is subjected to waveform correction and shaping by the shaping module 200 and then outputs a pulse signal Output.
In summary, according to the pulse signal generating circuit provided by the embodiment of the invention, the resistance modulation module modulates the input step signal according to the input mode signal and the modulation signal by using the resistance characteristics, and outputs the pulse modulation signal; shaping the output pulse modulation signal by a shaping module to output a pulse signal; therefore, only three external digital inputs are needed, input signals are few, and IO resource occupation is reduced; compared with a DAC scheme, the IO resource occupation can be reduced by 80%; the cost is low, and the method is particularly suitable for multi-channel adjustable pulse generation; the generated adjustable pulse can be applied to the Set/Reset, laser source control, power control and other occasions of the RRAM array.
In addition, the embodiment of the invention also provides a resistive random access memory, which comprises the pulse signal generating circuit.
According to the resistive random access memory provided by the embodiment of the invention, the digital adjustable pulse is generated through the resistive characteristics of the single RRAM, so that the circuit occupies less IO resources and the cost is low.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms should not be understood as necessarily being directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (9)
1.A pulse signal generating circuit, comprising:
the resistance change modulation module is used for modulating an input step signal by utilizing resistance change characteristics according to the input mode signal and the modulation signal and outputting a pulse modulation signal;
The shaping module is used for shaping the pulse modulation signal and outputting a pulse signal;
wherein, the resistance change modulation module includes:
the resistive element is grounded at one end;
One end of the first capacitor is connected with the other end of the resistance variable element and is provided with a first node, the other end of the first capacitor receives the step signal, and the first node is used as the output end of the resistance variable modulation module;
And the Set/Reset pulse unit is connected with the resistive element and is used for controlling the resistive element and the first capacitor to modulate the step signal according to the mode signal and the modulation signal so as to output the pulse modulation signal through the first node.
2. The pulse signal generating circuit according to claim 1, further comprising:
The amplifying module is connected between the resistance change modulating module and the shaping module and is used for amplifying the pulse modulation signal before the shaping module performs shaping processing on the pulse modulation signal.
3. The pulse signal generating circuit according to claim 1, further comprising:
and the amplitude limiting module is used for carrying out amplitude limiting processing on the input step signals.
4. The pulse signal generating circuit of claim 3, wherein the clipping module comprises:
The anode of the first diode is connected with the other end of the first capacitor, and the cathode of the first diode is grounded;
And the anode of the second diode is grounded, and the cathode of the second diode is connected with the other end of the first capacitor.
5. The pulse signal generating circuit according to claim 2, wherein the amplifying module comprises:
the positive input end of the amplifier is connected with the output end of the resistance change modulation module;
The first resistor is connected between the negative input end and the output end of the amplifier;
And one end of the second resistor is connected with the negative input end of the amplifier, and the other end of the second resistor is grounded.
6. The pulse signal generating circuit according to claim 5, wherein the shaping module comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the control electrode of the first transistor is connected to the control electrode of the second transistor and has a second node, the first terminal of the first transistor is grounded, the second terminal of the first transistor is connected to the first terminal of the second transistor and has a third node, the second terminal of the second transistor is connected to a preset power supply, the control electrode of the third transistor is connected to the third node after being connected to the control electrode of the fourth transistor, the first terminal of the third transistor is grounded, the second terminal of the third transistor is connected to the first terminal of the fourth transistor and has a fourth node, the second terminal of the fourth transistor is connected to the preset power supply, the second node serves as the input terminal of the shaping module, and the fourth node serves as the output terminal of the shaping module.
7. The pulse signal generating circuit according to claim 6, wherein the first transistor and the third transistor are NMOS transistors, and wherein the second transistor and the fourth transistor are PMOS transistors.
8. The pulse signal generating circuit according to claim 1, wherein a width of the pulse signal is adjusted according to the mode signal.
9. A resistive random access memory comprising the pulse signal generating circuit according to any one of claims 1 to 8.
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| CN202111422140.4A CN113948125B (en) | 2021-11-26 | 2021-11-26 | Pulse signal generating circuit and resistive random access memory |
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| CN202111422140.4A CN113948125B (en) | 2021-11-26 | 2021-11-26 | Pulse signal generating circuit and resistive random access memory |
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| CN113948125A CN113948125A (en) | 2022-01-18 |
| CN113948125B true CN113948125B (en) | 2024-07-02 |
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| US8644049B2 (en) * | 2010-08-20 | 2014-02-04 | Shine C. Chung | Circuit and system of using polysilicon diode as program selector for one-time programmable devices |
| CN103680602B (en) * | 2012-09-11 | 2017-02-08 | 复旦大学 | Resistive random access memory and reset operation method thereof |
| CN103051308B (en) * | 2013-01-09 | 2015-04-29 | 武汉科技大学 | Square wave and sawtooth wave generation circuit based on memristor |
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