CN113921390A - Processing technique of wafer-level chip and wafer structure - Google Patents
Processing technique of wafer-level chip and wafer structure Download PDFInfo
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- CN113921390A CN113921390A CN202111170203.1A CN202111170203A CN113921390A CN 113921390 A CN113921390 A CN 113921390A CN 202111170203 A CN202111170203 A CN 202111170203A CN 113921390 A CN113921390 A CN 113921390A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a processing technique method of wafer level chips and a wafer structure.A chip is embedded in the front surface of a wafer, a scribing groove is arranged between adjacent chips, a convex graph structure is formed on the scribing groove area corresponding to a single chip on the back surface of the wafer, and the graph structure comprises an annular structure on the peripheral edge of the wafer and a supporting structure corresponding to the single chip; electroplating the obtained protruding graph structure to form a metal layer, and filling resin into the back of the wafer subjected to the whole corrosion thinning process for wafer-level plastic packaging so as to form a plastic packaging layer outside the metal layer; grinding the wafer after plastic packaging to a specified wafer thickness; and after grinding to the specified thickness, cutting the wafer into single chips by adopting a scribing process, and then carrying out subsequent packaging. The invention solves the packaging problem of the thinned existing ultrathin chip, reduces the thickness of the effective area of a single chip and adopts a four-side protection method, thereby achieving the beneficial effect and enhancing the whole packaging structure.
Description
Technical Field
The invention belongs to the integrated circuit packaging technology, and particularly relates to a processing method of a wafer-level chip and a wafer structure.
Background
In the wafer processing technology, the wafer is usually thinned before subsequent processing processes such as etching, chemical deposition, electroplating and the like are performed, or after two wafers are bonded, the back face of the wafer is thinned.
And the wafer thinning means that the back surface of the wafer is ground, and the redundant base material on the back surface of the wafer is removed to a certain thickness, so that the wafer is thinned to a certain thickness. In order to adapt to the trend of miniaturization of integrated circuit chip packages, it is desirable to make the thickness of the wafer very thin, i.e. to manufacture ultra-thin wafers, such as wafer thinning to 150um or even below 150 um. As applications such as memory and power devices are moving toward smaller size and higher performance, the demand for thin wafers is also increasing. Thinner wafers can provide numerous benefits, including ultra-thin packaging, and thus smaller size profiles, including improved electrical performance and better heat dissipation.
However, wafers that are too thin can present warpage and breakage problems, and wafers of larger dimensions are more susceptible to such problems.
At this stage, the most common semiconductor thinning process is grinding, for example: when the TAIKO process is adopted to grind the wafer, the edge part at the periphery of the wafer is reserved, and only the interior of the wafer is ground and thinned.
However, the TAIKO process requires a particularly fine grinding tool, for example, JP2007173487A discloses a grinding processing device, by which the central portion of the wafer is ground while the peripheral edge of the wafer is retained, but the top layer structure of the IC has more manufacturing steps, and the stress caused by mechanical grinding is liable to cause the breakage of the wafer due to the thinner structure, for example, the power device needs to be covered with polyimide about 5 μm thick, and the breakage almost occurs when the wafer is thinned to 100 μm.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to solve the defects in the prior art and provides a processing method of a wafer-level chip and a wafer structure.
The technical scheme is as follows: the invention discloses a processing technique method of a wafer-level chip, which comprises the following steps:
obtaining a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, chips are embedded in the front surface of the wafer in advance, and scribing grooves are formed between adjacent chips;
forming a convex graph structure on a scribing groove area corresponding to a single chip on the back surface of the wafer, wherein the graph structure comprises an annular structure on the peripheral edge of the wafer and a supporting structure corresponding to the single chip;
electroplating the obtained protruding graph structure to form a metal layer, and filling resin into the back of the chip subjected to the whole corrosion thinning process for wafer-level plastic packaging so as to form a plastic packaging layer outside the metal layer;
grinding the wafer after plastic packaging to a specified wafer thickness; after grinding to the specified thickness, cutting the wafer into single chips by adopting a scribing process, and then carrying out subsequent packaging.
The annular structure is located on the peripheral edge of the back face of the wafer, the supporting structure is located in the annular structure, and the supporting structure and the scribing groove area of the single chip are relatively applied to supporting the corresponding single chip.
The supporting structure corresponds to the scribing groove area of a single chip, so that the stability of the whole structure is better through the supporting structure, and the subsequent packaging and use are facilitated.
Further, a protruded pattern structure is formed on the scribing groove area corresponding to the single chip on the back surface of the wafer, and the method comprises the following steps:
coating bonding glue on the front surface of the wafer, and attaching a bonding support sheet to the front surface of the wafer;
forming a mask layer on the back surface of the wafer, and photoetching the mask layer to form a patterned photoresist layer; the patterned photoresist layer at least covers the annular part of the peripheral edge of the wafer and the scribing groove area corresponding to each chip;
performing first etching, namely removing the part, which is not covered by the photoresist layer, in the mask layer, transferring the pattern on the photoresist layer to the mask layer, and then removing the photoresist layer;
and performing second etching to remove the mask layer and partial area of the back surface of the wafer, transferring the pattern on the mask layer to the back surface of the wafer to obtain a protruding pattern structure on the back surface of the wafer, and then removing the mask layer.
Through the steps, the pattern structure on the back surface of the wafer corresponds to a single chip, the whole back surface of the whole wafer does not need to be formed in a protruding mode, the process difficulty is reduced, and the subsequent chip cutting is facilitated.
Further, a protruded pattern structure is formed on the scribing groove area corresponding to the single chip on the back surface of the wafer, and the method comprises the following steps:
forming a graphical photoresist layer on the back surface of the wafer, wherein the graphical photoresist layer at least covers the annular part of the peripheral edge of the wafer and the scribing groove area corresponding to each chip;
and carrying out third etching to obtain a convex pattern structure on the back of the wafer.
Furthermore, the longitudinal section of the area surrounded by the supporting structure of the single chip is isosceles trapezoid, and the diameter of the cross section far away from the chip is larger than that of the cross section close to the chip.
Furthermore, the longitudinal section of the scribing groove area between two adjacent chips is isosceles trapezoid, and the diameter of the cross section far away from one side of the chip is smaller than that of the cross section close to one side of the chip.
Furthermore, the mask layer is formed on the back surface of the wafer by adopting a chemical vapor deposition method and a TEOS material.
Further, the first etching is wet etching using HF.
Further, the second etching is wet etching using TMAH.
Further, the third etching is wet etching using TMAH.
Furthermore, before the protruded pattern structure is formed on the wafer back surface and the scribing groove area corresponding to the single chip, the wafer back surface is thinned by adopting a grinding or wet etching method.
The invention also discloses a wafer structure prepared by the processing technique method of the wafer-level chip, which comprises a wafer, wherein the front surface of the wafer is embedded with chips in advance, scribing grooves are arranged between adjacent chips, a convex graph structure is formed on the scribing groove area corresponding to a single chip on the back surface of the wafer, the graph structure comprises an annular structure at the peripheral edge of the wafer and a supporting structure corresponding to the single chip, the longitudinal section of the area surrounded by the supporting structure of the single chip is trapezoidal, and the diameter of the cross section of the side far away from the chip is larger than that of the cross section of the side close to the chip.
Has the advantages that: compared with the prior art, the invention has the following advantages:
(1) the invention solves the scribing problem after the thinning of the existing ultrathin chip, reduces the thickness of the effective area of a single chip and adopts a four-side protection method, thereby achieving the beneficial effect and enhancing the whole packaging structure.
(2) The thinning corrosion method can directly utilize the existing wafer level packaging equipment, can realize the ultrathin grinding of the wafer without adding new equipment, can be suitable for wafers of various sizes, has wide adaptability, saves the cost and improves the packaging efficiency.
(3) The pattern structure, particularly the supporting structure, is used for a single chip, the supporting structure is matched with the scribing groove area, the subsequent chip cutting is facilitated, the breakage and the like can be avoided, the whole back of the wafer is not needed, and the whole process efficiency is improved.
Drawings
FIG. 1 is a schematic view of an exemplary wafer;
FIG. 2 is a schematic diagram of an exemplary mask layer;
FIG. 3 is a schematic view of an exemplary photoresist layer;
FIG. 4 is a schematic diagram illustrating the mask layer after the photoresist layer is removed in the embodiment;
FIG. 5 is a schematic diagram of an exemplary embodiment of a graphic configuration;
FIG. 6 is a schematic diagram of an embodiment of a metal layer;
FIG. 7 is a schematic view of an exemplary molding layer;
FIG. 8 is a schematic diagram of a single chip in the example;
FIG. 9 is a schematic view of the entire structure of the thinned wafer in the embodiment.
Detailed Description
The technical solution of the present invention is described in detail below, but the scope of the present invention is not limited to the embodiments.
Example 1:
as shown in fig. 1 to 5, a processing method of a wafer level chip of the present embodiment includes the following steps:
forming a chip on the front surface of the provided wafer; thinning the wafer, forming a convex pattern structure on the back surface of the wafer and a scribing groove area corresponding to a single chip, electroplating the obtained convex pattern structure to form a metal layer, filling resin into the back surface of the chip subjected to the whole corrosion thinning for wafer-level plastic packaging, and forming a plastic packaging layer outside the metal layer; the pattern structure comprises an annular structure and a supporting structure, the annular structure is located on the peripheral edge of the back face of the wafer, the supporting structure is located in the annular structure, and the supporting structure and the scribing groove area of a single chip are relatively applied to supporting the corresponding single chip.
Coating bonding glue on the front surface of the wafer, and attaching a bonding support sheet to the front surface of the wafer; forming a mask layer on the back surface of the wafer, and photoetching the mask layer to form a patterned photoresist layer; then, carrying out first etching, namely removing the part which is not covered by the photoresist layer in the mask layer, transferring the pattern on the photoresist layer to the mask layer, and then removing the photoresist layer; then, second etching is carried out, the mask layer and partial area of the back surface of the wafer are removed, the pattern on the mask layer is transferred to the back surface of the wafer, and a protruding pattern structure is obtained on the back surface of the wafer; the patterned photoresist layer comprises an annular part covering the peripheral edge of the wafer and a scribing groove corresponding to each chip.
The mask layer may be a silicon dioxide layer or other material layer suitable as a mask. The mask layer may be a single layer material or a multi-layer composite material. Preferably, the mask layer is formed by chemical vapor deposition of TEOS (Tetraethyl orthosilicate) material.
The forming method of the patterned photoresist layer comprises the following steps: forming a photoresist layer on the surface of the mask layer; and etching the photoresist layer into a patterned photoresist layer by utilizing exposure and development.
In this embodiment, a wet etching process may be used for the first etching, and a corrosive capable of removing the material of the mask layer is selected to achieve the effect of transferring the pattern. Wet etching with HF may also be employed. After the first etching, removing the photoresist layer; any suitable photoresist removal process may be used to remove the photoresist layer.
In this embodiment, a wet etching process or a dry etching process may be used for the second etching, and if the wet etching process is used, a corrosive agent capable of removing the mask layer material and the wafer material is selected to achieve the effects of transferring the pattern and thinning the wafer. The second etching here is preferably a wet etching using TMAH. By adjusting the etching parameters such as time, concentration of the etching solution, temperature and the like, the thickness of the obtained projected pattern structure and the thinning degree of the wafer can be accurately controlled. If a dry etching process is adopted, gases such as SF6 and C4F8 are selected, the gases are decomposed into plasma under the action of glow discharge, and the plasma etches the silicon material so as to achieve the effects of transferring patterns and thinning the wafer.
In the embodiment, when wafer-level plastic package is performed, a scribing film is attached to the back surface; the back side of the wafer can be selectively thinned to the specified thickness of the wafer. Then debonding the front side of the wafer, and removing the bonding support sheet and the front side glue on the front side of the wafer; and finally, scribing the wafer along the scribing grooves, and scribing a single chip on the wafer to obtain a single chip with concave plastic package on the back surface as shown in figure 1.
In this embodiment, a longitudinal section of an area surrounded by the supporting structures of the single chip is an isosceles trapezoid, and a diameter of a cross section on a side far away from the chip is larger than a diameter of a cross section on a side close to the chip. Meanwhile, the longitudinal section of the scribing groove area between two adjacent chips is in an isosceles trapezoid shape, and the diameter of the cross section far away from one side of the chip is smaller than that of the cross section close to one side of the chip.
Example 2:
the difference between this embodiment and embodiment 1 is that a patterned photoresist layer is directly formed on the back surface of the wafer without using a mask layer, and accordingly, the second etching is directly performed without performing the first etching.
Example 3:
in this embodiment, on the basis of the technical solution of embodiment 1, a grinding process and a wet etching method are combined to thin the wafer. The difference from embodiment 1 is that before forming the mask layer on the back surface of the wafer, the back surface of the wafer is thinned to a certain thickness by using a grinding or wet etching method, and then the protruding pattern structure is formed on the back surface of the wafer by using the method of embodiment 1, and the wafer is thinned to a final required thickness.
Example 4:
as shown in fig. 6, this embodiment combines the back plating process with the technical solution of embodiment 1. The difference from embodiment 1 is that after the second etching is completed, back electroplating is directly performed, and the metal layer 8 subjected to back electroplating at this time may be a conductive metal such as gold, silver, titanium, copper, or the like; and then, attaching a scribing film on the back surface, and scribing the normal wafer to obtain a single chip with the back surface concave back gold as shown in the figure.
Example 5:
as shown in fig. 7 and 8, this embodiment combines the processes of back plating and wafer level plastic package based on the technical solution of embodiment 1. The difference from embodiment 1 is that after the second etching is completed, back electroplating is directly performed, and the metal layer plated on the back at this time may be conductive metal such as gold, silver, titanium, copper, and the like; then, carrying out wafer-level plastic package to form a plastic package layer 9 outside the metal layer, wherein the plastic package material is UV curing resin; and then, attaching a scribing film on the back surface, and scribing the normal wafer to obtain a single chip structure with the concave back gold plastic package on the back surface as shown in the figure.
Example 6:
as shown in fig. 9, in this embodiment, the wafer structure prepared by the processing method includes a wafer, chips are embedded in the front surface of the wafer, a scribe line is disposed between adjacent chips, a convex pattern structure is formed on a scribe line region corresponding to a single chip on the back surface of the wafer, the pattern structure includes an annular structure on the peripheral edge of the wafer and a supporting structure corresponding to the single chip, the longitudinal section of a region surrounded by the supporting structure of the single chip is trapezoidal, and the diameter of the cross section on the side far from the chip is larger than the diameter of the cross section on the side close to the chip.
In the implementation, through the graph structure and the cooperation with the scribing groove area 6, the scribing problem after the existing ultrathin chip is thinned is solved, the thickness of the effective area of a single chip is reduced, meanwhile, a four-edge protection method is adopted, the structural strength in the packaging process can be enhanced, and the final scribing is prevented from being broken.
Claims (9)
1. A processing technique method of wafer level chips is characterized in that: the method comprises the following steps:
obtaining a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, chips are embedded in the front surface of the wafer in advance, and scribing grooves are formed between adjacent chips;
forming a convex graph structure on a scribing groove area corresponding to a single chip on the back surface of the wafer, wherein the graph structure comprises an annular structure on the peripheral edge of the wafer and a supporting structure corresponding to the single chip;
electroplating the obtained protruding graph structure to form a metal layer, and filling resin into the back of the chip subjected to the whole corrosion thinning process for wafer-level plastic packaging so as to form a plastic packaging layer outside the metal layer;
grinding the wafer after plastic packaging to a specified wafer thickness; and after grinding to the specified thickness, cutting the wafer into single chips by adopting a scribing process, and then carrying out subsequent packaging.
2. The processing method of wafer level chip as claimed in claim 1, wherein: form convex figure structure on the wafer back and the corresponding scribing groove region of single chip, include:
coating bonding glue on the front surface of the wafer, and attaching a bonding support sheet to the front surface of the wafer; forming a mask layer on the back surface of the wafer, and photoetching the mask layer to form a patterned photoresist layer, wherein the patterned photoresist layer at least covers the annular part of the peripheral edge of the wafer and a scribing groove area corresponding to each chip;
performing first etching to remove the part of the mask layer which is not covered by the photoresist layer, transferring the pattern on the photoresist layer to the mask layer, and then removing the photoresist layer;
and performing second etching to remove a partial area on the back surface of the wafer, transferring the pattern on the mask layer to the back surface of the wafer to obtain a protruding pattern structure on the back surface of the wafer, and then removing the mask layer.
3. The processing method of wafer level chip as claimed in claim 1, wherein: form convex figure structure on the wafer back and the corresponding scribing groove region of single chip, include:
forming a graphical photoresist layer on the back surface of the wafer, wherein the graphical photoresist layer at least covers the annular part of the peripheral edge of the wafer and the scribing groove area corresponding to each chip;
and carrying out third etching to obtain a convex pattern structure on the back of the wafer.
4. The processing method of wafer level chip as claimed in claim 1, wherein: the longitudinal section of the area surrounded by the supporting structures of the single chip is in an isosceles trapezoid shape, and the diameter of the cross section far away from one side of the chip is larger than that of the cross section close to one side of the chip.
5. The processing method of wafer level chip as claimed in claim 2, wherein: the mask layer is formed on the back of the wafer by adopting a chemical vapor deposition method and a TEOS material.
6. The processing method of wafer level chip as claimed in claim 2, wherein: the first etching is wet etching using HF.
7. The processing method of wafer level chip as claimed in claim 2, wherein: the second etching is wet etching using TMAH.
8. The processing method of wafer level chip as claimed in claim 1, wherein: before forming the protruded pattern structure on the scribing groove area of the back surface of the wafer corresponding to the single chip, the back surface of the wafer is thinned by adopting a grinding or wet etching method.
9. A wafer structure prepared by the processing method of the wafer level chip as claimed in any one of claims 1 to 8, wherein: the wafer structure comprises a wafer, wherein chips are embedded into the front surface of the wafer in advance, scribing grooves are formed between adjacent chips, a convex graph structure is formed on a scribing groove area corresponding to a single chip on the back surface of the wafer, the graph structure comprises an annular structure at the peripheral edge of the wafer and a supporting structure corresponding to the single chip, the longitudinal section of an area surrounded by the supporting structure of the single chip is trapezoidal, and the diameter of the cross section far away from one side of the chip is larger than that of the cross section near one side of the chip.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013127035A1 (en) * | 2012-02-28 | 2013-09-06 | Liu Sheng | Fan-out wafer level semiconductor chip three-dimensional stacked package structure and process |
| CN103579020A (en) * | 2012-08-07 | 2014-02-12 | 万国半导体股份有限公司 | Packaging method for wafer-level chip |
| CN104124176A (en) * | 2013-04-24 | 2014-10-29 | 万国半导体股份有限公司 | Method for preparation of semiconductor device used in flip installing process |
| CN105448854A (en) * | 2014-08-29 | 2016-03-30 | 万国半导体股份有限公司 | Wafer manufacturing method for thickly-back-metalized molded chip-scale package |
| CN107689320A (en) * | 2016-08-05 | 2018-02-13 | 上海新昇半导体科技有限公司 | A kind of wafer thining method and thinned crystal circle structure |
| CN109346398A (en) * | 2018-09-26 | 2019-02-15 | 广西桂芯半导体科技有限公司 | A kind of ultra-thin chip production method |
| CN111653528A (en) * | 2020-07-22 | 2020-09-11 | 江苏长晶科技有限公司 | Chip packaging structure, method and semiconductor device |
-
2021
- 2021-10-08 CN CN202111170203.1A patent/CN113921390A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013127035A1 (en) * | 2012-02-28 | 2013-09-06 | Liu Sheng | Fan-out wafer level semiconductor chip three-dimensional stacked package structure and process |
| CN103579020A (en) * | 2012-08-07 | 2014-02-12 | 万国半导体股份有限公司 | Packaging method for wafer-level chip |
| CN104124176A (en) * | 2013-04-24 | 2014-10-29 | 万国半导体股份有限公司 | Method for preparation of semiconductor device used in flip installing process |
| CN105448854A (en) * | 2014-08-29 | 2016-03-30 | 万国半导体股份有限公司 | Wafer manufacturing method for thickly-back-metalized molded chip-scale package |
| CN107689320A (en) * | 2016-08-05 | 2018-02-13 | 上海新昇半导体科技有限公司 | A kind of wafer thining method and thinned crystal circle structure |
| CN109346398A (en) * | 2018-09-26 | 2019-02-15 | 广西桂芯半导体科技有限公司 | A kind of ultra-thin chip production method |
| CN111653528A (en) * | 2020-07-22 | 2020-09-11 | 江苏长晶科技有限公司 | Chip packaging structure, method and semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| SHANNON PAN ET AL.: "线键合与凸点倒装芯片晶圆用的切割蓝膜评估", 《功能材料与器件学报》, 25 October 2013 (2013-10-25) * |
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