CN113921062A - Memory and operation method thereof - Google Patents
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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Abstract
The embodiment of the application provides a memory and a programming method thereof, wherein the method comprises the following steps: applying a first program pulse to a word line of a selected memory cell to perform a first program on the selected memory cell; performing program verification on the memory cell subjected to the first programming; when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length; performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
Description
Technical Field
The present application relates to the field of memories, and relates to, but is not limited to, a memory and a method of operating the same.
Background
According to the characteristics of the semiconductor memory, it can be divided into a volatile memory that loses data stored therein when power is turned off, and a non-volatile memory that does not lose data stored therein when power is turned off. Volatile memory can have fast programming and reading speeds, but cannot store data for long periods of time; non-volatile memory enables long-term storage of data, but has relatively slow programming and reading speeds.
Due to the process and inherent characteristics of the device structure, the non-volatile memory has non-uniform programming effect on different memory cells during the programming process, which makes it difficult to achieve the desired programming and verifying effects.
Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a memory and an operating method thereof.
In a first aspect, an embodiment of the present application provides an operating method of a memory, where the method includes:
applying a first program pulse to a word line of a selected memory cell to perform a first program on the selected memory cell;
performing program verification on the memory cell subjected to the first programming; wherein,
when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length;
performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
In some embodiments, the first sensing duration is less than the second sensing duration.
In some embodiments, the program verify includes at least two verifications: a first program verify and a second program verify, wherein the first program verify is a first verify in a current program loop;
performing program verification on the first programmed memory cell includes:
applying a first verification voltage to a word line of the memory cell subjected to the first programming, the first program verification being performed based on the first sensing duration;
applying a second verification voltage to the word line of the memory cell subjected to the first programming, the second program verifying being performed based on the second sensing duration.
In some embodiments, the second verify voltage is greater than the first verify voltage.
In some embodiments, the first programmed memory cells include a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell are memory cells having different program target states;
performing a first verification based on a first sensing duration, including performing a first program verification on a first memory cell based on the first sensing duration;
performing a second verification based on a second sensing duration includes performing a second program verification on a second memory cell based on the second sensing duration.
In some embodiments, the at least two verifications further include a third program verify, the third program verify being performed after the first program verify and the second program verify;
performing program verification on the first programmed memory cell further includes:
applying a third verification voltage to the word line of the first programmed memory cell, the third program verification being performed based on the third sensing duration; wherein the third sensing duration is different from the first sensing duration.
In some embodiments, the third sensing duration is the same as the second sensing duration.
In some embodiments, the program verify includes only one verify: a fourth program verify; performing program verification on the first programmed memory cell includes:
a fourth program verify is performed based on the first sensing duration.
On the other hand, an embodiment of the present application further provides a memory, which includes:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to:
applying a first program pulse to a word line of a selected memory cell to perform a first program on the selected memory cell;
performing program verification on the memory cell subjected to the first programming; wherein,
when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length;
performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
In some embodiments, the plurality of memory cells includes a first memory cell and a second memory cell;
performing a first verification based on a first sensing duration, including performing a first program verification on a first memory cell based on the first sensing duration;
performing a second verification based on a second sensing duration includes performing a second program verification on a second memory cell based on the second sensing duration.
According to the technical scheme provided by the embodiment of the application, after the memory is programmed, the memory unit can be verified once or for many times, and the verification for many times aims at different programming states and adopts different induction time lengths. Therefore, on one hand, the accuracy and comprehensiveness of verification can be improved; on the other hand, the influence of the verification process on the memory cells in different states can be reduced by adopting different sensing time lengths for verification, and the programming quality is improved.
Drawings
FIG. 1 is a flowchart of a method for programming a memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of incremental step pulse programming provided by an embodiment of the present application;
FIG. 3 is an alternative schematic diagram of a memory cell threshold voltage distribution provided by an embodiment of the present application;
FIG. 4 is an alternative schematic diagram of a memory cell threshold voltage distribution provided by an embodiment of the present application;
FIG. 5 is an alternative schematic diagram of a memory cell threshold voltage distribution provided by an embodiment of the present application;
fig. 6 is a flowchart of verification based on different sensing durations according to an embodiment of the present disclosure;
fig. 7 is a flowchart of verification based on different sensing durations according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a memory according to an embodiment of the present application.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, an embodiment of the present application provides a method for programming a memory, where the method includes:
step S101, applying a first programming pulse to a word line of a selected memory cell, and performing first programming on the selected memory cell;
step S102, performing programming verification on the memory cell subjected to the first programming; step S102 may include the following two cases:
when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length;
performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
In the embodiment of the present application, due to process variations and performance differences of the memory cells themselves, different threshold voltages may be reached after each programming voltage application, and thus different programming states may be entered. Thus, the memory cell can be verified one or more times after each application of a programming pulse to determine whether the memory cell has been programmed into a target state. Moreover, because different memory cells have different target states, the programming can be performed through multiple programming cycles, and one to multiple verifications are performed after each programming cycle, and for the memory cells which pass the verification and have entered the target state, the programming can be inhibited, and other memory cells which do not enter the target state can be continuously subjected to the cycles of programming and verification.
The sensing duration used in the verification process may be different in consideration of the different verification voltages in different states. In the embodiment of the present application, the sensing durations corresponding to the first program verification (i.e., the first verification) and the non-first program verification performed after the program pulse is applied in each program loop may be different. In one embodiment, the first sensing duration is less than the second sensing duration. I.e., the sensing duration for the first program verify is short, such verify conditions are relaxed, i.e., have large margins. And for the non-first programming verification, a longer verification time is adopted, so that the verification accuracy is ensured, and the program is continuously inhibited from the memory cell which reaches the target state.
Therefore, on one hand, the programming efficiency can be improved, and on the other hand, flexible verification can be performed in consideration of the performances of different memory cells, so that the occurrence of programming errors is reduced.
In some embodiments, the program verify includes at least two verifications: a first program verify and a second program verify, wherein the first program verify is a first verify in a current program loop;
performing program verification on the first programmed memory cell further includes:
applying a first verification voltage to a word line of the memory cell subjected to the first programming, the first program verification being performed based on the first sensing duration;
applying a second verification voltage to the word line of the memory cell subjected to the first programming, the second program verifying being performed based on the second sensing duration.
In an embodiment, the second verify voltage is greater than the first verify voltage.
For example, a first program pulse may be applied to a word line of a memory cell to be programmed, performing a first program on the memory cell; sequentially applying at least two verify pulses to the word lines of the memory cells to verify at least two states of the memory cells; wherein, the induction time lengths adopted when the at least two states are verified are different; and performing second programming according to the verification results of the at least two states.
In some embodiments, the first programmed memory cells include a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell are memory cells having different programmed target states (i.e., different target states). Performing a first verification based on a first sensing duration, including performing a first program verification on a first memory cell based on the first sensing duration; performing a second verification based on a second sensing duration includes performing a second program verification on a second memory cell based on the second sensing duration. Specifically, at the time of verification, the memory already acquires the target states of the first memory cell and the second memory cell, so that at the time of verification, the first memory cell and the second memory cell can be directly verified by respectively adopting the verification voltages corresponding to the target states; and if the verification voltages applied to the multiple selected memory cells in the verification phase in the current programming cycle do not contain the verification voltages corresponding to the target states of the first memory cell and the second memory cell, not verifying the first memory cell and the second memory cell. If the verify voltage applied to the selected memory cell in the verify phase of the current program cycle includes a verify voltage corresponding to the target state of the first memory cell but does not include a verify voltage corresponding to the target state of the second memory cell, the first memory cell is verified but the second memory cell is not verified. If the verify voltage applied to the selected memory cell in the verify phase of the current program cycle includes the verify voltage corresponding to the target state of the second memory cell but does not include the verify voltage corresponding to the target state of the first memory cell, the second memory cell is verified but the first memory cell is not verified.
In other embodiments, the at least two verifications further include a third program-verify, the third program-verify being performed after the first program-verify and the second program-verify;
performing program verification on the first programmed memory cell further includes:
applying a third verification voltage to the word line of the first programmed memory cell, the third program verification being performed based on the third sensing duration; wherein the third sensing duration is different from the first sensing duration.
In one embodiment, the third sensing duration is the same as the second sensing duration. That is, there may be one to many program verifications in one program loop for different memory cells. The first time programming verification in one programming can adopt a first sensing time length, and the non-first time programming verification can adopt the same sensing time length.
It should be noted that the third sensing time period and the second sensing time period may be different. Specifically, the third sensing duration and the second sensing duration are both less than the first sensing duration.
Accordingly, in one embodiment, the program verify includes only one verify: a fourth program verify; performing program verification on the first programmed memory cell includes:
a fourth program verify is performed based on the first sensing duration.
In one embodiment, a one-time programming process includes a plurality of program-verify cycles, each program-verify cycle including at least one verify operation; the first verification step in all program verify cycles uses the same sensing duration, which may be, for example, the first sensing duration. The sensing time duration of the second verifying operation in all program verifying cycles including at least 2 verifying operations is the same, and may be, for example, the second sensing time duration. The sensing duration of the first verifying operation and the sensing duration of the second verifying operation in all program verifying cycles including at least 2 verifying operations are different.
It should be noted that the memory referred to in the embodiments of the present application refers to a memory device that can perform operations such as programming, reading, and erasing data. For example: NAND Flash Memory (NAND Flash Memory), NOR Flash Memory (NOR Flash Memory), Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), or Resistive Random Access Memory (RRAM), and the like. The memory device may include a memory cell array and control logic, wherein operations such as read/write and verification of the memory cell array may be controlled by a plurality of Word Lines (WL) and a plurality of Bit Lines (BL), and each memory cell is connected to a corresponding Word Line and Bit Line. The bit line signal may be applied to the source of the memory cell and the word line signal may be applied to the gate of the memory cell. The memory cells herein may be non-volatile memory cells.
Each memory Cell may be a double-layer memory Cell (MLC) storing 2-bit data, a Triple-layer memory Cell (TLC) storing 3-bit data, or a Quad-layer memory Cell (QLC) storing 4-bit data. However, the embodiments of the present application are not limited thereto, and some memory cells may be MLCs and some other memory cells may be TLCs, for example. Note that the MLC, TLC, and QLC are induced on the basis of a Single Level Cell (SLC). Specifically, the SLC may include an erase state "1" and a program state "0", and the MLC may include an erase state "11", a first state "10", a second state "00", and a third state "01".
In the embodiment of the present application, the programming method adopted for the selected memory cell in the memory may be Incremental-step-pulse programming (ISPP), and the programming of the memory cell is completed by pulse writing and applying the verification threshold voltage. For example, when data needs to be programmed into a memory cell, the data can be programmed by a set initial programming pulse, and after the pulse is ended, the programmed memory cell is verified by a verification voltage to judge whether the memory cell has entered a target programming state. If the memory cell does not reach the current target programming state, i.e. the state before the target programming state, the adjustment value Δ V of the incremental step pulse programming is added to the currently applied initial pulse voltage as a new pulse voltage, and a round of new programming and verification is performed on the memory cell according to the new pulse voltage and the pulse time until the memory cell is programmed to the correct state, i.e. data is correctly written into the corresponding memory cell.
In the present embodiment, each memory cell needs to be programmed to a respective desired target state, which needs to be achieved through several programming phases. Each programming phase is used to bring the selected memory cells to one of a plurality of programmed states, respectively, until all of the selected memory cells reach their respective desired target states. In the first programming phase, all memory cells are in an erased state before programming is started, and then a program operation is performed on selected memory cells by applying a first program pulse. It should be noted that the program phase in the embodiment of the present application may include a plurality of program-verify cycles, for example, two program-verify cycles or three program-verify cycles, so that the memory cell is programmed to the next state. Wherein one program verify cycle may include one program operation and at least one verify operation.
After one programming operation, a verify operation is required. Here, two verifications may be performed, where the first verification is to determine whether the selected memory cells reach the program state corresponding to the verification voltage of the first verification, and if the program state corresponding to the verification voltage is the final target state of some memory cells, the second verification is not performed on these memory cells if the verification is passed, and the program of these memory cells is inhibited in the subsequent programming process. If the verify passes, but the programmed state to which the verify voltage corresponds is not the target state of the selected memory cell, then the second programming is continued. If not, a second programming may be performed on the memory cells that do not pass the verification. In the verification, a second verification may be performed immediately after the first verification, where the verification voltage of the second verification is different from the verification voltage of the first verification, and specifically, the verification voltage of the second verification is a next state corresponding to the verification voltage of the first verification. If the verify voltage of the second verify corresponds to the verify voltage of the target state of the memory cell, the memory cells are passed the second verify, indicating that the target state has been entered, and therefore the memory cells can be always inhibited from programming in the subsequent programming stages.
The second programming is the next programming after the first programming, and may be the programming in the next programming phase, or the programming in which the program pulse is applied next in the same programming phase as the first programming.
Thus, after the memory cells to be programmed all pass the first state, the verification operation corresponding to the first state can be ended, and after the next programming stage, the verification operation of the first state is not performed any more, but the memory cells which need to be programmed to the second state or higher are programmed. For example, there are 64 memory cells to be programmed, 32 of which are to be programmed to the third state (first set), 16 are to be programmed to the second state (second set), and another 16 are to be programmed to the first state (third set). Thus, in the first programming phase, all 64 memory cells are programmed, with at least one verify and program voltage applied, until all memory cells to be programmed enter the first state. And then entering a second programming stage, and performing programming and verifying processes on all the memory cells in the first group and the second group until the memory cells all enter the second state, and synchronously inhibiting programming on the memory cells in the third group. Then, a third programming phase is entered, and the programming and verifying processes are continued for the first group until they are all tri-stated, and the programming is synchronously inhibited for the memory cells of the second and third groups.
As shown in FIG. 2, in the first programming phase, at least one verify is performed after each application of a programming pulse, such as: when the program pulse is small, none of the selected memory cells have entered the second state, and verify Vv1 may be performed only for the first state; when the program pulse is large, some of the memory cells may enter the second state, and verify Vv1 for the first state and verify Vv2 for the second state need to be performed. If the first state does not verify, the programming pulse is still repeatedly applied in the programming phase, and the second state is verified to find the memory cells (e.g., fast cells) that have reached the first state and entered the higher state. If the first state has passed verification, then the second programming phase is entered, with the program pulses continuing to be applied, and the second and third states Vv2 and Vv3 being verified, so looping, in which it is then necessary to determine whether a new loop can be entered in accordance with the verify of the second state Vv 2.
Illustratively, taking a two-level memory cell capable of storing 2-bit data as an example, there are four corresponding states, namely an erase state "11", a first state "10", a second state "01", and a third state "00". Since the threshold voltages corresponding to the four states are sequentially increased, the program pulses to be applied to program the states are sequentially increased. It should be noted that, the numerical value corresponding to the first state to the third state is only an example, and may be other numerical values, for example, the first state is "01", the second state is "10", and the numerical value may be specifically set according to requirements. Prior to programming, all memory cells are set to an erased state, that is, the erased state of the memory cells corresponds to a threshold voltage less than the threshold voltage corresponding to the first state "10". Next, a programming operation is performed on selected memory cells in the memory, electrons in the conductive channel may be injected into the charge storage layer or the floating gate of the memory cells, so that the memory cells are programmed to corresponding target program states. If the target programming state of the memory cell is the first state, the threshold voltage of the memory cell is larger than the threshold voltage corresponding to the first state "10" through programming, so that the data in the memory cell is changed from "11" to "10", namely, the programming of the selected memory cell in the programming phase is completed.
It should be noted that the programming pulses applied in the embodiments of the present application may be on the word lines corresponding to one or more pages of memory cells. Wherein, part of the memory cells need only be programmed to the first state "10" (i.e. the target programming state of the memory cells is the first state), and part of the memory cells need to be programmed to the third state "00" (i.e. the target programming state of the memory cells is the third state). Here, it is necessary to program all the memory cells to be programmed to the first state "10" first, inhibit programming of the memory cell (the target state of the memory cell is the first state) that has been programmed to the first state "10" in the next programming cycle, and allow other memory cells to continue to be programmed to the second state "01" and finally to the third state "00".
After programming the memory cells, verification is performed, which typically includes the stages of precharging, sensing and sensing. In the precharge stage, a voltage is applied to the bit line by a voltage generator or a sense amplifier, so as to generate a voltage difference between the bit line and the substrate, i.e., between the source and the drain, and then the threshold voltage of the memory cell can be detected according to the voltage change, thereby determining whether the verification passes the corresponding programming state. The voltage precharged onto the bit line may be changed corresponding to the target programmed state of the selected memory cell. The sensing stage is a stage for sensing the change of the bit line voltage and determining whether the verification passes, corresponding to the process of bit line discharging. The read phase is to read the verified state in a latch through sense circuitry connected to the bit line for subsequent interaction with the memory controller. For example, when verifying the memory cell in the first state, a first verification voltage is applied to the word line corresponding to the memory cell. Here, when the threshold voltage corresponding to the programmed memory cell is greater than the first verifying voltage, the memory cell has been programmed to the first state (or has reached the first state); conversely, when the threshold voltage corresponding to the programmed memory cell is less than the first verifying voltage, the memory cell is not programmed to the first state, and the next round of programming and verifying is required. It should be noted that the first state here may be any one of the first to third states described above, or other target programming states.
It should be noted that, in the process of programming and verifying, the duration of the sensing phase may affect the result of the verification. The sensing duration (e.g., the first sensing duration, the second sensing duration) mentioned in the embodiments of the present application all refer to the duration of the sensing phase in the verify operation in one program verify cycle. Illustratively, the first state Pn(where n is a positive integer) is the next state of the erased state E, as shown in FIG. 3, when the sensing duration is shorter, fewer memory cells reach the first state PnResult in a first state PnMargin with the erased state E is small, resulting in odd-side boundary Loss (Margin Loss); for example, if the threshold voltage distributions of the memory cells after being programmed are more distributed, the memory cells in the first state P will be in the first statenThe difference between the minimum threshold voltage and the threshold voltage corresponding to the erased state is small, and the memory cell is easy to have read errors during reading. As shown in FIG. 4, when the sensing duration is longer, more memory cells will reach the first state PnAlbeit in the first state PnThe margin spacing from the erased state E may increase, but a portion of the memory cells that are not programmed may be affected, resulting in a loss of margin for the erased state E. Illustratively, for the memory cells in the erase state E, no programming operation is needed, but since the memory cells to be programmed are subjected to multiple programming pulses, the threshold voltage distribution of some of the memory cells in the erase state E is affected by the multiple programming voltages and drifts. Here, Vr1 and Vr2 shown in FIGS. 3 and 4, respectively, refer to the first shapeState PnAnd a second state Pn+1Vv1 and Vv2 refer to the first state P, respectivelynAnd a second state Pn+1The verification voltage of (1).
Therefore, in the embodiment of the present application, as shown in FIG. 5, the first state P of the memory cell is determined based on the shorter sensing timenThe boundary loss can be effectively reduced by verifying; second state P of memory cell based on longer sensing durationn+1Verification is performed to increase the margin interval between adjacent states. Here the second state Pn+1Is in a first state PnThe next adjacent programmed state refers to a programmed state in which more electrons are injected into the charge storage layer or the floating gate of the memory cell after the verification passes. For example, the second state "10" (second state P) of the MLC described aboven+1) Is the first state "01" (first state P)n) A later adjacent programmed state; third state "11" (second state P)n+1) Is the second state "10" (the first state P)n) The next adjacent programmed state. Finally, according to whether the above-mentioned storage unit reaches first state P or notnAnd/or whether the second state P is reachedn+1For the next round of programming. Similarly, Vr1 and Vr2 shown in FIG. 5 refer to the first state P respectivelynAnd a second state Pn+1Vv1 and Vv2 refer to the first state P, respectivelynAnd a second state Pn+1The verification voltage of (1).
In summary, according to the programming method of the memory provided in the embodiment of the present application, on one hand, after a programming operation is performed in a programming verification cycle, two verification pulses are respectively applied to perform verification, verification voltages corresponding to the two verification pulses may be verification voltages of a first state and a second state (i.e., verification voltages corresponding to two adjacent states), and the two verifications may have different sensing durations, so that a better verification effect on each state is achieved. In another embodiment, multiple verifications may also be performed, each with a different verification voltage. When the verification is carried out, whether the current verification is the first verification in the current cycle or not can be determined, if the current verification is the first verification, the first sensing time length is selected, and if the current verification is not the first verification, the second sensing time length can be selected. In addition, if verification is carried out for multiple times, different induction durations can be adopted, the embodiment of the application is not limited, and the setting can be flexibly carried out in practical application.
After the programming pulse of the first programming is verified for multiple times, the subsequent second programming is carried out according to the verification result. Therefore, on one hand, the accuracy and comprehensiveness of verification can be improved; on the other hand, the verification is carried out for multiple times after each programming based on different induction durations, so that the influence of the verification process on the storage units in different states can be reduced, the corresponding subsequent processing on different storage units is facilitated, and the programming quality is further improved.
It should be noted that, in the embodiment of the present application, the verification passes, and the number of memory cells entering the corresponding state of the verification in the memory satisfies the predetermined condition. As shown in fig. 2, the overall programming of the memory in the embodiment of the present application may include a plurality of program phases, and each program phase may include a plurality of program-verify cycles, so that the memory cell is programmed to the next state. Wherein one program verify cycle may include one program operation and at least one verify operation. After each program-verify cycle is over, the adjustment value Δ V programmed by the incremental step pulse may be added to the next program pulse.
In some embodiments, the method further comprises:
determining a number of failed bits of the first state during the second programming.
Generally, after the selected memory cell is verified, a round of Fail Bit Count (FBC) is required to Count the number of memory cells that Fail to be verified in the corresponding verification programming state in the programming operation, so as to adjust (reprogram) the selected memory cell in time, otherwise, the related data will be lost, which adversely affects the entire memory. But taking the wrong bit statistics up time, increasing the time for programming.
In the embodiment of the present application, the number of failed bits of the first verification may be counted synchronously when the next programming operation is performed. The second programming is a next programming operation of the first programming. Because the number of the failed bits is counted after the first verification is passed, the number of the failed bits of the first programming is not influenced, and the programming operation can be simultaneously carried out, so that the time of the whole programming is greatly reduced, and the programming efficiency is improved.
The embodiment of the application adopts the variable induction duration to verify different states of different storage units, so that the time of integral programming can be reduced, and the programming accuracy is improved.
In some embodiments, verifying the memory cell to be verified includes:
precharging a bit line to which the memory cell is connected to a first bit voltage;
applying a verify voltage to a word line corresponding to the memory cell;
detecting the induction voltage of an induction node on the bit line based on the induction time corresponding to the verification; and determining whether the verification is passed or not according to the change condition of the induction voltage.
The verification process is mainly determined by sensing a change in a voltage of a sense node corresponding to a bit line to which the selected memory cell is connected, wherein the voltage of the sense node is changed according to a current flowing through the selected memory cell.
It should be noted that, in the sensing phase, the sensing voltage at the sensing node SO corresponding to the bit line changes accordingly, where the SO node is a node located in a Page Buffer (Page Buffer). Illustratively, if the induced voltage corresponding to the memory cell drops below the set voltage during the sensing time, the memory cell verification is unsuccessful; if the induction voltage corresponding to the memory cell does not drop below the set voltage within the induction time, the verification of the memory cell is successful. It can also be understood that, in the sensing time, the sensing voltage corresponding to the memory cell that has not been verified linearly decreases faster than the sensing voltage corresponding to the memory cell that has been verified.
The embodiments of the present application also provide the following examples:
if a short sensing time is adopted, the boundary loss of the memory cell at the odd edge can be caused; if a longer sensing duration is used, the high state (second state) is hard to pass and results in longer program time and loss of margin for the low state (erased state).
When the memory carries out PnUpon verification of the state, Pn+1The verification of the state will be done in the next sequence, which sub-sequence may be named Pn+1-a sub state. Thus, for PnSum of states Pn+1The verification of the sub-state, different sensing durations can be flexibly applied. Illustratively, as shown in fig. 6, after the verification starts, the selected memory cell is first verified using a first sensing duration, i.e., a shorter sensing duration. Then, it is determined whether verification is required for a next state, where the next state is a current verification state PnThe latter adjacent state. If the next state needs to be verified, verifying the next state of the selected storage unit by using a second sensing time length, namely a longer sensing time length; if the next state part needs to be verified, the current verification is finished. Note that, for the current verification state PnAnd the next state is verified in the same program-verify cycle, and if the verification is finished, the next program-verify cycle is continued.
In other embodiments, as shown in FIG. 7, after verification begins, it is first determined whether to verify PnVerifying the state, if so, verifying the selected storage unit by using a first induction time length, namely a shorter induction time length; if not, the second sensing time length, namely the longer sensing time length is used for P of the selected storage unitn+1-sub status verification. At P to the selected memory cellnState and Pn+1After the sub state verification is finished, the verification result is sensed, and finally, the verification corresponding to the current round of programming is finished. Here, at PnThe use of a shorter sensing duration (first sensing duration) in the verification of the state can reduce the number of programming pulses that need to be performed, thereby improving the margin of the low state; at Pn+1The verification of the sub-state can be achieved at the larger odd edge with a longer sensing duration (second sensing duration)The margin of the boundary of (1).
Further, may be at PnHiding P in the next programming pulse after state verification passesnNumber of failed bits of state. Thus, P can be compensatednAnd the boundary loss at the odd edge caused by the induction time length during state verification.
Thus, in the examples of this application, PnState and Pn+1Flexible sensing duration is applied in the verification of the sub-state, and boundary loss at odd edges and margin loss of a low state can be compensated; and the statistics of the number of failed bits are hidden in PnIn the next programming pulse after the state verification passes, the programming time can be reduced, and the programming efficiency is improved.
As shown in fig. 8, an embodiment of the present application provides a memory 10, where the memory 10 includes:
a memory cell array 200 including a plurality of memory cells 210;
a peripheral circuit 300 configured to:
applying a first program pulse to a word line of a selected memory cell to perform a first program on the selected memory cell;
performing program verification on the memory cell subjected to the first programming; wherein,
when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length;
performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
In the embodiment of the present application, operations such as read/write and verification of the memory cell array may be controlled by a plurality of word lines and a plurality of bit lines, and each memory cell is connected to a corresponding word line and bit line. The bit line signal may be applied to the source of the memory cell through peripheral circuitry, and the word line signal may be applied to the gate of the memory cell through peripheral circuitry. The memory cells herein may be non-volatile memory cells.
In some embodiments, the plurality of memory cells includes a first memory cell and a second memory cell;
performing a first verification based on a first sensing duration, including performing a first program verification on a first memory cell based on the first sensing duration;
performing a second verification based on a second sensing duration includes performing a second program verification on a second memory cell based on the second sensing duration.
Due to inherent characteristics and process offsets, memory cells in a memory cell array can be generally divided into fast cells and slow cells. In the embodiment of the present application, the slow cell is a key factor that affects whether programming and verification pass, and therefore, after the first programming is performed, the peripheral circuit needs to perform the second programming on the memory cells that have entered the second state according to the verification results of the at least two states, so that the accuracy of the programming can be improved.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method of operating a memory, the method comprising:
applying a first program pulse to a word line of a selected memory cell to perform a first program on the selected memory cell;
performing program verification on the memory cell subjected to the first programming; wherein,
when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length;
performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
2. The method of claim 1, wherein the first sensing duration is less than the second sensing duration.
3. The method of claim 1, wherein the program verify comprises at least two verifies: a first program verify and a second program verify, wherein the first program verify is a first verify in a current program loop;
performing program verification on the first programmed memory cell includes:
applying a first verification voltage to a word line of the memory cell subjected to the first programming, the first program verification being performed based on the first sensing duration;
applying a second verification voltage to the word line of the memory cell subjected to the first programming, the second program verifying being performed based on the second sensing duration.
4. The method of claim 3, wherein the second verify voltage is greater than the first verify voltage.
5. The method of claim 1, wherein the first programmed memory cells comprise first memory cells and second memory cells, wherein the first memory cells and the second memory cells are memory cells having different programming target states;
performing a first verification based on a first sensing duration, including performing a first program verification on a first memory cell based on the first sensing duration;
performing a second verification based on a second sensing duration includes performing a second program verification on a second memory cell based on the second sensing duration.
6. The method of claim 3, wherein the at least two verifications further comprise a third program-verify, the third program-verify being performed after the first program-verify and the second program-verify;
performing program verification on the first programmed memory cell further includes:
applying a third verification voltage to the word line of the memory cell subjected to the first programming, the third program verification being performed based on a third sensing period; wherein the third sensing duration is different from the first sensing duration.
7. The method of claim 6, wherein the third sensing period is the same as the second sensing period.
8. The method of claim 1, wherein the program verify comprises only one verify: a fourth program verify; performing program verification on the first programmed memory cell includes:
a fourth program verify is performed based on the first sensing duration.
9. A memory, comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to:
applying a first program pulse to a word line of a selected memory cell to perform a first program on the selected memory cell;
performing program verification on the memory cell subjected to the first programming; wherein,
when the programming verification is the first verification in the current programming cycle, performing first verification based on a first induction time length;
performing a second verification based on a second sensing duration when the program verification is not the first verification in the current programming cycle; the second sensing duration is different from the first sensing duration.
10. The memory of claim 9, wherein the plurality of memory cells includes a first memory cell and a second memory cell;
performing a first verification based on a first sensing duration, including performing a first program verification on the first memory cell based on the first sensing duration;
performing a second verification based on a second sensing duration includes performing a second program verification on the second memory cell based on the second sensing duration.
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