CN113903393A

CN113903393A - Method for improving NOR FLASH reliability

Info

Publication number: CN113903393A
Application number: CN202110953010.7A
Authority: CN
Inventors: 李建波; 王延斌
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2022-01-07

Abstract

The invention provides a method for improving the reliability of NOR FLASH, which is applied to the field of chip secure storage. The method comprises 5 stages: stage 1, updating an erasing frequency statistical page; stage 2, updating an ECC error statistic page; stage 3, updating the address mapping information page; step 4, initializing an address mapping table; and stage 5, accessing the physical area by the logical address. Aiming at the problem of NOR FLASH reliability, a physical state statistical area is introduced to comprise an erasing frequency statistical page and an ECC error statistical page, the erasing frequency influences the reliability, the ECC error indicates that failure occurs, and the NOR FLASH reliability level can be effectively evaluated through the information. And simultaneously adding a redundant physical area, and replacing the failed original physical area by an address mapping table. The method provided by the invention can evaluate the reliability level of the NOR FLASH and improve the reliability of the NOR FLASH at the same time.

Description

Method for improving NOR FLASH reliability

Technical Field

The invention relates to the technical field of chip secure storage, in particular to a method for improving NOR FLASH reliability.

Background

With the continuous development of the integrated circuit industry in China, the application field of NOR FLASH is more and more extensive, and higher challenges are provided for the reliability of NORFLASH. In the use process of the traditional NOR FLASH chip, the reliability problem is caused by some reasons (such as chip aging, environmental temperature and humidity change, erasing times exceeding the upper limit and the like), so that the chip works abnormally.

When failure analysis is carried out on a NOR FLASH chip with reliability problems, only failed units can be identified, but the reasons for the results cannot be analyzed, and the chip cannot be recovered to work normally. Therefore, there is a need for a suitable method to preserve the state affecting the reliability of NOR FLASH for evaluating the reliability level, while a method to replace failed cells to restore the chip to normal operation is needed.

Disclosure of Invention

The invention provides a method for improving the reliability of NOR FLASH, which is used for evaluating the reliability level of the NOR FLASH and improving the reliability of the NOR FLASH at the same time.

The invention provides a method for improving NOR FLASH reliability, which is characterized in that the method specifically comprises a physical area, a physical state statistical area, an address mapping area and an address mapping table, and the method comprises the following 5 stages:

stage 1, updating an erasing frequency statistical page;

stage 2, updating an ECC error statistic page;

stage 3, updating the address mapping information page;

step 4, initializing an address mapping table;

stage 5, the logical address accesses the physical area;

in the stage 1, updating the erasing times counting Page is that after the current Page in the physical area is erased, the hardware reads the information of the erasing times counting Page corresponding to the current Page, and then updates the information of the erasing times counting Page corresponding to the current Page, wherein the specific updating is writing operation, the specific reading information is the erased times of the current Page, and the specific updating information is the erased times of the current Page plus one.

And the step 2 of updating the ECC error counting Page is that after the current Page of the physical area has an ECC error, the information of the ECC error counting Page corresponding to the current Page is read, and then the information of the ECC error counting Page corresponding to the current Page is updated, wherein the specific updating is writing operation, the specific reading information is the number of times of the current Page having the ECC error, and the specific updating information is the number of times of the current Page having the ECC error plus one.

And 3, updating the address mapping information page in a stage of reading the information of the physical state statistical area, judging whether the erasing times is larger than the maximum value, if so, updating the address mapping information page, otherwise, judging whether ECC errors occur, if so, updating the address mapping information page, otherwise, carrying out no operation, specifically updating the address mapping information page to be write operation, wherein the specific maximum value is the intrinsic life of NOR FLASH, the content of the specific address mapping information page is 1 or 0, and the specific address mapping information page is defaulted to be 1, and the specific no operation means that the write operation is not carried out.

And the step 4 of initializing the address mapping table is to read the address mapping information page and update the address mapping table after the chip is powered on, and specifically, the address mapping table is initialized to latch the content of the read address mapping information page into a register, and the address mapping table selects a redundant physical area or an original physical area according to the value of the register.

And in the stage 5, when the logical address accesses the physical area, the logical address is firstly latched and then converted into the physical address, whether the redundant physical area is started or not is judged according to the address mapping table, if so, the redundant physical area is started, otherwise, the original physical area is kept unchanged, the specific conversion into the physical address belongs to the memory space management, the physical address is already fixed during chip design, and after the specific initialization address mapping table is completed, the physical address corresponds to the redundant physical area or the original physical area and is a fixed value.

Drawings

FIG. 1 is a system diagram of a method for improving NOR FLASH reliability;

FIG. 2 is a flowchart of an update erase count page;

FIG. 3 is a flowchart of updating an ECC error statistics page;

FIG. 4 is a flowchart of updating an address mapping information page;

FIG. 5 is a flow chart of initializing an address mapping table;

FIG. 6 is a flow chart of logical address access to a physical area;

Detailed Description

The method for improving the reliability of the NOR FLASH comprises 3 parts, as shown in figure 1, the part 1 is that the current Page erasing times and ECC error state information of a NOR FLASH physical area (108) are acquired and stored to an erasing times counting Page (1011) and an ECC error counting Page (1012) corresponding to a physical state counting area (101), and the information is used for evaluating the reliability level of the current Page; the 2 nd part is that a user program (103) obtains the current Page erasing times and ECC error state information through a physical state statistical module (102), and updates an address mapping information Page (1051) of an address mapping area (105) through an address mapping management module (104), and the part is a key decision link and decides whether to replace an original physical area or not according to the reliability level of the current Page; part 3 is the replacement of the redundant physical area with the original physical area by initializing the address mapping table (107) by reading the contents of the address mapping information page (1051). The implementation will be described in detail from 5 stages below.

The phase 1 update erase count statistics page is shown in fig. 2, specifically:

in step 201, the current Page erase of the physical area is completed.

Step 202, reading the statistical Page information of the corresponding erasing times of the current Page.

And step 203, updating the statistical Page information of the corresponding erasing times of the current Page.

The step 201 that the current Page erase of the physical area is completed means that the user executes a Page erase instruction, and the chip completes the Page erase operation.

Reading the statistics Page information of the erasing times corresponding to the current Page in step 202 means that the chip automatically reads the statistics Page information of the erasing times corresponding to the current Page, the specific erasing times statistics Page is a fixed Page of a physical area corresponding to a fixed address in the Page, and the specific reading information is the erased times of the current Page.

The step 203 of updating the information of the statistical Page of the erasing times corresponding to the current Page means that a write operation is performed on the statistical Page of the erasing times corresponding to the current Page, and the specific content of the write operation is that the erased times of the current Page read in the step 202 are increased by one.

Phase 2 update ECC error statistics page as shown in fig. 3, specifically:

in step 301, the current Page of the physical area is ECC-error.

Step 302, reading the ECC error statistical Page information corresponding to the current Page.

Step 303, updating the ECC error statistical Page information corresponding to the current Page.

The current Page ECC error of the physical area in step 301 refers to an ECC error occurring when a user reads the content of the current Page.

Step 302, reading the ECC error statistics Page information corresponding to the current Page means that the chip automatically reads the ECC error statistics Page information corresponding to the current Page, and the specific read information is the number of times of ECC errors occurring in the current Page, where the specific fixed address in the ECC error statistics Page corresponds to the fixed Page in the physical area.

Updating the information of the ECC error statistic Page corresponding to the current Page in step 303 means performing a write operation on the ECC error statistic Page corresponding to the current Page, where the specific content of the write operation is to add one to the number of ECC errors occurring when the current Page is read in step 302.

Stage 3 updating address mapping information page as shown in fig. 4, specifically:

step 401, reading the physical status statistics area information, where the information includes the number of times of erasure and the number of times of ECC errors.

Step 402, judging whether the erasing times is larger than the maximum value, if so, executing step 403, otherwise, executing step 404, wherein the specific maximum value is the intrinsic life of the NOR FLASH.

Step 403, updating the address mapping information page, where the specific update is a write operation, and the content of the write operation is 0. The specific content of the address mapping information page is 1 or 0, and defaults to 1.

Step 404, determining whether the number of ECC errors is greater than 1, if so, executing step 403, otherwise, executing step 405.

Step 405, no operation, i.e. no write operation, ends this phase.

Stage 4 initializing address mapping table as shown in fig. 5, specifically:

step 501, the chip power-on completion means that the chip completes simulation trimming, chip configuration and safety monitoring, and can execute a user program.

In step 502, reading the address mapping information page refers to latching the content of the read address mapping information page into a register.

In step 503, updating the address mapping table means selecting a redundant physical area or an original physical area according to the register value latched in step 502, where the latched register value corresponds to the original physical area if it is 1, and corresponds to the redundant physical area if it is 0.

Stage 5 logical address access physical area as shown in fig. 6, specifically:

in step 601, latching the logical address refers to latching the address accessed by the user into the register.

The translation to a physical address, step 602, refers to translating a logical address to a physical address according to a memory space management scheme.

Step 603, judging whether to start a redundant physical area, if so, executing step 604, otherwise, executing step 605, wherein the specific judgment is based on the content of the address mapping table of the stage 4, if so, selecting the original physical area, if so, selecting the redundant physical area, and after the specific stage 4 is completed, the content of the address mapping table is a fixed value, namely the redundant physical area or the original physical area corresponding to the current Page is a fixed value.

In step 604, the redundant physical area refers to that the corresponding content of the current Page of the address mapping table is 0, and the redundant physical area is selected.

Step 605, selecting the original physical area, where the content of the address mapping table corresponding to the current Page is 1.

Claims

1. A method for improving NOR FLASH reliability is characterized in that the method specifically comprises a physical area, a physical state statistical area, an address mapping area and an address mapping table, and the method comprises the following 5 steps:

step 1, updating an erasure frequency statistical page;

step 2, updating an ECC error statistical page;

step 3, updating an address mapping information page;

step 4, initializing an address mapping table;

and step 5, the logical address accesses the physical area.

2. The method according to claim 1, wherein the updating of the statistics Page for erase times is performed by reading statistics Page information for erase times corresponding to the current Page after the current Page in the physical area is erased, and updating statistics Page information for erase times corresponding to the current Page.

3. The method of claim 1, wherein the updating the ECC error statistics Page comprises reading information of the ECC error statistics Page corresponding to the current Page after the current Page of the physical area has an ECC error, and updating the information of the ECC error statistics Page corresponding to the current Page.

4. The method of claim 1, wherein the updating the address mapping information page is reading physical state statistics area information, and then determining whether the number of times of erasing is greater than a maximum value, if so, updating the address mapping information page, otherwise, determining whether an ECC error occurs, if so, updating the address mapping information page, otherwise, no operation is performed.

5. The method of claim 1, wherein initializing the address mapping table is reading the address mapping information page and updating the address mapping table after the chip is powered on.

6. The method as claimed in claim 1, wherein the logical address access physical area latches the logical address first, converts the logical address into the physical address, determines whether to activate the redundant physical area according to the address mapping table, activates the redundant physical area if the redundant physical area is activated, and otherwise keeps the original physical area unchanged.