CN113903301B

CN113903301B - Shift register, scanning driving circuit, driving method, display panel and device

Info

Publication number: CN113903301B
Application number: CN202111204248.6A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2023-04-21
Anticipated expiration: 2041-10-15
Also published as: CN113903301A

Abstract

The embodiment of the disclosure provides a shift register, a scanning driving circuit, a driving method, a display panel and a device, and relates to the technical field of display, so as to improve the phenomenon of dynamic image smear and improve the image display effect. The driving method of the shift register comprises a plurality of line scanning time periods, wherein the line scanning time periods comprise a scanning stage and a black inserting stage; the plurality of line scanning time periods comprise at least M line scanning time period groups, each line scanning time period group comprises N line scanning time periods, and the time sequences of scanning phases of the N line scanning time periods are the same; the black insertion stage of the line scanning period starts at a time after the scanning stage of the last line scanning period; the duration of the black insertion stage is less than or equal to the reference time difference of the starting time of two scanning stages under the condition that scanning signals are output by two adjacent line scanning periods line by line, and the black insertion stage comprises M times (N-1) time sequences at most. The driving method of the shift register of the embodiment of the disclosure is used for the shift register.

Description

Shift register, scanning driving circuit, driving method, display panel and device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a shift register, a scan driving circuit, a driving method, a display panel and a device.

Background

The scan driving circuit is an important component in the display device. The scan driving circuit may include a multi-stage cascade of shift registers, each of which may be electrically connected to a row of wiring in the display device. The scan driving circuit may input scan signals into a plurality of wirings (e.g., gate lines or enable signal lines, etc.) in the display device line by line to enable the display device to perform picture display.

However, during the display of the display device, an image smear phenomenon occurs during the process of switching the dynamic image, that is, when the display device is switched from one frame to another frame, the viewer may feel the image smear of the previous frame (also referred to as dynamic image smear), thereby affecting the image display effect.

Disclosure of Invention

The disclosure provides a shift register, a scanning driving circuit, a driving method, a display panel and a device, so as to improve the phenomenon of dynamic image smear and improve the image display effect.

In one aspect, a method of driving a shift register is provided. The shift register includes a plurality of sub-shift registers, each of which corresponds to a line scanning period in one frame period, the line scanning period including a scanning phase and a black insertion phase. The plurality of line scanning time periods corresponding to the plurality of sub-shift registers comprise at least M line scanning time period groups, each line scanning time period group comprises N line scanning time periods, and the time sequences of the scanning phases of the N line scanning time periods are the same; m is greater than or equal to 1, N is greater than or equal to 2, and M and N are integers. The black insertion stage of the line scanning period starts at a time after the scanning stage of the last line scanning period of the plurality of line scanning periods; the duration of the black inserting stage is smaller than or equal to the reference time difference of the starting time of two scanning stages under the condition that scanning signals are output by two adjacent line scanning periods line by line, and the black inserting stage of the plurality of line scanning periods comprises M× (N-1) time sequences at most.

In some embodiments, the timings of the black insertion phases of the plurality of line scan periods are the same; or the black inserting stage of the plurality of line scanning periods comprises at least two time sequences, and the time sequences of the black inserting stages of at least two line scanning periods are the same; alternatively, the black inserting stage of the plurality of line scanning periods includes at least two timings, and the black inserting stage of the relatively preceding line scanning period is earlier in time than the black inserting stage of the relatively succeeding line scanning period.

In some embodiments, the shift register includes eight sub-shift registers corresponding to eight row scan periods, respectively, in one frame period. Wherein the eight line scanning periods comprise a line scanning period group, each line scanning period group comprises two line scanning periods, and the eight black inserting phases of the eight line scanning periods have the same time sequence; or, the eight line scanning periods include two line scanning period groups, each line scanning period group including two line scanning periods; the eight black inserting stages of the eight line scanning periods comprise two time sequences, the time sequences of the black inserting stages of the first four line scanning periods are identical, and the time sequences of the black inserting stages of the last four line scanning periods are identical; or, the eight line scanning periods include four line scanning period groups, each line scanning period group including two line scanning periods; the eight black inserting stages of the eight line scanning periods include four kinds of timings, and timings of the black inserting stages of each line scanning period group are the same.

In some embodiments of the present disclosure, in a frame period, the timings of scan phases of at least two line scan periods are the same, so that idle time is saved, and black insertion is performed by using the saved idle time. Therefore, in the driving method of the shift register provided by some embodiments of the present disclosure, under the condition that the refresh frequency is certain, the time of the black inserting stage can be increased on the basis of not compressing the time of each scanning stage, that is, the black picture is inserted in the process that the sub-pixel emits light to display the normal image, so that the MPRT (Motion Picture Response Time, dynamic image response time) is increased, the phenomenon of dynamic image smear is improved, and the image display effect is improved.

In another aspect, a shift register is provided. The shift register is used for executing the driving method of the shift register according to any one of the embodiments. The shift register includes a plurality of sub-shift registers, each sub-shift register electrically connected to a row of sub-pixels. The sub shift register includes an input circuit and an output circuit. The input circuit is coupled with the input signal end and the first node; the input circuit is configured to transmit a scan input signal received at the input signal terminal to the first node in response to the scan input signal; and transmitting the black inserted input signal to the first node in response to the black inserted input signal received at the input signal terminal. The output circuit is coupled to the first node, the first clock signal terminal CLKE, and the first output signal terminal; the output circuit is configured to transmit a scan clock signal received at the first clock signal terminal to the first output signal terminal in a case where the scan input signal is transmitted to the first node, so that the first output signal terminal outputs a scan signal; and transmitting the black insertion clock signal received at the first clock signal terminal to the first output signal terminal under the condition that the black insertion input signal is transmitted to the first node, so that the first output signal terminal outputs a black insertion signal.

The shift register comprises M sub-shift register groups, each sub-shift register group comprises N adjacent sub-shift registers, M is more than or equal to 1, N is more than or equal to 2, and M and N are integers; the N sub shift registers are configured to receive scan clock signals having the same timing to output scan signals having the same timing. The time for starting to output the black signal is after the writing of the data signal is completed by one row of sub-pixels connected with the last sub-shift register in the plurality of sub-shift registers; the duration of the black insertion signal is smaller than or equal to the reference time difference of the starting time of two scanning signals under the condition that two adjacent sub-shift registers output the scanning signals row by row; the black insertion signals output by the plurality of sub-shift registers include at most M× (N-1) kinds of timings.

In yet another aspect, a scan driving circuit is provided. The scan driving circuit includes a plurality of shift registers as described in the above embodiments in cascade.

In some embodiments, each shift register includes X sub-shift registers, X.gtoreq.2, and X is an integer. The scan driving circuit further includes a plurality of first clock signal line groups, each of which includes at least X-mx (N-1) first clock signal lines. The first clock signal terminals of each shift register are correspondingly coupled with the first clock signal lines of the first clock signal line group.

In some embodiments, the first clock signal terminals of the N sub-shift registers of each sub-shift register group are coupled to the same first clock signal line, and different sub-shift register groups are coupled to different first clock signal lines. In the shift register, the first clock signal ends of all the other sub-shift registers except the M sub-shift register groups are respectively coupled with different first clock signal lines.

In still another aspect, a driving method of a scan driving circuit is provided. The driving method is applied to the scanning driving circuit described in any one of the above embodiments. Each frame period comprises a plurality of line scanning periods, and each line scanning period comprises a scanning phase and a black inserting phase; each sub shift register of each shift register of the scan driving circuit is for performing one row scan period. In the scanning stage, the sub-shift register receives a scanning input signal and a scanning clock signal and outputs a scanning signal to control a row of sub-pixels electrically connected with the sub-shift register to emit light. In the black inserting stage, the input circuit receives a black inserting input signal and a black inserting clock signal and outputs a black inserting signal so as to control a row of sub-pixels electrically connected with the sub-shift register to stop emitting light.

In some embodiments, the black insertion stage of the row scan period performed by each sub-shift register of the shift register is after the scan stage of the plurality of row scan periods performed by the plurality of sub-shift registers of the shift register and before a row of sub-pixel data signals corresponding to the row scan period performed by one of the other shift registers is written.

In some embodiments, the black insertion stage of the line scan period performed by any one of the sub-shift registers is subsequent to the scan stage of the line scan period performed by the last sub-shift register of the cascaded plurality of shift registers.

In yet another aspect, a method of driving a shift register is provided. The shift register includes a plurality of sub-shift registers, each of which corresponds to a line scanning period in one frame period, the line scanning period including a scanning phase and a black insertion phase. The time for starting the black inserting stage is the same as the time for starting the writing of the data signals of one row of sub-pixels driven by the set row scanning period, and the ratio of the duration of the black inserting stage to the duration of the writing of the data signals of one row of sub-pixels driven by the set row scanning period is less than or equal to 1/2; the set line scanning period is a line scanning period corresponding to one sub-shift register of the other shift registers.

In yet another aspect, a shift register is provided. The shift register is used for executing the driving method of the shift register according to the embodiment. The shift register includes a plurality of sub-shift registers, each sub-shift register electrically connected to a row of sub-pixels. The sub shift register comprises a scanning input circuit, a black insertion input circuit and an output circuit. The scanning input circuit is coupled with the scanning input signal end and the first node; the scan in circuit is configured to transmit a scan in signal to the first node in response to the scan in signal received at the scan in signal terminal. The black insertion input circuit is coupled with the black insertion signal end and the first node; the black insertion input circuit is configured to transmit a black insertion input signal received at the black insertion input signal terminal to the first node in response to the black insertion input signal. The output circuit is coupled to the first node, the first clock signal terminal CLKE, and the first output signal terminal; the output circuit is configured to transmit a scan clock signal received at the first clock signal terminal to the first output signal terminal in a case where the scan input signal is transmitted to the first node, so that the first output signal terminal outputs a scan signal; and transmitting the black insertion clock signal received at the first clock signal terminal to the first output signal terminal under the condition that the black insertion input signal is transmitted to the first node, so that the first output signal terminal outputs a black insertion signal.

The time for starting outputting the black inserting signal is the same as the time for starting writing the data signal of one row of sub-pixels connected with the setting sub-shift register, and the ratio of the duration of the black inserting signal to the duration of writing the data signal of one row of sub-pixels connected with the setting sub-shift register is less than or equal to 1/2; the setting sub-shift register is one sub-shift register in other shift registers.

In yet another aspect, a display panel is provided. The display panel comprises the scanning driving circuit in any embodiment.

In yet another aspect, a display device is provided. The display device comprises the display panel described in the above embodiment.

The shift register, the scan driving circuit, the driving method of the scan driving circuit, the display panel and the display device provided by some embodiments of the present disclosure have the same advantages as those of the driving method of the shift register provided by the above technical solution, and are not described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is a block diagram of a display panel according to some embodiments;

FIG. 3 is a block diagram of another display panel according to some embodiments;

FIG. 4 is a circuit diagram of a sub-pixel according to some embodiments;

FIG. 5 is a timing diagram corresponding to the sub-pixel of FIG. 4 according to one of the related art;

FIG. 6 is a timing diagram corresponding to the sub-pixel of FIG. 4, according to some embodiments;

FIG. 7 is a block diagram of a shift register according to some embodiments;

FIG. 8 is a circuit diagram of a sub-shift register according to some embodiments;

FIG. 9 is a circuit diagram of another seed shift register according to some embodiments;

FIG. 10 is a circuit diagram of yet another sub-shift register according to some embodiments;

FIG. 11 is a block diagram of another shift register according to some embodiments;

FIG. 12 is a circuit diagram of a black insertion input circuit of a sub-shift register according to some embodiments;

FIG. 13 is a circuit diagram of yet another sub-shift register according to some embodiments;

fig. 14 is a block diagram of a scan driving circuit according to some embodiments;

FIG. 15 is a block diagram of another scan drive circuit according to some embodiments;

FIG. 16 is a timing diagram of a partial sub-shift register of a scan driving circuit according to some embodiments;

FIG. 17 is a timing diagram of the clock signal lines of the scan driving circuit shown in FIG. 16;

FIG. 18 is a timing diagram of a partial sub-shift register of another scan driving circuit according to some embodiments;

FIG. 19 is a timing diagram of the clock signal lines of the scan driving circuit shown in FIG. 18;

FIG. 20 is a timing diagram of a portion of a sub-shift register of yet another scan driving circuit according to some embodiments;

FIG. 21 is a timing diagram of a clock signal line of the scan driving circuit shown in FIG. 20;

FIG. 22 is a timing diagram of yet another scan driving circuit according to some embodiments;

fig. 23 is a timing chart of clock signal lines of the scan driving circuit shown in fig. 22;

FIG. 24 is a timing diagram of yet another scan driving circuit according to some embodiments;

fig. 25 is a timing chart of clock signal lines of the scan driving circuit shown in fig. 24.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C," both include the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

As used herein, the term "if" is optionally interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if determined … …" or "if detected [ stated condition or event ]" is optionally interpreted to mean "upon determining … …" or "in response to determining … …" or "upon detecting [ stated condition or event ]" or "in response to detecting [ stated condition or event ]" depending on the context.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (e.g., oxide thin film transistors), or other switching devices with the same characteristics, and the thin film transistors are all described in the embodiments of the present disclosure as examples.

In some embodiments, the control of each transistor employed by the shift register is the gate of the transistor, the first being one of the source and drain of the transistor and the second being the other of the source and drain of the transistor. Since the source and drain of a transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present disclosure may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit provided by the embodiment of the disclosure, the nodes do not represent actually existing components, but represent junction points of related electrical connections in the circuit diagram, that is, the nodes are equivalent nodes of the junction points of the related electrical connections in the circuit diagram.

In embodiments of the present disclosure, the term "pull-up" means that one electrode of one node or one transistor is charged such that the absolute value of the level of the node or the electrode is raised, thereby enabling the operation (e.g., turning on) of the corresponding transistor. The term "pull down" means that one electrode of one node or one transistor is discharged such that the absolute value of the level of the node or the electrode is reduced, thereby enabling the operation (e.g., turning off) of the corresponding transistor.

In the following, in the circuit provided in the embodiment of the present disclosure, the transistors are all exemplified by N-type transistors.

Some embodiments of the present disclosure provide a display device 2000, as shown in fig. 1, the display device 2000 may be any device that displays images whether in motion (e.g., video) or stationary (e.g., still image) and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like.

In some embodiments, as shown in fig. 1. The display device 2000 includes the display panel 1000 described above.

Illustratively, the display device 2000 further includes a frame, a circuit board, a source driving chip, and other electronic components. Wherein the display panel 1000 may be disposed within the frame.

The types of the display panel 1000 include various types, and can be selected according to actual needs.

Illustratively, the display panel 1000 may be: any one of an organic light emitting diode (Organic Light Emitting Diode, abbreviated as OLED) display panel, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, abbreviated as QLED) display panel, a Micro light emitting diode (Micro Light Emitting Diodes, abbreviated as Micro LED) display panel, and the like is not specifically limited in this disclosure.

Some embodiments of the present disclosure are schematically described below taking the above-described display panel 1000 as an OLED display panel as an example.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 has a display area a and a frame area B disposed beside the display area a. Wherein, "side" means one side, two sides, three sides, or a peripheral side of the display area a, that is, the bezel area B may be located at one side, two sides, or three sides of the display area a, or the bezel area B may be disposed around the display area a.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 may include: a scan driving circuit 100 and a substrate 200. The substrate 200 is used to carry the scan driving circuit 100.

Here, the scan driving circuit 100 may be located in the frame region B or the display region a. The present disclosure is not limited in this regard.

The types of the substrate 200 include various types, and the arrangement may be selected according to actual needs.

Illustratively, the substrate 200 may be a rigid substrate. The rigid substrate may be, for example, a glass substrate, a PMMA (Polymethyl methacrylate ) substrate, or the like.

Illustratively, the substrate 200 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene terephthalate ) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like. At this time, the display panel 1000 may be a flexible display panel.

Here, the scan driving circuit 100 may be, for example, a light emission control circuit or a gate driving circuit. The present disclosure is schematically illustrated by taking the scan driving circuit 100 as a gate driving circuit.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 may further include: a plurality of sub-pixels P disposed at one side of the substrate 200 and located in the display area a. The plurality of sub-pixels P may be arranged in a plurality of rows along the first direction X and a plurality of columns along the second direction Y, for example. Each row of the sub-pixels P may include a plurality of sub-pixels P, and each column of the sub-pixels P may include a plurality of sub-pixels P.

Here, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. Illustratively, the angle between the first direction X and the second direction Y may be 85 °, 89 °, 90 °, or the like.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 may further include: a plurality of gate lines GL and a plurality of data lines DL disposed at one side of the substrate 200 and located at the display area a. Wherein the plurality of gate lines GL extend along a first direction X, and the plurality of data lines DL extend along a second direction Y.

For example, the sub-pixels P arranged in one row in the first direction X may be referred to as the same row of sub-pixels P, and the sub-pixels P arranged in one column in the second direction Y may be referred to as the same column of sub-pixels P. The same row of subpixels P may be electrically connected to one gate line GL, and the same column of subpixels P may be electrically connected to one data line DL.

In some embodiments, as shown in fig. 4, each of the plurality of sub-pixels P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. The light emitting device may be an OLED.

For example, one gate line GL may be electrically connected to a plurality of pixel driving circuits in the same row of sub-pixels P, and one data line DL may be electrically connected to a plurality of pixel driving circuits in the same column of sub-pixels P.

The structure of the pixel driving circuit includes various types, and can be selected and set according to actual needs. For example, the structure of the pixel driving circuit may include a structure of "2T1C", "3T1C", "6T1C", "7T1C", "6T2C", or "7T2C", or the like. Where "T" is denoted as a transistor, the number preceding "T" is denoted as the number of transistors, "C" is denoted as a storage capacitor, and the number preceding "C" is denoted as the number of storage capacitors.

Here, during the use of the display panel 1000, the stability of the transistors and the light emitting devices in the pixel driving circuit may be reduced (e.g., the threshold voltage of the driving transistor is shifted), which affects the display effect of the display panel 1000, and thus, the sub-pixels P need to be compensated.

The manner of compensating the sub-pixel P may include various manners, and may be selected according to actual needs. For example, a pixel compensation circuit may be provided in the sub-pixel P to internally compensate the sub-pixel P using the pixel compensation circuit. For another example, the driving transistor or the light emitting device may be sensed through a transistor inside the sub-pixel P, and sensed data is transmitted to an external sensing circuit to calculate a driving voltage value to be compensated and perform feedback by using the external sensing circuit, thereby implementing external compensation of the sub-pixel P.

The present disclosure uses an external compensation method (sensing the driving transistor), and the pixel driving circuit uses a structure of "3T1C" as an example, and the structure and operation of the subpixel P are schematically described.

Illustratively, as shown in fig. 4, the pixel driving circuit may include: a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

For example, as shown in fig. 4, the control electrode of the switching transistor T1 is electrically connected to the first scan signal terminal G1, the first electrode of the switching transistor T1 is electrically connected to the Data signal terminal Data, and the second electrode of the switching transistor T1 is electrically connected to the second node G. Wherein the switching transistor T1 is configured to transmit the Data signal received at the Data signal terminal Data to the second node G in response to the first scan signal received at the first scan signal terminal G1.

Here, the data signal may include, for example, a detection data signal, a display data signal, and a black insertion data signal. Wherein the detection data signal is used in the blanking period, the display data signal is used in the display period, and the black insertion data signal is used in the black insertion writing period. Regarding the black insertion writing phase, the display period, and the blanking period, reference may be made to the following descriptions in some embodiments, and details thereof will not be repeated here.

For example, as shown in fig. 4, the control electrode of the driving transistor T2 is electrically connected to the second node G, the first electrode of the driving transistor T2 is electrically connected to the fourth voltage signal terminal ELVDD, and the second electrode of the driving transistor T2 is electrically connected to the third node S. Wherein the driving transistor T2 is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal ELVDD to the third node S under the control of the voltage of the second node G.

For example, as shown in fig. 4, a first terminal of the storage capacitor Cst is electrically connected to the second node G, and a second terminal of the storage capacitor Cst is electrically connected to the third node S. The switching transistor T1 charges the storage capacitor Cst simultaneously during charging of the second node G.

For example, as shown in fig. 4, the anode of the light emitting device is electrically connected to the third node S, and the cathode of the light emitting device is electrically connected to the fifth voltage signal terminal ELVSS. The light emitting device is configured to emit light under the mutual cooperation of the fourth voltage signal from the third node S and the fifth voltage signal transmitted from the fifth voltage signal terminal ELVSS.

For example, as shown in fig. 4, the control electrode of the sensing transistor T3 is electrically connected to the second scan signal terminal G2, the first electrode of the sensing transistor T3 is electrically connected to the third node S, and the second electrode of the sensing transistor T3 is electrically connected to the sensing signal terminal Sense. Wherein the sense transistor T3 is configured to detect an electrical characteristic of the drive transistor T2 in response to the second scan signal received at the second scan signal terminal G2 to achieve external compensation. The electrical characteristics include, for example, a threshold voltage and/or carrier mobility of the driving transistor T2.

Here, the Sense signal terminal Sense may provide a reset signal for resetting the third node S or acquire a Sense signal for acquiring the threshold voltage of the driving transistor T2.

Based on the structure of the pixel driving circuits, as shown in fig. 2, a plurality of pixel driving circuits in the same row of sub-pixels P may be electrically connected to two gate lines GL (i.e., a first gate line and a second gate line). For example, each first scanning signal terminal G1 may be electrically connected to the first gate line and receive the first scanning signal transmitted by the first gate line; each second scan signal terminal G2 may be electrically connected to the second gate line, and receive the second scan signal transmitted by the second gate line.

It should be noted that one frame period may include, for example, a display period, a black insertion period, and a blanking period that are sequentially performed. In the display period, the sub shift register 10 may drive the corresponding sub pixel P to perform image display; in the black insertion period, the sub shift register 10 may drive the corresponding sub pixel P to display a black picture; in the blanking period, the sub shift register 10 may drive the corresponding sub pixel P for external compensation. Only the display period therein is schematically described below.

In the display period, as shown in fig. 5, the operation process of the sub-pixel P may include, for example, a reset phase P1, a data writing phase P2, and a light emitting phase P3.

In the reset phase P1, the level of the second scan signal provided by the second scan signal terminal G2 is high, and the Sense signal terminal Sense provides a reset signal (the level of the reset signal is low, for example). The sensing transistor T3 is turned on under the control of the second scan signal, receives a reset signal, and transmits the reset signal to the third node S to reset the third node S.

In the Data writing stage P2, the level of the first scan signal provided by the first scan signal terminal G1 is high, and the level of the display Data signal provided by the Data signal terminal Data is high. The switching transistor T1 is turned on under the control of the first scan signal, receives a display data signal, and transmits the display data signal to the second node G while charging the storage capacitor Cst.

In the light emitting stage P3, the level of the first scan signal provided by the first scan signal terminal G1 is low, the level of the second scan signal provided by the second scan signal terminal G2 is low, and the level of the fourth voltage signal provided by the fourth voltage signal terminal ELVDD is high. The switching transistor T1 is turned off under the control of the first scan signal, and the sensing transistor T3 is turned off under the control of the second scan signal. The storage capacitor Cst starts to discharge so that the voltage of the second node G is maintained at a high level. The driving transistor T2 is turned on under the control of the voltage of the second node G, receives a fourth voltage signal, and transmits the fourth voltage signal to the third node S, so that the light emitting device emits light under the interaction of the fourth voltage signal and the fifth voltage signal transmitted by the fifth voltage signal terminal ELVSS.

In some embodiments, the scan driving circuit 100 and the plurality of sub-pixels P are located on the same side of the substrate 200. The scan driving circuit 100 may include a plurality of shift registers 1 in cascade, and one shift register 1 may be electrically connected to a plurality of pixel driving circuits in at least one row of sub-pixels P. Illustratively, one shift register 1 includes a plurality of sub-shift registers 10, each sub-shift register 10 being electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P.

It should be noted that, the first scan signal transmitted by the first scan signal terminal G1 and the second scan signal transmitted by the second scan signal terminal G2 are provided by the scan driving circuit 100. That is, each sub shift register 10 in the scan driving circuit 100 may be electrically connected to the first scan signal terminal G1 through a first gate line through which a first scan signal is transmitted to the first scan signal terminal G1, and electrically connected to the second scan signal terminal G2 through a second gate line through which a second scan signal is transmitted to the second scan signal terminal G2.

Of course, as shown in fig. 3, a plurality of pixel driving circuits in the same row of sub-pixels P may be electrically connected to the same gate line GL. In this case, the first scan signal and the second scan signal are the same. In the scan driving circuit 100, each sub-shift register 10 is electrically connected to the first scan signal terminal G1 and the second scan signal terminal G2 through the corresponding gate line GL, and transmits signals to the first scan signal terminal G1 and the second scan signal terminal G2 through the gate line GL.

In the related art, during the display of the display panel 1000, an image smear phenomenon occurs during the process of switching the dynamic image, that is, when the display panel 1000 switches from one frame to another frame, the viewer may feel the smear of the previous frame (also referred to as dynamic image smear), thereby affecting the image display effect.

Based on this, some embodiments of the present disclosure provide a driving method of shift registers, as shown in fig. 7, each shift register 1 includes a plurality of sub-shift registers 10. Each of the sub-shift registers 10 is electrically connected to a plurality of pixel driving circuits in one row of sub-pixels P (see fig. 2 and 3), and in conjunction with fig. 18 and 22, each of the sub-shift registers 10 corresponds to one row scanning period in one frame period, and each row scanning period includes a scanning phase P6 and a black insertion phase P7.

It should be noted that, the scanning stage P6 in one row scanning period corresponding to each sub-shift register 10 corresponds to the reset stage P1 and the data writing stage P2 electrically connected to the plurality of pixel driving circuits in one row of sub-pixels P; the descriptions of the reset phase P1 and the data writing phase P2 may be referred to above, and will not be repeated here. The black inserting stage P7 in a row scanning period corresponding to each sub-shift register 10 corresponds to a black inserting writing stage P4 electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P, and the relevant description of the black inserting writing stage P4 will be omitted herein.

In some embodiments, the plurality of line scan periods corresponding to the plurality of sub-shift registers 10 include at least M line scan period groups, each line scan period group includes N line scan periods, and the timings of the scan phases P6 of the N line scan periods are the same; m is greater than or equal to 1, N is greater than or equal to 2, and M and N are integers. In this case, in the shift register 1, each group of the line scanning periods can save at least the reference time difference of the times at which the two scanning phases start in the case where the scanning signals are output line by line for N-1 adjacent two line scanning periods. For example, each row scan period group may save the duration of the data writing phase P2 for N-1 sub-pixels P. In this way, the group of M line scan periods in the shift register 1 can save at least the duration of the data writing phase P2 of the m× (N-1) subpixel P during one frame period. Fig. 18 is a diagram illustrating an example in which one line scanning period group 20 includes two line scanning periods, and fig. 22 is a diagram illustrating an example in which two line scanning period groups 20 each include two line scanning periods.

The time when the black inserting stage P7 of the line scanning period starts is after the scanning stage P6 of the last line scanning period of the plurality of line scanning periods, and the duration of each black inserting stage P7 is smaller than or equal to the reference time difference of the time when two adjacent line scanning periods start under the condition that scanning signals are output line by line. For example, the duration of each black insertion stage P7 is less than or equal to the duration of the data writing stage P2 of the adjacent sub-pixel P. Further, the black insertion stage P7 of the plurality of line scanning periods includes at most m× (N-1) kinds of timings. That is, the black insertion stage P7 in the shift register 1 occupies at most the duration of the data writing stage P2 of the m× (N-1) subpixel P in one frame period.

As can be seen from the above, in the driving method of the shift register provided in some embodiments of the present disclosure, the timing of the scan phase P6 of at least two line scan periods is the same in one frame period, so that the idle time is saved, and the black insertion is performed by using the saved idle time. Therefore, in the driving method of the shift register provided in some embodiments of the present disclosure, under the condition of a certain refresh frequency, the time of the black inserting stage P7 may be increased on the basis of not compressing the time of each scanning stage P6, that is, a black picture is inserted in the process that the sub-pixel P emits light to perform normal image display, so as to increase MPRT (Motion Picture Response Time, dynamic image response time), improve the phenomenon of dynamic image smear, and improve the image display effect.

In some embodiments, in each shift register 1, referring to fig. 18 and 20, the timings of the black insertion stage P7 of the plurality of line scanning periods are the same.

Illustratively, the shift register 1 includes eight sub-shift registers 10, and the eight sub-shift registers 10 respectively correspond to eight line scanning periods in one frame period. As shown in fig. 18 and 20, eight line scanning periods include one line scanning period group, each line scanning period group includes two line scanning periods, and the timings of eight black insertion phases P7 of the eight line scanning periods are the same.

In other embodiments, referring to fig. 22, in each shift register 1, the black inserting stage P7 of the plurality of line scanning periods includes at least two timings, and the black inserting stage P7 of the relatively preceding line scanning period is earlier in time than the black inserting stage P7 of the relatively succeeding line scanning period.

Illustratively, the shift register 1 includes eight sub-shift registers 10, and the eight sub-shift registers 10 respectively correspond to eight line scanning periods in one frame period. Wherein, as shown in fig. 22, eight line scanning periods include two line scanning period groups, each line scanning period group including two line scanning periods. The eight black inserting stages P7 of the eight line scanning periods include two timings, the timings of the black inserting stages P7 of the first four line scanning periods are the same, the timings of the black inserting stages P7 of the second four line scanning periods are the same, and the timings of the black inserting stages P7 of the first four line scanning periods are earlier than the timings of the black inserting stages P7 of the second four line scanning periods.

In still other embodiments, referring to fig. 24, the black inserting stage P7 of the plurality of line scan periods includes at least two timings, and the timings of the black inserting stage P7 of at least two line scan periods are the same.

Illustratively, as shown in fig. 24, the shift register 1 includes eight sub-shift registers 10, and the eight sub-shift registers 10 respectively correspond to eight line scanning periods in one frame period. Wherein the eight line scanning periods include four line scanning period groups, each line scanning period group including two line scanning periods; the eight black inserting stages P7 of the eight line scanning periods include four kinds of timings, and the timings of the black inserting stages P7 of each line scanning period group are the same.

Some embodiments of the present disclosure also provide a shift register 1 for performing the driving method of the shift register as described in any of the above embodiments. As shown in fig. 7 and 8, each shift register 1 includes a plurality of sub-shift registers 10. Each sub-shift register 10 is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P (see fig. 2 and 3). The sub shift register 10 includes an input circuit 11 and an output circuit 12.

In some embodiments, as shown in fig. 7 and 8, the Input circuit 11 is coupled to an Input signal terminal Input (shown in the drawings and abbreviated as Iput hereinafter) and a first node N1. Wherein the input circuit 11 is configured to transmit a scan input signal to the first node N1 in response to the scan input signal received at the input signal terminal Iput; and transmitting the black inserted input signal to the first node N1 in response to the black inserted input signal received at the input signal terminal Iput.

For example, in the case where the level of the input signal terminal Iput is high, the input circuit 11 may be turned on by the scan input signal or the black insertion input signal, and transmit the scan input signal or the black insertion input signal to the first node N1, and charge the first node N1 such that the voltage of the first node N1 increases.

It should be noted that, in the embodiment of the present disclosure, the scan input signal and the black insertion input signal are transmitted to the input circuit 11 at different times, respectively.

In some embodiments, as shown in fig. 7 and 8, the Output circuit 12 is coupled to the first node N1, the first clock signal terminal CLKE, and the first Output signal terminal Output1 (which is abbreviated as "op ut 1" in the drawings and below). Wherein the output circuit 12 is configured to transmit the scan clock signal received at the first clock signal terminal CLKE to the first output signal terminal op ut1 in a case where the scan input signal is transmitted to the first node, so that the first output signal terminal op ut1 outputs the scan signal; and, in the case where the black insertion input signal is transmitted to the first node N1, the black insertion clock signal received at the first clock signal terminal CLKE is transmitted to the first output signal terminal Oput1 to cause the first output signal terminal Oput1 to output the black insertion signal.

Illustratively, in the case where the voltage of the first node N1 is at a high level, the output circuit 12 may be turned on under the control of the voltage of the first node N1, outputting the first clock signal received at the first clock signal terminal CLKE as a scan signal from the first output signal terminal Oput 1. And, in the case where the voltage of the first node N1 is at the high level, the output circuit 12 may be turned on under the control of the voltage of the first node N1, and output the first clock signal received at the first clock signal terminal CLKE as the black insertion signal from the first output signal terminal Oput 1.

It should be noted that, in the embodiment of the present disclosure, the scan signal and the black insertion signal are output from the first output signal terminal Oput1 at different times, respectively.

In this case, a plurality of pixel driving circuits in the same row of sub-pixels P are electrically connected to the same gate line GL. The first output signal terminal Oput1 of one sub-shift register 10 may be electrically connected to the first scanning signal terminal G1 and the second scanning signal terminal G2 of the plurality of pixel driving circuits in the corresponding row of sub-pixels P through the gate line GL, and the scanning signal and the black insertion signal outputted from the first output signal terminal Oput1 may also be transmitted to the first scanning signal terminal G1 and the second scanning signal terminal G2 of the plurality of pixel driving circuits through the gate line GL.

In some embodiments, referring to FIG. 7, the shift register 1 includes M sub-shift register groups 20, M is equal to or greater than 1, and M is an integer. Each sub-shift register group 20 includes N adjacent sub-shift registers 10, N.gtoreq.2, where N is an integer. Wherein the N sub shift registers 10 are configured to receive scan clock signals having the same timing to output scan signals having the same timing (see fig. 18).

In addition, the time for starting outputting the black signal is after the pixel driving circuit of the row of sub-pixels P connected to the last sub-shift register 10 of the X sub-shift registers 10 completes the writing of the data signal, so as to avoid the interference between the black signal and the scan signal.

The beneficial effects of the shift register provided by some embodiments of the present disclosure are the same as those of the driving method of the shift register provided by the above technical solution, and are not described herein.

As shown in fig. 3, the first scan signal terminal G1 and the second scan signal terminal G2 of the plurality of pixel driving circuits in the same row of sub-pixels P are electrically connected to the same gate line GL.

As described above, the pixel driving circuit in the sub-pixel P, as shown in fig. 6, for example, one frame period may include a display period, a black insertion period, and a blanking period, which are sequentially performed. The black insertion period includes a black insertion writing phase P4 and a black insertion holding phase P5.

In the display period, the voltage of the first node N1 is first raised by the input circuit 11. In response to the scan input signal received at the input signal terminal Iput, the input circuit 11 is turned on and charges the first node N1, and the output circuit 12 may be turned on under control of the voltage of the first node N1, outputting the first clock signal as a scan signal from the first output signal terminal op ut 1.

In the reset phase P1 and the data writing phase P2, the input circuit 11 is turned off, the voltage of the first node N1 is maintained at a high level, the output circuit 12 is maintained in a turned-on state by the voltage of the first node N1, and the level of the first clock signal output from the first output signal terminal Oput1 is at a high level. In the light emitting stage P3, the voltage of the first node N1 is at a low level, the output circuit 12 is turned off, the level of the signal output from the first output signal terminal Oput1 is at a low level, and the driving transistor T2 is turned on under the control of the voltage of the first node G to drive the light emitting device to emit light.

At a certain time during the light emitting process of the light emitting device (i.e. the time when the light emitting phase P3 and the black inserting writing phase P4 alternate in fig. 6), after the input circuit 11 is turned on and charges the first node N1 in response to the black inserting input signal received at the input signal terminal Iput, the output circuit 12 may be turned on under the control of the voltage of the first node N1, and output the first clock signal as the black inserting signal from the first output signal terminal Oput 1.

At this time, the black insertion signal is transmitted to the first scan signal terminal G1 and the second scan signal terminal G2 of the corresponding pixel driving circuit. The level of the black insertion signal is high, the switching transistor T1 is turned on under the control of the black insertion signal, and a data signal of low level or lower (may also be referred to as a black insertion data signal) is transmitted to the second node G; the sensing transistor T3 is turned on under the control of the black insertion signal, and transmits a low-level reset signal to the third node S. At this time Vgs (i.e., the voltage difference between the second node G and the third node S) is smaller than Vth (i.e., the threshold voltage of the driving transistor T2), the sub-pixel P stops emitting light and switches to a black picture. In the black insertion holding period t5, the sub-pixel P is continuously displayed as a black screen.

That is, the present disclosure can insert a black picture in the process of emitting light from the sub-pixel P to perform normal image display, so that MPRT (Motion Picture Response Time, dynamic image response time) can be increased without increasing refresh frequency, a phenomenon of dynamic image smear can be improved, and an image display effect can be improved.

In addition, by controlling the writing time of the black signal and the black data signal, the ratio of the time of normal light emission of the sub-pixel P to the time of keeping the sub-pixel P as a black picture can be controlled, thus being convenient for adjusting MPRT, further being beneficial to improving the phenomenon of dynamic image smear and improving the image display effect.

In the case where the shift register 1 includes eight sub-shift registers 10, the eight line scanning periods include one line scanning period group, each line scanning period group includes two line scanning periods, and the timings of eight black insertion phases P7 of the eight line scanning periods are the same, as shown in fig. 7 and 18, the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include one sub-shift register group 20, each sub-shift register group 20 includes two adjacent sub-shift registers 10, and the timings of eight black insertion signals outputted by the eight sub-shift registers 10 are the same.

In the case where the shift register 1 includes eight sub-shift registers 10, eight black inserting stages P7 of eight line scanning periods include two timings, timings of black inserting stages P7 of the first four line scanning periods are the same, timings of black inserting stages P7 of the last four line scanning periods are the same, referring to fig. 7 and 22, the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include two sub-shift register groups 20, each sub-shift register group 20 includes two adjacent sub-shift registers 10, and eight black inserting signals output by the eight sub-shift registers 10 include two timings. Wherein, the eight sub-shift registers 10 have the same timing sequence of the four black insertion signals output by the first four sub-shift registers 10; the timings of the four black insertion signals outputted from the last four sub-shift registers 10 are the same, and the time of the black insertion signals outputted from the first four sub-shift registers 10 is earlier than the time of the black insertion signals outputted from the last four sub-shift registers 10.

The shift register 1 comprises eight sub-shift registers 10, wherein eight line scanning periods comprise four line scanning period groups, and each line scanning period group comprises two line scanning periods; in the case where the eight black inserting stages P7 of the eight line scanning periods include four timings and the timings of the black inserting stages P7 of each line scanning period group are the same, referring to fig. 7 and 24, the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include four sub-shift register groups 20, and the eight black inserting signals output by the eight sub-shift registers 10 include four timings. The eight sub-shift registers 10, each sub-shift register group 20 includes two adjacent sub-shift registers 10 outputting two black insertion signals with the same timing, and the time of outputting the black insertion signal is earlier than the time of outputting the black insertion signal by the relatively rear sub-shift register group 20.

In some embodiments, as shown in fig. 7 and 8, the output circuit 12 is further coupled to the second clock signal terminal CLKD and the cascade signal terminal CR. The output circuit 12 is further configured to transmit the second clock signal received at the second clock signal terminal CLKD to the cascade signal terminal CR in a case where the scan input signal is transmitted to the first node N1, so that the cascade signal terminal CR outputs the scan cascade signal.

Illustratively, in the case where the voltage of the first node N1 is at a high level, the output circuit 12 may be turned on under the control of the voltage of the first node N1, outputting the second clock signal received at the second clock signal terminal CLKD as a scan cascade signal from the cascade signal terminal CR.

In some embodiments, as shown in fig. 8 and 9, the above-described input circuit 11 includes a scan input circuit 111 and a black insertion input circuit 112.

As shown in fig. 9 and 10, the scan input circuit 111 is coupled to the scan input signal terminal GI and the first node N1. Wherein the scan input circuit 111 is configured to transmit a scan input signal to the first node N1 in response to the scan input signal received at the scan input signal terminal GI.

For example, in the case that the level of the scan input signal terminal GI is high, the scan input circuit 11 may be turned on by the scan input signal, and transmit the scan input signal to the first node N1, and charge the first node N1, so that the voltage of the first node N1 increases.

As shown in fig. 9 and 10, the black insertion input circuit 112 is coupled to the black insertion input signal terminal BI and the first node N1. Wherein the black insertion input circuit 112 is configured to transmit a black insertion input signal to the first node N1 in response to a black insertion input signal received at the black insertion input signal terminal BI.

For example, in the case where the level of the black insertion input signal terminal BI is high, the black insertion input circuit 112 may be turned on by the scan input signal and transmit the scan input signal to the first node N1, and charge the first node N1, so that the voltage of the first node N1 increases.

It should be noted that, in the embodiment of the present disclosure, the scan input circuit 111 and the black insertion input circuit 112 are turned on at different times, respectively.

In the shift register 1, in the case where 1+.L, and L is an integer, the scan input signal terminal GI of the first L stage sub-shift register 10 is configured to be coupled with the scan initialization signal line STV2 (see FIG. 15); the scan input signal terminal GI of the remaining stage of the sub-shift register 10 is coupled to the cascade signal terminal CR of the previous sub-shift register 10, so that the scan cascade signal outputted from each sub-shift register 10 can be used as the scan input signal of the next sub-shift register 10, thereby realizing cascade display.

Accordingly, in the shift register 1, in the case where 1+.s, and S is an integer, the black insertion input signal terminal BI of the previous S-stage sub-shift register 10 is configured to be coupled with the black insertion initialization signal line STV1 (see fig. 15); the black insertion input signal terminal BI of the remaining stage of the sub-shift register 10 is coupled to the first node N1 of the previous one of the sub-shift registers 10, so that the high level received at the first node N1 of each of the sub-shift registers 10 can be used as the black insertion input signal of the next one of the sub-shift registers 10.

It should be noted that, the cascade signal output at the cascade signal terminal CR is used as the black insertion input signal of a certain sub-shift register 10; alternatively, the high level received at the first node N1 may be used as the black insertion input signal of a certain sub shift register 10, and the disclosure is not limited herein.

In some embodiments, one shift register 1 includes a plurality of sub-shift registers 10, and each sub-shift register 10 includes a black insertion input circuit 112.

In other embodiments, as shown in fig. 11 and 12, among the plurality of sub-shift registers 10 included in one shift register 1, the sub-shift registers 10 having the same black insertion timing may share one black insertion input circuit 112. Illustratively, one sub-shift register group 20 includes two sub-shift registers 10, and the two sub-shift registers 10 may share one black insertion input circuit 112.

Here, by sharing one black insertion input circuit 112 with the sub shift registers 10 included in the sub shift register group 20, the number of black insertion input circuits 112 can be reduced, the structure of the shift register 1 can be simplified, and the yield of the shift register 1 can be improved.

Moreover, by adopting the above arrangement, a smaller number of black insertion input circuits 112 can be adopted to realize the control of the plurality of sub-shift registers 10 for black insertion at the same time sequence, which is beneficial to reducing the difficulty of controlling the plurality of sub-shift registers 10 to output black insertion signals at the same time.

In some embodiments, as shown in fig. 10, the above-described black insertion input circuit 112 includes a black insertion control sub-circuit 113, a black insertion input sub-circuit 114, and a black insertion transmission sub-circuit 115.

As shown in fig. 10, the black insertion control sub-circuit 113 is electrically connected to the third clock signal terminal BCK1, the black insertion input signal terminal BI, the first voltage signal terminal VGL1, and the first black insertion node M. Wherein the black insertion control sub-circuit 113 is configured to transmit the black insertion input signal received at the black insertion input signal terminal BI to the first black insertion node M under the control of the third clock signal.

Here, the first voltage signal terminal VGL1 may be configured to transmit a direct current low level signal (e.g., lower than or equal to a low level portion of the clock signal). Illustratively, the first voltage signal terminal VGL1 is grounded.

For example, in the case where the level of the third clock signal is high, the black insertion control sub-circuit 113 is turned on under the control of the third clock signal, transmits the black insertion input signal received at the black insertion input signal terminal BI to the first black insertion node M, and charges the first black insertion node M so that the voltage of the first black insertion node M increases.

As shown in fig. 10, the black insertion input sub-circuit 114 is electrically connected to the first black insertion node M, the fourth clock signal terminal BCK2, and the second black insertion node K. Wherein the black insertion input sub-circuit 114 is configured to transmit the fourth clock signal received at the fourth clock signal terminal BCK2 to the second black insertion node K under the control of the voltage of the first black insertion node M.

For example, in the case where the black insertion input sub-circuit 114 is turned on and charges the first black insertion node M such that the voltage of the first black insertion node M increases, the black insertion input sub-circuit 114 may be turned on under the control of the voltage of the first black insertion node M, receive and transmit the fourth clock signal to the second black insertion node K.

As shown in fig. 10, the black insertion transmission sub-circuit 115 is electrically connected to the fourth clock signal terminal BCK2, the second black insertion node K, and the first node N1. Wherein the black insertion transmitting sub-circuit 115 is configured to transmit the fourth clock signal from the second black insertion node K to the first node N1 under the control of the fourth clock signal.

For example, in the case where the level of the fourth clock signal is high, the black insertion transmission sub-circuit 115 may be turned on under the control of the fourth clock signal to transmit the fourth clock signal from the second black insertion node K to the first node N1. Since the level of the fourth clock signal from the second black insertion node K is also a high level, the first node N1 can be charged so that the voltage of the first node N1 increases.

In consideration of the structure of the black insertion input circuit 112, the arrangement of the black insertion input circuit 112 shared in the same shift register group 10 includes various arrangements, and may be specifically selected according to actual needs.

Here, a case where one black insertion input circuit 112 is shared by a plurality of sub-shift registers 10 included in the same sub-shift register group 20 will be schematically described.

In some embodiments, the black insertion input circuit 112 includes a black insertion transmission sub-circuit 115. The black insertion transmission sub-circuit 115 is electrically connected to the first node N1 of the plurality of sub-shift registers 10 included in the same sub-shift register group 20.

In other embodiments, as shown in fig. 10 and 12, the black insertion input circuit 112 includes a plurality of black insertion transmission sub-circuits 115, the number of the black insertion transmission sub-circuits 115 is the same as the number of the sub-shift registers 10 included in the sub-shift register group 20, and one black insertion transmission sub-circuit 115 is electrically connected to the first node N1 of one sub-shift register 10 of the sub-shift register group 20.

Here, the configurations of the scan input circuit 111, the black insertion input circuit 112, and the output circuit 12 include various configurations, and can be selected and set according to actual needs. The following schematically describes the structures of the scan input circuit 111, the black insertion input circuit 112, and the output circuit 12.

In some embodiments, as shown in fig. 10, the input circuit 111 includes a first transistor M1.

Illustratively, as shown in fig. 10, the control electrode of the first transistor M1 is electrically connected to the scan input signal terminal GI, the first electrode of the first transistor M1 is electrically connected to the scan input signal terminal GI, and the second electrode of the first transistor M1 is electrically connected to the first node N1.

For example, in case that the level of the scan input signal is high, the first transistor M1 may be turned on under control of the scan input signal, receive the scan input signal, and transmit the scan input signal to the first node N1 such that the voltage of the first node N1 increases.

In some embodiments, as shown in fig. 10, the black insertion control sub-circuit 113 includes a second transistor M2 and a first capacitor C1.

Illustratively, as shown in fig. 10, the control electrode of the second transistor M2 is electrically connected to the third clock signal terminal BCK1, the first electrode of the second transistor M2 is electrically connected to the black insertion input signal terminal BI, and the second electrode of the second transistor M2 is electrically connected to the first black insertion node M.

For example, in case that the level of the first clock signal is high, the second transistor M2 may be turned on under the control of the third clock signal, transmit the black insertion input signal received at the black insertion input signal terminal BI to the first black insertion node M, and charge the first black insertion node M such that the voltage of the first black insertion node M increases.

Illustratively, as shown in fig. 10, a first terminal of the first capacitor C1 is electrically connected to the first black insertion node M, and a second terminal of the first capacitor C1 is electrically connected to the first voltage signal terminal VGL 1.

For example, the first capacitor C1 is also charged during the process of turning on the second transistor M2 and charging the first black insertion node M. After the second transistor M2 is turned off, the first capacitor C1 may be discharged such that the voltage of the first black insertion node M is maintained at a high voltage.

In some embodiments, as shown in fig. 10, the black inserted input sub-circuit 114 includes a third transistor M3.

Illustratively, as shown in fig. 10, the control electrode of the third transistor M3 is electrically connected to the first black insertion node M, the first electrode of the third transistor M3 is electrically connected to the fourth clock signal terminal BCK2, and the second electrode of the third transistor M3 is electrically connected to the second black insertion node K.

For example, in a case where the second transistor M2 is turned on and charges the first black insertion node M such that the voltage of the first black insertion node M increases, the third transistor M3 may be turned on under control of the voltage of the first black insertion node M, receive and transmit the fourth clock signal to the second black insertion node K.

In some embodiments, as shown in fig. 10, the black inserted transmission sub-circuit 115 includes a fourth transistor M4.

Illustratively, as shown in fig. 10, the control electrode of the fourth transistor M4 is electrically connected to the fourth clock signal terminal BCK2, the first electrode of the fourth transistor M4 is electrically connected to the second black insertion node K, and the second electrode of the fourth transistor M4 is electrically connected to the first node N1.

For example, in the case where the level of the second clock signal is high, the fourth transistor M4 may be turned on under the control of the fourth clock signal, transmit the fourth clock signal from the second black insertion node K to the first node N1, and charge the first node N1 such that the voltage of the first node N1 increases.

In some embodiments, as shown in fig. 10, the output circuit 12 includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.

Illustratively, as shown in fig. 10, the control electrode of the fifth transistor M5 is electrically connected to the first node N1, the first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKD, and the second electrode of the fifth transistor M5 is electrically connected to the cascade signal terminal CR.

For example, in case that the voltage of the first node N1 is high, the fifth transistor M5 may be turned on under the control of the first node N1, and the second clock signal received from the second clock signal terminal CLKD may be outputted from the cascade signal terminal CR as the scan cascade signal.

Illustratively, as shown in fig. 10, the control electrode of the sixth transistor M6 is electrically connected to the first node N1, the first electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLKE, and the second electrode of the sixth transistor M6 is electrically connected to the first output signal terminal Oput 1.

For example, in case that the voltage of the first node N1 is high, the sixth transistor M6 may be turned on under the control of the first node N1, and output the first clock signal received from the first clock signal terminal CLKE as the scan signal or the black insertion signal from the first output signal terminal Oput 1. In different periods, the effect of the signal output by the first output signal terminal Oput1 is different, and specific reference may be made to the description in some embodiments, which is not repeated herein.

Illustratively, as shown in fig. 10, a first terminal of the second capacitor C2 is electrically connected to the first node N1, and a second terminal of the second capacitor C2 is electrically connected to the first output signal terminal Oput 1.

For example, during the process of turning on the first transistor M1 and charging the first node N1, the second capacitor C2 is also charged. After the first transistor M1 is turned off, the second capacitor C2 may be discharged such that the voltage of the first node N1 is maintained at a high voltage.

As another example, during the process of turning on the black insertion input circuit 112 and charging the first node N1, the second capacitor C2 is also charged. After the black insertion input circuit 112 is turned off, the second capacitor C2 may be discharged so that the voltage of the first node N1 is maintained at a high voltage.

In some embodiments, in the case where each sub shift register 10 in the scan driving circuit 100 is electrically connected to the first scan signal terminal G1 through the first gate line and is electrically connected to the second scan signal terminal G2 through the second gate line, as shown in fig. 13, the output circuit 12 is further electrically connected to the fifth clock signal terminal CLKF and the second output signal terminal Oput2, the first signal output terminal Oput1 is electrically connected to the first scan signal terminal G1 through the first gate line, and the second output signal terminal Oput2 is electrically connected to the second scan signal terminal G2 through the second gate line.

In the case where the output circuit 12 is further electrically connected to the fifth clock signal terminal CLKF and the second output signal terminal Oput2, the output circuit 12 further includes a seventh transistor M7 and a third capacitor C3.

Illustratively, as shown in fig. 13, the control electrode of the seventh transistor M7 is electrically connected to the first node N1, the first electrode of the seventh transistor M7 is electrically connected to the fifth clock signal terminal CLKF, and the second electrode of the seventh transistor M7 is electrically connected to the second output signal terminal Oput 2.

For example, in case that the voltage of the first node N1 is high, the seventh transistor M7 may be turned on under the control of the first node N1 to output the fifth clock signal received from the fifth clock signal terminal CLKF from the second output signal terminal op ut 2.

Illustratively, as shown in fig. 13, a first terminal of the third capacitor C3 is electrically connected to the first node N1, and a second terminal of the third capacitor C3 is electrically connected to the second output signal terminal Oput 2.

For example, the third capacitor C3 is also charged during the process of turning on the first transistor M1 and charging the first node N1. After the first transistor M1 is turned off, the third capacitor C3 may be discharged such that the voltage of the first node N1 is maintained at a high voltage.

As another example, the third capacitor C3 is also charged during the process of turning on the black insertion input circuit 112 and charging the first node N1. After the black insertion input circuit 112 is turned off, the third capacitor C3 may be discharged so that the voltage of the first node N1 is maintained at a high voltage.

In some embodiments, the sub-shift register 10 may further include other circuit structures, and may specifically be set according to actual needs.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include: a control circuit 13 and a second voltage signal terminal VDD.

As shown in fig. 13, the control circuit 13 is electrically connected to the second voltage signal terminal VDD, the first node N1, the first voltage signal terminal VGL1, and the fourth node N4. Wherein the control circuit 13 is configured to transmit the second voltage signal to the fourth node N4 in response to the second voltage signal received at the second voltage signal terminal VDD, and to transmit the first voltage signal received at the first voltage signal terminal VGL1 to the fourth node N4 under the control of the voltage of the first node N1.

Here, the second voltage signal terminal VDD may be configured to transmit a direct current high level signal (e.g., higher than or equal to a high level portion of the clock signal). Reference herein to "high" and "low" are relative terms. Illustratively, the voltage value of the second voltage signal is greater than the voltage value of the first voltage signal.

For example, the control circuit 13 may receive and transmit the second voltage signal to the fourth node N4 under the control of the second voltage signal. In the case that the voltage of the first node N1 is at the high level, the control circuit 13 may receive and transmit the first voltage signal to the fourth node N4 under the control of the voltage of the first node N1, and perform the pull-down reset on the fourth node N4.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a first reset circuit 14 and a first reset signal terminal STD.

As shown in fig. 13, the first reset circuit 14 is electrically connected to the first reset signal terminal STD, the first node N1, and the first voltage signal terminal VGL 1. The first reset circuit 14 is configured to transmit a first voltage signal to the first node N1 under the control of a first reset signal transmitted by the first reset signal terminal STD.

For example, in the case where the level of the first reset signal is high, the first reset circuit 14 may be turned on under the control of the first reset signal, transmit the first voltage signal received at the first voltage signal terminal VGL1 to the first node N1, and perform a pull-down reset on the first node N1.

It should be noted that, except for the last several sub-shift registers 10 (for example, the last sub-shift register 10 or the last four sub-shift registers 10, etc.), the first reset signal terminal STD of each sub-shift register 10 may be electrically connected to the cascade signal terminal CR of the next sub-shift register 10, and further, the scan cascade signal outputted from the cascade signal terminal CR of the next sub-shift register 10 may be used as the first reset signal of the sub-shift register 10 to implement the cascade reset.

Accordingly, the first reset signal terminal STD of the last several sub-shift registers 10 (e.g., the last sub-shift register 10 or the last four sub-shift registers 10, etc.) may be electrically connected to the display reset signal line, so as to receive the display reset signal transmitted by the display reset signal line as the first reset signal.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a second reset circuit 15 and a second reset signal terminal BTRST.

As shown in fig. 13, the second reset circuit 15 is electrically connected to the first black insertion node M, the second reset signal terminal BTRST, the first node N1, and the first voltage signal terminal VGL 1. The second reset circuit 15 is configured to transmit the first voltage signal to the first node N1 under the control of the voltage of the first black insertion node M and the second reset signal transmitted by the second reset signal terminal BTRST.

For example, when the voltage of the first black insertion node M is at a high level and the level of the second reset signal is at a high level, the second reset circuit 15 may be turned on under the control of the voltage of the first black insertion node M and the second reset signal, and transmit the first voltage signal received at the first voltage signal terminal VGL1 to the first node N1 to perform a pull-down reset on the first node N1.

Here, the second reset circuit 15 may reset the first node N1 after the black insertion, for example.

In some embodiments, as shown in fig. 13, the sub-shift register 10 may further include a third reset circuit 16.

As shown in fig. 13, the third reset circuit 16 is electrically connected to the fourth node N4, the first node N1, and the first voltage signal terminal VGL 1. Wherein the third reset circuit 16 is configured to transmit the first voltage signal to the first node N1 under control of the voltage of the fourth node N4.

For example, in the case where the voltage of the fourth node N4 is at the high level, the third reset circuit 16 may be turned on under the control of the voltage of the fourth node N4, transmit the first voltage signal received at the first voltage signal terminal VGL1 to the first node N1, and perform a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a fourth reset circuit 17 and a third voltage signal terminal VGL2.

As shown in fig. 13, the fourth reset circuit 17 is electrically connected to the first node N1, the cascade signal terminal CR, the first output signal terminal Oput1, the first voltage signal terminal VGL1, and the third voltage signal terminal VGL2. The fourth reset circuit 17 is configured to transmit the first voltage signal to the cascade signal terminal CR and the third voltage signal to the first output signal terminal op ut1 under the control of the first node N1.

For example, in the case where the voltage of the first node N1 is at the high level, the fourth reset circuit 17 may be turned on under the control of the voltage of the first node N1, transmit the first voltage signal received at the first voltage signal terminal VGL1 to the cascade signal terminal CR, perform a pull-down reset on the cascade signal terminal CR, and transmit the third voltage signal received at the third voltage signal terminal VGL2 to the first output signal terminal Oput1, perform a pull-down reset on the first output signal terminal Oput 1.

Here, the third voltage signal terminal VGL2 may be configured to transmit a direct current low level signal (e.g., lower than or equal to a low level portion of the clock signal). Illustratively, the third voltage signal terminal VGL2 is grounded. Wherein, the voltage value of the second voltage signal is larger than the voltage value of the third voltage signal. The voltage value of the first voltage signal and the voltage value of the third voltage signal may be equal or unequal.

Illustratively, as shown in fig. 13, in the case where the output circuit 12 is also electrically connected to the fifth clock signal terminal CLKF and the second output signal terminal Oput2, the fourth reset circuit 17 is also electrically connected to the second output signal terminal Oput2. The fourth reset circuit 17 is further configured to transmit the third voltage signal to the second output signal terminal Oput2 under the control of the first node N1.

For example, in the case where the voltage of the first node N1 is at a high level, the fourth reset circuit 17 may be turned on under the control of the voltage of the first node N1, transmit the third voltage signal received at the third voltage signal terminal VGL2 to the second output signal terminal op ut2, and perform a pull-down reset on the second output signal terminal op ut 2.

The structures of the control circuit 13, the first reset circuit 14, the second reset circuit 15, the third reset circuit 16 and the fourth reset circuit 17 include various structures, and can be selected and set according to actual needs. The configuration of the control circuit 13, the first reset circuit 14, the second reset circuit 15, the third reset circuit 16, and the fourth reset circuit 17 is schematically described below.

In some embodiments, as shown in fig. 13, the control circuit 13 includes an eighth transistor M8 and a ninth transistor M9.

Illustratively, as shown in fig. 13, the control electrode of the eighth transistor M8 is electrically connected to the second voltage signal terminal VDD, the first electrode of the eighth transistor M8 is electrically connected to the second voltage signal terminal VDD, and the second electrode of the eighth transistor M8 is electrically connected to the fourth node N4 and the first electrode of the ninth transistor M9.

For example, the eighth transistor M8 may be turned on under the control of the second voltage signal, and receive and transmit the second voltage signal to the fourth node N4, and charge the fourth node N4, so that the voltage of the fourth node N4 rises.

Illustratively, as shown in fig. 13, the control electrode of the ninth transistor M9 is electrically connected to the first node N1, and the second electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VGL 1.

For example, in the case where the voltage of the first node N1 is at a high level, the ninth transistor M9 may be turned on under the control of the first node N1, receive and transmit the first voltage signal to the fourth node N4, and perform a pull-down reset on the fourth node N4.

In some embodiments, as shown in fig. 13, the first reset circuit 14 includes a tenth transistor M10.

Illustratively, as shown in fig. 13, the control electrode of the tenth transistor M10 is electrically connected to the first reset signal terminal STD, the first electrode of the tenth transistor M10 is electrically connected to the first node N1, and the second electrode of the tenth transistor M10 is electrically connected to the first voltage signal terminal VGL 1.

For example, in the case where the level of the first reset signal is high, the tenth transistor M10 may be turned on under the control of the first reset signal, receive and transmit the first voltage signal to the first node N1, and perform a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the second reset circuit 15 includes an eleventh transistor M11 and a twelfth transistor M12.

Illustratively, as shown in fig. 13, the control electrode of the eleventh transistor M11 is electrically connected to the first black insertion node M, the first electrode of the eleventh transistor M11 is electrically connected to the first node N1, and the second electrode of the eleventh transistor M11 is electrically connected to the first electrode of the twelfth transistor M12. The control electrode of the twelfth transistor M12 is electrically connected to the second reset signal terminal BTRST, and the second electrode of the twelfth transistor M12 is electrically connected to the first voltage signal terminal VGL 1.

For example, in the case where the voltage of the first black insertion node M is at a high level and the level of the second reset signal is at a high level, the eleventh transistor M11 may be turned on under the control of the voltage of the first black insertion node M, the twelfth transistor M12 may be turned on under the control of the second reset signal, the twelfth transistor M12 may receive and transmit the first voltage signal to the second pole of the eleventh transistor M11, and then the eleventh transistor M11 may transmit the first voltage signal to the first node N1, and perform a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the third reset circuit 16 includes a thirteenth transistor M13.

Illustratively, as shown in fig. 13, the control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, the first electrode of the thirteenth transistor M13 is electrically connected to the first node N1, and the second electrode of the thirteenth transistor M13 is electrically connected to the first voltage signal terminal VGL 1.

For example, in the case where the voltage of the fourth node N4 is at a high level, the thirteenth transistor M13 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the first voltage signal to the first node N1, and perform a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the fourth reset circuit 17 includes: a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16.

Illustratively, as shown in fig. 13, the control electrode of the fourteenth transistor M14 is electrically connected to the fourth node N4, the first electrode of the fourteenth transistor M14 is electrically connected to the cascade signal terminal CR, and the second electrode of the fourteenth transistor M14 is electrically connected to the first voltage signal terminal VGL1.

For example, in the case that the voltage of the fourth node N4 is at the high level, the fourteenth transistor M14 may be turned on under the control of the voltage of the fourth node N4, and receive and transmit the first voltage signal to the cascade signal terminal CR to perform the pull-down reset on the cascade signal terminal CR.

Illustratively, as shown in fig. 13, the control electrode of the fifteenth transistor M15 is electrically connected to the fourth node N4, the first electrode of the fifteenth transistor M15 is electrically connected to the first output signal terminal Oput1, and the second electrode of the fifteenth transistor M15 is electrically connected to the third voltage signal terminal VGL 2.

For example, in the case where the voltage of the fourth node N4 is at the high level, the fifteenth transistor M15 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the third voltage signal to the first output signal terminal op ut1, and perform the pull-down reset on the first output signal terminal op ut 1.

Illustratively, as shown in fig. 13, the control electrode of the sixteenth transistor M16 is electrically connected to the fourth node N4, the first electrode of the sixteenth transistor M16 is electrically connected to the second output signal terminal Oput2, and the second electrode of the sixteenth transistor M16 is electrically connected to the third voltage signal terminal VGL 2.

For example, in the case where the voltage of the fourth node N4 is at the high level, the sixteenth transistor M16 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the third voltage signal to the second output signal terminal op ut2, and perform the pull-down reset on the second output signal terminal op ut 2.

From the foregoing, one frame period may include, for example, a display period, a black insertion period, and a blanking period that are sequentially performed. Based on this, in some embodiments, as shown in fig. 13, the sub shift register 10 may further include a blanking circuit 18.

In some embodiments, as shown in fig. 13, the blanking circuit 18 is electrically connected to the sixth clock signal terminal CLKA, the selection control signal terminal OE, the scan input signal terminal GI, the first node N1 and the first voltage signal terminal VGL 1. The blanking circuit 18 is configured to transmit the sixth clock signal to the first node N1 under control of the selection control signal at the selection control signal terminal OE, the scan input signal, and the sixth clock signal at the sixth clock signal terminal CLKA.

In some embodiments, one shift register 1 includes a plurality of sub-shift registers 10, and each sub-shift register 10 includes a blanking circuit 18.

In other embodiments, among the plurality of sub-shift registers 10 included in one shift register 1, the sub-shift registers 10 having the same blanking timing may share one blanking circuit 18. Illustratively, one sub-shift register group 20 includes two sub-shift registers 10, and the two sub-shift registers 10 may share one blanking circuit 18.

Here, by sharing one blanking circuit 18 for the sub shift registers 10 included in the sub shift register group 20, the number of blanking circuits 18 can be reduced, the structure of the shift register 1 can be simplified, and the yield of the shift register 1 can be improved.

Moreover, by adopting the above arrangement, a smaller number of blanking circuits 18 can be adopted to realize the control of the plurality of sub-shift registers 10 blanking the same time sequence, which is beneficial to reducing the difficulty of controlling the plurality of sub-shift registers 10 to blank simultaneously.

In some embodiments, as shown in fig. 13, blanking circuit 18 includes a select control sub-circuit 181, a blanking input sub-circuit 182, and a blanking transmit sub-circuit 183.

The selection control sub-circuit 181 is electrically connected to the scan input signal terminal GI, the first blanking node H, the selection control signal terminal OE, the scan input signal terminal GI, the first blanking node H, and the first voltage signal terminal VGL 1. Wherein the selection control sub-circuit 181 is configured to transmit the scan input signal to the first blanking node H under the control of the selection control signal.

Illustratively, in the case where the level of the selection control signal is high, the selection control sub-circuit 181 may be turned on under the control of the selection control signal and transmit the received scan input signal to the first blank node H, charging the first blank node H such that the voltage of the first blank node H increases.

For example, when the sub shift register 10 needs to output the sensing signal, the waveform timing of the selection control signal and the waveform timing of the scan input signal may be made the same, and the selection control sub circuit 181 may be turned on.

In some embodiments, as shown in fig. 13, the blanking input sub-circuit 182 is electrically connected to the first blanking node H, the sixth clock signal terminal CLKA, and the second blanking node Q. Wherein the blanking input sub-circuit 182 is configured to transmit the sixth clock signal to the second blanking node Q under control of the voltage of the first blanking node H.

Illustratively, in the case where the selection control sub-circuit 181 is turned on such that the voltage of the first blanking node H increases, the blanking input sub-circuit 182 may be turned on under the control of the voltage of the first blanking node H, receive the sixth clock signal transmitted by the sixth clock signal terminal CLKA, and transmit the sixth clock signal to the second blanking node Q.

In some embodiments, as shown in fig. 13, the blanking transmission sub-circuit 183 is electrically connected to the sixth clock signal terminal CLKA, the second blanking node Q, and the first node N1. Wherein the blanking transmission sub-circuit 183 is configured to transmit the sixth clock signal from the second blanking node Q to the first node N1 under control of the sixth clock signal.

Illustratively, in the case where the level of the sixth clock signal is high, the blanking transmission sub-circuit 183 may be turned on under the control of the sixth clock signal, and receive the sixth clock signal from the second blanking node Q, transmit the received sixth clock signal to the first node N1, and charge the first node N1 such that the voltage of the first node N1 increases.

The configuration of the selection control sub-circuit 181, the blanking input sub-circuit 182, and the blanking transmission sub-circuit 183 included in the blanking circuit 18 is schematically described below with reference to the drawings.

In some embodiments, as shown in fig. 13, the selection control sub-circuit 181 includes a seventeenth transistor M17 and a fourth capacitor C4.

Illustratively, as shown in fig. 13, the control electrode of the seventeenth transistor M17 is electrically connected to the selection control signal terminal OE, the first electrode of the seventeenth transistor M17 is electrically connected to the scan input signal terminal GI, and the second electrode of the seventeenth transistor M17 is electrically connected to the first blanking node H.

For example, in the case where the level of the selection control signal transmitted by the selection control signal terminal OE is high, the seventeenth transistor M17 may be turned on by the selection control signal, receive and transmit the scan input signal to the first blanking node H, and charge the first blanking node H, so that the voltage of the first blanking node H increases.

Illustratively, as shown in fig. 13, a first terminal of the fourth capacitor C4 is electrically connected to the first blanking node H, and a second terminal of the fourth capacitor C4 is electrically connected to the first voltage signal terminal VGL 1.

For example, in the process in which the seventeenth transistor M17 is turned on and charges the first blanking node H, the fourth capacitor C4 is also charged. This makes it possible to discharge with the fourth capacitor C4 with the seventeenth transistor M17 turned off, so that the first blanking node H remains at a high level.

In some embodiments, as shown in fig. 13, the blanking input subcircuit 182 includes an eighteenth transistor M18.

Illustratively, as shown in fig. 13, the control electrode of the eighteenth transistor M18 is electrically connected to the first blanking node H, the first electrode of the eighteenth transistor M18 is electrically connected to the sixth clock signal terminal CLKA, and the second electrode of the eighteenth transistor M18 is electrically connected to the second blanking node Q.

For example, in case that the voltage of the first blank node H is at a high level, the eighteenth transistor M18 may be turned on under the control of the voltage of the first blank node H to transmit the sixth clock signal received at the sixth clock signal terminal CLKA to the second blank node Q.

In some embodiments, as shown in fig. 13, the blanking transfer subcircuit 183 includes a nineteenth transistor M19.

Illustratively, as shown in fig. 13, the control electrode of the nineteenth transistor M19 is electrically connected to the sixth clock signal terminal CLKA, the first electrode of the nineteenth transistor M19 is electrically connected to the second blanking node Q, and the second electrode of the nineteenth transistor M19 is electrically connected to the first node N1.

For example, in the case that the level of the sixth clock signal transmitted by the sixth clock signal terminal CLKA is high, the nineteenth transistor M19 may be turned on by the sixth clock signal, and receive and transmit the sixth clock signal from the second blanking node Q to the first node N1 to charge the first node N1.

As shown in fig. 14 and 15, some embodiments of the present disclosure further provide a scan driving circuit 100, where the scan driving circuit 100 includes a plurality of shift registers 1 according to any of the above embodiments in cascade connection.

Wherein each shift register 1 comprises X sub-shift registers 10, X is equal to or greater than 2, and X is an integer. The scan driving circuit 100 further includes a plurality of first clock signal line groups 30, and each first clock signal line group 30 includes at least X-mx (N-1) first clock signal lines 31. The first clock signal terminals CLKE of each shift register 1 are coupled to the first clock signal lines 31 of the first clock signal line group 30.

Illustratively, in the case where the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include one sub-shift register group 20, each sub-shift register group 20 includes two adjacent sub-shift registers 10, and the timings of eight black insertion signals outputted by the eight sub-shift registers 10 are the same, each first clock signal line group 30 may include 7 first clock signal lines 31 (CLK 5 to CLK11 or CLK12 to CLK 18), and the timing chart is shown in fig. 19 and 21.

Illustratively, in the case where the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include two sub-shift register groups 20, each sub-shift register group 20 includes two adjacent sub-shift registers 10, and eight black insertion signals outputted by the eight sub-shift registers 10 include two timings, each first clock signal line group 30 may include 6 first clock signal lines 31 (CLK 5 to CLK10 or CLK11 to CLK 16), and the timing chart is shown in fig. 23.

Illustratively, in the case where the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include four sub-shift register groups 20, and eight black insertion signals outputted from the eight sub-shift registers 10 include four timings, each first clock signal line group 30 may include 4 first clock signal lines 31 (CLK 5 to CLK8 or CLK9 to CLK 12), and the timing chart is shown in fig. 25.

Here, in the shift register 1, the first clock signal terminals CLKE of the N sub-shift registers 10 of each sub-shift register group 20 are coupled to the same first clock signal line 31, and different sub-shift register groups 20 are coupled to different first clock signal lines 31. In the shift register 1, the first clock signal terminals CLKE of the remaining sub-shift registers 10 except for the M sub-shift register groups 20 are respectively coupled to different first clock signal lines 31.

In this case, the plurality of sub-shift registers 10 included in each sub-shift register group 20 share one clock signal line, so that the number of clock signal lines can be reduced, the structure of the scan driving circuit 100 can be simplified, and the yield of the scan driving circuit 100 and the display panel 1000, the display device 2000, and the like to which the scan driving circuit is applied can be improved.

The following schematically illustrates the scan driving circuit 100, taking the configuration of the scan driving circuit 100 illustrated in fig. 14 and 15 as an example.

Illustratively, A <1-8>, A <9-16>, A <17-24>, A <25-32> … … A <2145-2152>, A <2153-2160> shown in FIG. 15 represent different shift registers 1, respectively, and each shift register 1 includes eight sub-shift registers 10. A1, A2, A3 … … a15, a16 shown in fig. 15 represent 16 sub-shift registers 10 in the first shift register 1 and the second shift register 1, respectively.

For example, as shown in fig. 14, each shift register 1 includes one sub-shift register group 20, and each sub-shift register group 20 includes two sub-shift registers 10.

As illustrated in fig. 15, the scan driving circuit 100 includes a plurality of clock signal lines, which may include a first control clock signal line CLK1, a second control clock signal line CLK2, a third control clock signal line CLK3, and a fourth control clock signal line CLK4.

For example, in the shift register 1 of the 2Y-1 th, the third clock signal terminal BCK1 of each sub-shift register 10 is electrically connected to the first control clock signal line CLK 1. In the shift register 1 of the 2M-1 th, the fourth clock signal terminal BCK2 of each sub-shift register 10 is electrically connected to the second control clock signal line CLK 2. Wherein Y is a positive integer.

In the shift register 2Y, the third clock signal terminal BCK1 of each sub-shift register 10 is electrically connected to the third control clock signal line CLK 3. In the 2M-th shift register 1, the fourth clock signal terminal BCK2 of each sub-shift register 1 is electrically connected to the fourth control clock signal line CLK 4.

As illustrated in fig. 15, the plurality of clock signal lines included in the scan driving circuit 100 further includes two first clock signal line groups 30, and the two first clock signal line groups 30 include a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, a twelfth clock signal line CLK12, a thirteenth clock signal line CLK13, a fourteenth clock signal line CLK14, a fifteenth clock signal line CLK15, a sixteenth clock signal line CLK16, a seventeenth clock signal line CLK17, and an eighteenth clock signal line CLK18.

For example, in the shift register 1 of the 2Y-1 th, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the first and second

sub-shift registers

10 and 10 are electrically connected to the fifth clock signal line CLK5, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the third sub-shift register 10 are electrically connected to the sixth clock signal line CLK6, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fourth sub-shift register 10 are electrically connected to the seventh clock signal line CLK7, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fifth sub-shift register 10 are electrically connected to the eighth clock signal line CLK8, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the sixth sub-shift register 10 are electrically connected to the ninth clock signal line CLK9, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the seventh sub-shift register 10 are electrically connected to the tenth clock signal line CLK10, and the fourth clock signal terminal CLKD and the eleventh clock signal terminal CLKE of the eighth sub-shift register 10 are electrically connected to the eleventh clock signal line CLK 11.

In the 2Y-th shift register 1, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the first and second

sub-shift registers

10 and 10 are electrically connected to the twelfth clock signal line CLK12, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the third sub-shift register 10 are electrically connected to the thirteenth clock signal line CLK13, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fourth sub-shift register 10 are electrically connected to the fourteenth clock signal line CLK14, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fifth sub-shift register 10 are electrically connected to the fifteenth clock signal line CLK15, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the sixth sub-shift register 10 are electrically connected to the sixteenth clock signal line CLK16, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the seventh sub-shift register 10 are electrically connected to the seventeenth clock signal line CLK17, and the eighth clock signal terminal CLKD and the eighteenth clock signal terminal CLKE of the eighth sub-shift register 10 are electrically connected to the eighteenth clock signal line CLK 18.

It should be noted that the cascade relationship shown in fig. 15 is only an example, and other cascade manners may be adopted in the present disclosure according to actual situations.

In the scan driving circuit 100, the scan input signal terminal GI of each sub-shift register 10 except the first L stage sub-shift register 10 may be coupled with the cascade signal terminal CR of the preceding sub-shift register 10 to implement a cascade display. Wherein L is more than or equal to 1, and L is an integer. It should be noted that the scan input signal terminal GI of the first L stage sub-shift register 10 may be coupled to the scan initialization signal line STV 2.

In the scan driving circuit 100, the scan input signal terminals GI of the first four sub-shift registers 10 are coupled to the scan initialization signal line STV2, and the scan input signal terminals GI of the remaining sub-shift registers 10 are respectively coupled to the cascade signal terminals CR of the fourth sub-shift registers 10 to realize cascade display.

In the scan driving circuit 100, the black insertion input signal terminal BI in each sub-shift register 10, except for the former S-stage sub-shift register 10, may be coupled with the first node N1 of the former sub-shift register 10 to implement cascade black insertion. Wherein S is more than or equal to 1, and S is an integer. It should be noted that the black insertion input signal terminal BI of the previous S stage sub-shift register 10 may be coupled to a black insertion initialization signal.

Illustratively, in the scan driving circuit 100, the black insertion input signal terminal BI of the first eight sub-shift registers 10 is coupled to the black insertion initialization signal line STV1, and the black insertion input signal terminals BI of the remaining sub-shift registers 10 are respectively coupled to the first node N1 of the first eighth sub-shift register 10 to implement cascade black insertion.

Some embodiments of the present disclosure also provide a driving method of a scan driving circuit, which is applied to the scan driving circuit 100 described in any of the above embodiments.

In the scan driving circuit 100, in conjunction with fig. 18 and 24, each frame period includes a plurality of line scan periods, each line scan period including a scan stage P6 and a black insertion stage P7. Each sub shift register 10 of each shift register 1 of the scan driving circuit 100 (see fig. 14) is used to perform one line scan period.

In the scan phase, the sub shift register 10 receives a scan input signal and a scan clock signal, and outputs a scan signal. At this time, the Data signal terminal Data of the pixel driving circuit in the sub-pixel P electrically connected to the sub-shift register 10 receives the display Data signal, so that the driving transistor T2 is turned on to control the row of sub-pixels P electrically connected to the sub-shift register 10 to emit light.

Note that, the scan clock signal is a first clock signal output at the first clock signal terminal CLKE of the output circuit 12 of the sub-shift register 10 when the input circuit 11 of the sub-shift register 10 receives the scan input signal.

In the black insertion stage P7, the sub shift register 10 receives a black insertion input signal and a black insertion clock signal, and outputs a black insertion signal. At this time, the Data signal terminal Data of the pixel driving circuit in the sub-pixel P electrically connected to the sub-shift register 10 receives the black insertion Data signal, so that the driving transistor T2 is turned off to control the row of sub-pixels P electrically connected to the sub-shift register 10 to stop emitting light. Wherein, the voltage of the black insertion data signal is smaller than the voltage of the display data signal.

Note that the black insertion clock signal is a first clock signal output at the first clock signal terminal CLKE of the output circuit 12 of the sub shift register 10 when the input circuit 11 of the sub shift register 10 receives the black insertion input signal.

In some embodiments, as shown in fig. 22 and 24, the black insertion stage P7 of the line scanning period performed by any one of the sub-shift registers 10 is subsequent to the scanning stage P6 of the line scanning period performed by the last sub-shift register 10 of the plurality of shift registers 1 in cascade.

That is, the black insertion signal outputted from any one shift register 1 is after the last sub shift register 10 of the plurality of shift registers 1 in cascade outputs the scan signal. That is, after all the sub-shift registers 10 output the scanning signal so that the sub-pixels electrically connected to the sub-shift registers 10 emit light, all the sub-shift registers 10 are sequentially black inserted.

In this case, in the input circuit 11 of the sub shift register 10, the scan input signal and the black insertion input signal are transmitted at different times, respectively, and the scan input signal and the black insertion input signal may be multiplexed by one circuit. For example, the scan input signal terminal GI of the scan input circuit 111 can also receive a black insertion input signal, so that black insertion can be realized without providing the black insertion input circuit 112, the structure of the scan driving circuit 100 is simplified, and the yield of the scan driving circuit 100 and the display panel 1000, the display device 2000, and the like applied thereto is improved.

In other embodiments, as shown in fig. 18 and 20, the black inserting stage P7 of the line scanning period performed by each sub-shift register 10 of the shift register 1 is after the scanning stage P6 of the line scanning period performed by the plurality of sub-shift registers 10 of the shift register 1 and before the writing of the data signal of the one row sub-pixel P corresponding to the line scanning period performed by one sub-shift register 10 of the other shift registers 1, that is, before the data writing stage P2 of fig. 5.

That is, the sub-shift registers 10 of the shift registers 1 include the black insertion input circuit 112, and the black insertion signal outputted from each shift register 1 is before the data signal writing of the row of the sub-pixels P corresponding to one sub-shift register 10 of the other shift registers 1 after the last sub-shift register 10 of the shift registers 1 outputs the scan signal, i.e., before the data writing stage P2 in fig. 5.

Illustratively, except for the last shift register 1, the black insertion signal output by each shift register 1 is after the last sub-shift register 10 in the shift register 1 outputs the scan signal and before the data signal of the row of the sub-pixels P corresponding to the first sub-shift register 10 in the next shift register 1 is written.

It should be noted that, the black insertion signal output by the last shift register 1 may be after the last sub-shift register 10 in the last shift register 1 outputs the scan signal and before the data signal of the row of the sub-pixels P corresponding to the first sub-shift register 10 in the first shift register 1 is written.

Some embodiments of the present disclosure also provide a driving method of the shift register 1, as shown in fig. 9, 10 and 16, the shift register 1 (see fig. 15) includes a plurality of sub-shift registers 10, each sub-shift register 10 corresponding to one row scanning period in one frame period, the row scanning period including a scanning period P6 and a black insertion period P7.

The time for starting the black inserting stage P7 is the same as the time for starting the writing of the data signal for one row of the sub-pixels P driven by the set row scanning period, and the ratio of the duration of the black inserting stage P7 to the duration of the writing of the data signal for one row of the sub-pixels P driven by the set row scanning period is less than or equal to 1/2. Setting the line scanning period as the line scanning period corresponding to one sub-shift register 10 of the other shift registers 1; for example, the line scanning period is set as the next-stage line scanning period except for the last shift register 1; the set line scanning period corresponding to the last shift register 1 may be the line scanning period corresponding to the first shift register 1.

That is, each shift register 1 in the scan driving circuit 100 performs black insertion using the first half period of the data signal writing of the connected row of sub-pixels P, that is, the first half period of the data writing stage P2 in fig. 5, by using one sub-shift register 10 in the other shift registers 1; that is, the Data signal terminal Data of the pixel driving circuit in the electrically connected row of the sub-shift register 10 of the black insertion stage P7 in the on-going row scanning period is written at most, and the Data signal terminal Data of the pixel driving circuit in the electrically connected row of the sub-shift register 10 of the scanning stage P6 in the on-going row scanning period is the first half of the display Data signal received by the Data signal terminal Data of the pixel driving circuit in the electrically connected row of the sub-pixel P. The voltage of the display Data signal transmitted by the Data signal terminal Data gradually rises from low to high, and Vgs is still smaller than Vth when the voltage of the first node G is the peak voltage corresponding to the first half of the display Data signal. In this way, the voltage of the first node G in the pixel driving circuit in the electrically connected row of the sub-pixels P in the sub-shift register 10 in the black insertion stage P7 is pulled down, so that Vgs is smaller than Vth, and the driving transistor T2 is turned off, so that the sub-pixels P stop emitting light, and switch to black.

That is, in the driving method of the shift register 1 provided in the present disclosure, under the condition of a certain refresh frequency, the black data writing time can be increased on the basis of the time of not compressing the data writing, and a black picture is inserted in the process that the sub-pixel P emits light to perform normal image display, so that MPRT (Motion Picture Response Time, dynamic image response time) is increased, the phenomenon of dynamic image smear is improved, and the image display effect is improved.

Some embodiments of the present disclosure also provide a shift register 1 for performing the driving method of the shift register described in the above embodiments. Referring to fig. 7 and 9, the shift register 1 includes a plurality of sub-shift registers 10, and each sub-shift register 10 is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P (see fig. 2). The sub shift register 10 includes a scan input circuit 111, a black insertion input circuit 112, and an output circuit 12.

It should be noted that, the scan input circuit 111, the black insertion input circuit 112, and the output circuit 12 may refer to the descriptions in some embodiments described above, and will not be described herein.

Here, referring to fig. 16, the time at which the black signal starts to be output is the same as the time at which the row of the sub-pixels P to which the setting sub-shift register 10 is connected starts to write the data signal, that is, the same as the time at which the data writing stage P2 in fig. 5 starts. And, the ratio of the duration of the black insertion signal to the duration of the writing of the data signal of the one row of the sub-pixels P connected to the setting sub-shift register 10 is less than or equal to 1/2, that is, the ratio of the duration of the data writing stage P2 (see fig. 5) of the one row of the sub-pixels P connected to the setting sub-shift register 10 is less than or equal to 1/2. The setting sub-shift register 10 is one sub-shift register 10 among the other shift registers 1. For example, the sub-shift register 10 is set as the first sub-shift register 10 in the next stage shift register 1 except for the last shift register 1; the setting sub-shift register 10 corresponding to the last shift register 1 may be the first sub-shift register 10 in the first shift register 1.

The beneficial effects of the shift register 1 provided in some embodiments of the present disclosure are the same as those of the driving method of the shift register provided in the above technical solution, and are not described herein.

Some embodiments of the present disclosure also provide a scan driving circuit 100 including a plurality of shift registers 1 as described in the above embodiments in cascade.

In some embodiments, the scan driving circuit 100 includes a plurality of first clock signal line groups 30, each first clock signal line group 30 includes at least a plurality of first clock signal lines 31, and the plurality of first clock signal terminals CLKE of each shift register 1 are coupled to the plurality of first clock signal lines 31 of one first clock signal line group 30 in a one-to-one correspondence.

Illustratively, in the case where the shift register 1 includes eight sub-shift registers 10, each of the first clock signal line groups 30 may include 8 first clock signal lines 31 (CLK 5 to CLK12 or CLK13 to CLK 20), for a timing chart, see fig. 17.

The beneficial effects of the scan driving circuit 100 provided in some embodiments of the present disclosure are the same as those of the driving method of the shift register provided in the above technical solution, and are not described herein.

As shown in fig. 2 and 3, some embodiments of the present disclosure further provide a display panel 1000 including the scan driving circuit 100 of any one of the above embodiments and a plurality of sub-pixels P arranged in an array, and the scan driving circuit 100 is electrically connected to the plurality of sub-pixels P.

As shown in fig. 1, some embodiments of the present disclosure further provide a display device 2000 including the display panel 1000 and the timing controller of any of the above embodiments.

The timing controller is electrically connected to the display panel 1000. The timing controller is configured to transmit a scan clock signal and a black insertion clock signal to the display panel 1000. The scan clock signal received at the first clock signal terminal CLKE of each sub-shift register 10 is identical to the scan signal output at the first output signal terminal Oput1 of the sub-shift register 10, and the black insertion clock signal received at the first clock signal terminal CLKE of each sub-shift register 10 is identical to the black insertion signal output at the first output signal terminal Oput1 of the sub-shift register 10. Note that the timing controller is also configured to transmit a scan initialization signal and a black insertion initialization signal to the scan driving circuit 100 of the display panel 1000.

The beneficial effects of the display panel 1000 and the display device 2000 provided in some embodiments of the present disclosure are the same as those of the driving method of the shift register provided in the above technical solution, and are not described herein.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A driving method of a shift register, wherein the shift register includes a plurality of sub-shift registers, each sub-shift register corresponds to a line scanning period in one frame period, and the line scanning period includes a scanning phase and a black insertion phase;

the plurality of line scanning time periods corresponding to the plurality of sub-shift registers comprise at least M line scanning time period groups, each line scanning time period group comprises N line scanning time periods, and the time sequences of the scanning phases of the N line scanning time periods are the same; m is more than or equal to 1, N is more than or equal to 2, and M and N are integers;

the black insertion stage of the line scanning period starts at a time after the scanning stage of the last line scanning period of the plurality of line scanning periods; the duration of the black inserting stage is smaller than or equal to the reference time difference of the starting time of two scanning stages under the condition that scanning signals are output by two adjacent line scanning periods line by line, and the black inserting stage of the plurality of line scanning periods comprises M× (N-1) time sequences at most;

the starting time of the black inserting stage is the same as the starting time of a row of sub-pixels driven by a set row scanning period, wherein the set row scanning period is a row scanning period corresponding to one sub-shift register of other shift registers.

2. The driving method according to claim 1, wherein timings of black insertion phases of the plurality of line scanning periods are the same; or,

the black inserting stage of the plurality of line scanning periods comprises at least two time sequences, and the time sequences of the black inserting stages of at least two line scanning periods are the same; or,

the black inserting stage of the plurality of line scanning periods includes at least two kinds of time sequences, and the time of the black inserting stage of the relatively preceding line scanning period is earlier than that of the black inserting stage of the relatively following line scanning period.

3. The driving method according to claim 1 or 2, wherein the shift register includes eight sub shift registers, the eight sub shift registers corresponding to eight line scanning periods, respectively, in one frame period;

wherein the eight line scanning periods comprise a line scanning period group, each line scanning period group comprises two line scanning periods, and the eight black inserting phases of the eight line scanning periods have the same time sequence;

or, the eight line scanning periods include two line scanning period groups, each line scanning period group including two line scanning periods; the eight black inserting stages of the eight line scanning periods comprise two time sequences, the time sequences of the black inserting stages of the first four line scanning periods are identical, and the time sequences of the black inserting stages of the last four line scanning periods are identical;

Or, the eight line scanning periods include four line scanning period groups, each line scanning period group including two line scanning periods; the eight black inserting stages of the eight line scanning periods include four kinds of timings, and timings of the black inserting stages of each line scanning period group are the same.

4. A shift register for performing the driving method of the shift register according to any one of claims 1 to 3; the shift register comprises a plurality of sub-shift registers, and each sub-shift register is electrically connected with one row of sub-pixels; the sub shift register includes:

the input circuit is coupled with the input signal end and the first node; the input circuit is configured to transmit a scan input signal received at the input signal terminal to the first node in response to the scan input signal; and transmitting the black inserted input signal to the first node in response to the black inserted input signal received at the input signal terminal;

the output circuit is coupled with the first node, the first clock signal end CLKE and the first output signal end; the output circuit is configured to transmit a scan clock signal received at the first clock signal terminal to the first output signal terminal in a case where the scan input signal is transmitted to the first node, so that the first output signal terminal outputs a scan signal; and transmitting the black inserted clock signal received at the first clock signal terminal to the first output signal terminal under the condition that the black inserted input signal is transmitted to the first node, so that the first output signal terminal outputs a black inserted signal;

The shift register comprises M sub-shift register groups, each sub-shift register group comprises N adjacent sub-shift registers, M is more than or equal to 1, N is more than or equal to 2, and M and N are integers; the N sub-shift registers are configured to receive scanning clock signals with the same time sequence so as to output scanning signals with the same time sequence;

the time for starting to output the black signal is after the writing of the data signal is completed by one row of sub-pixels connected with the last sub-shift register in the plurality of sub-shift registers; the duration of the black insertion signal is smaller than or equal to the reference time difference of the starting time of two scanning signals under the condition that two adjacent sub-shift registers output the scanning signals row by row; the black insertion signals output by the plurality of sub-shift registers include at most M× (N-1) kinds of timings.

5. A scan driving circuit comprising a plurality of shift registers as claimed in claim 4 in cascade.

6. The scan driving circuit according to claim 5, wherein each of the shift registers comprises X sub-shift registers, X is not less than 2, and X is an integer; the scanning driving circuit further comprises a plurality of first clock signal line groups, wherein each first clock signal line group at least comprises X-M× (N-1) first clock signal lines;

The first clock signal terminals of each shift register are correspondingly coupled with the first clock signal lines of the first clock signal line group.

7. The scan driving circuit according to claim 6, wherein the first clock signal terminals of the N sub-shift registers of each sub-shift register group are coupled to a same first clock signal line, and different sub-shift register groups are coupled to different first clock signal lines;

in the shift register, the first clock signal ends of all the other sub-shift registers except the M sub-shift register groups are respectively coupled with different first clock signal lines.

8. A driving method of a scanning driving circuit, characterized in that it is applied to the scanning driving circuit according to any one of claims 5 to 7, each frame period including a plurality of line scanning periods, each line scanning period including a scanning phase and a black insertion phase; each sub shift register of each shift register of the scan driving circuit is used for executing one row scan period;

in the scanning stage, the sub-shift register receives a scanning input signal and a scanning clock signal and outputs a scanning signal to control a row of sub-pixels electrically connected with the sub-shift register to emit light;

In the black inserting stage, the input circuit receives a black inserting input signal and a black inserting clock signal and outputs a black inserting signal so as to control a row of sub-pixels electrically connected with the sub-shift register to stop emitting light.

9. The driving method according to claim 8, wherein the black insertion stage of the line scanning period performed by each of the sub-shift registers of the shift register is after the scanning stages of the plurality of line scanning periods performed by the plurality of sub-shift registers of the shift register and before the writing of the line sub-pixel data signal corresponding to the line scanning period performed by one of the other sub-shift registers.

10. The driving method according to claim 8, wherein the black insertion stage of the line scanning period performed by any one of the sub-shift registers is subsequent to the scanning stage of the line scanning period performed by the last sub-shift register of the plurality of shift registers in cascade.

11. A driving method of a shift register, wherein the shift register includes a plurality of sub-shift registers, each sub-shift register corresponds to a line scanning period in one frame period, and the line scanning period includes a scanning phase and a black insertion phase; outputting scanning signals row by row in any two adjacent line scanning time periods;

The time for starting the black inserting stage is the same as the time for starting the writing of the data signals of one row of sub-pixels driven by the set row scanning period, the duration of the black inserting stage is smaller than or equal to the reference time difference of the time for starting the two scanning stages of the two adjacent row scanning periods, and the ratio of the duration of the writing of the data signals of one row of sub-pixels driven by the set row scanning period is smaller than or equal to 1/2; the set line scanning period is a line scanning period corresponding to one sub-shift register of the other shift registers.

12. A shift register for performing the driving method of the shift register according to claim 11; the shift register comprises a plurality of sub-shift registers, and each sub-shift register is electrically connected with one row of sub-pixels; the sub shift register includes:

the scanning input circuit is coupled with the scanning input signal end and the first node; the scan in circuit is configured to transmit a scan in signal to the first node in response to the scan in signal received at the scan in signal terminal;

the black insertion input circuit is coupled with the black insertion input signal end and the first node; the black inserted input circuit is configured to transmit a black inserted input signal received at the black inserted input signal terminal to the first node in response to the black inserted input signal;

13. A scan driving circuit comprising a plurality of shift registers as claimed in claim 12 in cascade.

14. A display panel, comprising:

a plurality of subpixels arranged in an array;

the scan driving circuit according to any one of claims 5 to 7 and 13, wherein the scan driving circuit is electrically connected to the plurality of sub-pixels.

15. A display device, comprising:

the display panel of claim 14;

the time sequence controller is electrically connected with the display panel; the timing controller is configured to transmit a scan clock signal and a black insertion clock signal to the display panel; the scanning clock signals received at the first clock signal end of each sub-shift register are identical to the scanning signals output at the first output signal end of the sub-shift register, and the black inserting clock signals received at the first clock signal end of each sub-shift register are identical to the black inserting signals output at the first output signal end of the sub-shift register.