CN113900984B - Circuit and server for interconnection and switching of single node and multiple nodes - Google Patents
Circuit and server for interconnection and switching of single node and multiple nodes Download PDFInfo
- Publication number
- CN113900984B CN113900984B CN202111153094.2A CN202111153094A CN113900984B CN 113900984 B CN113900984 B CN 113900984B CN 202111153094 A CN202111153094 A CN 202111153094A CN 113900984 B CN113900984 B CN 113900984B
- Authority
- CN
- China
- Prior art keywords
- request
- node
- chip
- nodes
- pcie switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000004044 response Effects 0.000 claims description 20
- 230000005540 biological transmission Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Multi Processors (AREA)
Abstract
The invention discloses a circuit for interconnecting and switching single nodes and multiple nodes, which comprises: a processing node; a plurality of request nodes; one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing nodes; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes and send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions. The invention also discloses a corresponding server.
Description
Technical Field
The present invention relates to the field of data transmission technologies, and in particular, to a circuit and a server for interconnecting and switching a single node and multiple nodes.
Background
In a traditional interconnection system of a server GPU (graphics processing unit, a graphic processor) and a CPU (central processing unit, a central processing unit), the GPUs are all in single-to-single interconnection, and in a multi-path CPU system, if a certain CPU is not connected with the GPU, the CPU needs to transmit data through interconnection signals among the CPUs under the condition that the CPU needs to use the GPU, and the data cannot be directly transmitted with the GPU.
In the existing scheme, the GPU is connected with the main CPU in a single point mode, and when the CPU which is not connected with the GPU needs to be used for a GPU processing unit in a multi-path CPU system, data to be processed needs to be transmitted to the main CPU connected with the GPU through an interconnection signal between the CPU and the CPU, and then the data is processed. Thus, the data processing response is not timely, and the waste of CPU and GPU resources is caused.
Disclosure of Invention
In order to solve the above problems, an embodiment of the present invention is to provide a circuit and a server for interconnection and switching between a single node and multiple nodes, and to implement automatic switching of corresponding CPU connections according to image processing requirements by switching between a GPU and multiple CPUs through PCIE Switch, thereby saving resources and improving efficiency.
Based on the above objects, an aspect of the embodiments of the present invention provides a circuit for interconnecting and switching a single node and multiple nodes, including: a processing node; a plurality of request nodes; one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing nodes; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes and send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions.
In some embodiments, the processing chip is further configured to: the processing node is a graphics processor, and the requesting node is a central processing unit.
In some embodiments, the CPLD chip is further configured to: and in response to receiving the request signals sent by the plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
In some embodiments, the PCIE Switch chip is further configured to: and responding to the control instruction sent by the CPLD chip to complete processing, and returning a completion signal to the CPLD chip.
In some embodiments, the CPLD chip is further configured to: and in response to receiving the completion signal returned by the CPLD chip, sending an interconnection signal to the corresponding request node.
In some embodiments, the requesting node is further configured to: and in response to receiving the interconnection signal sent by the CPLD chip, establishing connection with the processing node through PCI scanning, and carrying out data transmission and related operation.
In another aspect of the embodiments of the present invention, there is further provided a server including a circuit for interconnection and switching between a single node and a plurality of nodes as follows: a processing node; a plurality of request nodes; one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing nodes; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes and send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions.
In some embodiments, the processing chip is further configured to: the processing node is a graphics processor, and the requesting node is a central processing unit.
In some embodiments, the CPLD chip is further configured to: and in response to receiving the request signals sent by the plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
In some embodiments, the PCIE Switch chip is further configured to: and responding to the control instruction sent by the CPLD chip to complete processing, and returning a completion signal to the CPLD chip.
In some embodiments, the CPLD chip is further configured to: and in response to receiving the completion signal returned by the CPLD chip, sending an interconnection signal to the corresponding request node.
In some embodiments, the requesting node is further configured to: and in response to receiving the interconnection signal sent by the CPLD chip, establishing connection with the processing node through PCI scanning, and carrying out data transmission and related operation.
The invention has the following beneficial technical effects: through interconnection between the PCIE Switch switching GPU and the plurality of CPUs, corresponding CPU connection is automatically switched according to image processing requirements, resources are saved, and efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a single-node to multi-node interconnect and switch circuit provided by the present invention;
fig. 2 is a schematic diagram of an embodiment of a server provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
Based on the above objects, a first aspect of the embodiments of the present invention proposes an embodiment of a circuit for interconnection and switching of single nodes and multiple nodes. FIG. 1 is a schematic diagram of an embodiment of a circuit for interconnecting and switching single nodes and multiple nodes provided by the present invention. As shown in fig. 1, an embodiment of the present invention includes:
a processing node 100;
a number of requesting nodes 200, 201;
a PCIE Switch chip 300, where one end of the PCIE Switch chip 300 is connected to the plurality of request nodes 200, 201, and the other end is connected to the processing node 100;
the CPLD chip 400 is configured to receive request signals sent by a plurality of request nodes 200, 201, and send a control instruction to the PCIE Switch chip 300 based on the request signals, and the PCIE Switch chip 300 is configured to select one request node 200, 201 to interconnect with the processing node 100 based on the control instruction. Although two requesting nodes are illustrated, other numbers of requesting nodes are within the scope of the invention, as desired.
In this embodiment, the request signals sent by the plurality of request nodes 200 and 201 are sent to the CPLD chip 400, the default idle state of the request signals is 1, when the request node 200 or 201 has an image processing requirement, the request signal is set to 0, and after receiving the switching completion signal of the PCIE Switch chip 300, PCI scanning is performed to establish connection, and then data transmission and related calculation work are performed; the PCIe Switch chip 300 is responsible for switching interconnection between an uplink CPU and a GPU, switching connection between the GPU and a related CPU through a received control signal, and returning a completion signal after switching is completed; the CPLD chip 400 is a control unit that receives a request signal from a request node 200 or 201, controls the PCIe Switch chip 300 to Switch, and switches according to a request priority when a plurality of request nodes 200 and 201 have a request signal from each.
In this embodiment, the processing node is taken as a GPU unit, and the plurality of request nodes are taken as two CPU units CPU0 and CPU1 for illustration. The GPU can be connected with the CPU0 through switching of the PCIe Switch chip, the CPU1 is connected with the CPU0 by default, when the CPU1 sets the request signal 1 to be low level, the CPLD firstly judges whether the request signal 0 of the CPU0 is high level, and if the request signal 0 is high level, the PCIE Switch chip is connected with the GPU through switching of the GPU; if the request signal 0 of the CPU0 is at low level, the state is waited until the request signal 0 of the CPU0 becomes high level, and the CPU1 has the request signal sent out at low level, and the PCIE Switch chip switching GPU is interconnected with the CPU 1. After the switching is completed, the PCIe Switch chip sends a switching completion signal to the corresponding CPU. The method comprises the following specific steps:
powering on, and switching the PCIE Switch chip to the connection of the GPU and the CPU0 by default; when the CPU1 has an image processing requirement, the request signal 1 is pulled down; the CPLD receives the request signal 1, and the CPLD judges whether the request signal 0 is in a high level or not; if the request signal 0 is at a high level, the CPLD interconnects the PCIE Switch chip switching GPU and the CPU1, and returns a completion signal after completion; if the request signal 0 is low level, the CPLD waits for the state until the request signal 0 of the CPU0 becomes high level, and the CPLD interconnects the PCIE Switch chip switching GPU and the CPU1, and returns a completion signal after completion. After receiving the completion signal, the CPLD chip sends out a PCIE Switch chip switching completion signal 1; the CPU1 performs PCI scanning to establish connection, and then performs data transmission and related calculation work.
In some embodiments of the invention, the processing node 100 is a graphics processor and the requesting nodes 200, 201 are central processors.
In this embodiment, the processing node 100 is a GPU unit, and the GPU is an image processor, which is responsible for image and graphics related operations; the plurality of request nodes 200 and 201 are CPU units, a request signal sent by the CPU units is given to the CPLD chip 400, the default idle state of the request signal is 1, when the CPU has an image processing requirement, the request signal is set to 0, PCI scanning is performed to establish connection after the switching completion signal of the PCIE Switch chip 300 is received, and then data transmission and related calculation work are performed; the PCIe Switch chip 300 is responsible for switching interconnection between an uplink CPU and a GPU, switching connection between the GPU and a related CPU through a received control signal, and returning a completion signal after switching is completed; the CPLD chip 400 is a control unit that receives a request signal from a CPU to control the PCIe Switch chip 300 to Switch, and when a plurality of CPUs have a request signal from each CPU, the CPLD chip switches according to the request priority.
In this embodiment, a single GPU card may be automatically switched to connect with a corresponding CPU according to the CPU image processing requirements; and the GPU hardware resource sharing and the quick response are realized.
In some embodiments of the present invention, the CPLD chip 400 is further configured to: in response to receiving the request signals sent by the plurality of request nodes 200, 201, the priority of the request signals is determined, and a control instruction is sent to the PCIE Switch chip 300 based on the priority of the request signals.
In this embodiment, when the plurality of requesting nodes 200 and 201 have the request signals sent out, a control instruction is sent to the PCIE Switch chip 300 according to the request priority to Switch.
In some embodiments of the present invention, PCIE Switch chip 300 is further configured to: in response to the control instruction transmitted to the CPLD chip 400 being processed, a completion signal is returned to the CPLD chip 400.
In some embodiments of the present invention, the CPLD chip 400 is further configured to: in response to receiving the completion signal returned by the CPLD chip 400, an interconnection signal is sent to the corresponding requesting node 200, 201.
In some embodiments of the invention, the requesting node 200, 201 is configured to: in response to receiving the interconnect signal sent by CPLD chip 400, a connection is established with processing node 100 through the PCI scan, and data transmission and related operations are performed.
Based on the above object, a second aspect of the embodiments of the present invention proposes a server. Fig. 2 is a schematic diagram of an embodiment of a server provided by the present invention. As shown in fig. 2, the server 011 includes a single-node and multi-node interconnect and switch circuit 012, and the single-node and multi-node interconnect and switch circuit 012 includes: a processing node; a plurality of request nodes; one end of the PCIE Switch chip is connected with a plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing nodes; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes, send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions.
In some embodiments of the invention, the processing node is a graphics processor and the requesting node is a central processor.
In some embodiments of the invention, the CPLD chip is further configured to: and in response to receiving the request signals sent by the plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
In some embodiments of the invention, the PCIE Switch chip is further configured to: and responding to the control instruction sent to the CPLD chip to process completion, and returning a completion signal to the CPLD chip.
In some embodiments of the invention, the CPLD chip is further configured to: and in response to receiving the completion signal returned by the CPLD chip, sending an interconnection signal to the corresponding request node.
In some embodiments of the invention, the requesting node is configured to: and in response to receiving the interconnection signal sent by the CPLD chip, establishing connection with the processing node through PCI scanning, and carrying out data transmission and related operation.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (8)
1. A circuit for interconnecting and switching between a single node and multiple nodes, comprising:
a processing node;
a plurality of request nodes;
one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing nodes;
one end of the CPLD chip is connected with the request nodes, the other end of the CPLD chip is connected with the PCIE Switch chip,
the CPLD chip is configured to receive request signals sent by the plurality of request nodes, send control instructions to the PCIE Switch chip based on the request signals, select one request node to interconnect with the processing node based on the control instructions, and
the processing node is a graphics processor, and the request node is a central processing unit.
2. The single-node to multi-node interconnect and switch circuit of claim 1, wherein the CPLD chip is further configured to:
and in response to receiving the request signals sent by the plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
3. The single-node to multi-node interconnect and Switch circuit of claim 1, wherein the PCIE Switch chip is further configured to:
and responding to the control instruction sent by the CPLD chip to complete processing, and returning a completion signal to the CPLD chip.
4. The single-node to multi-node interconnect and switch circuit of claim 3, wherein said CPLD chip is further configured to:
and in response to receiving the completion signal returned by the CPLD chip, sending an interconnection signal to the corresponding request node.
5. The single-node to multi-node interconnect and switch circuit of claim 4, wherein the requesting node is configured to:
and in response to receiving the interconnection signal sent by the CPLD chip, establishing connection with the processing node through PCI scanning, and carrying out data transmission and related operation.
6. A server comprising a circuit for interconnecting and switching single nodes to multiple nodes, the circuit comprising:
a processing node;
a plurality of request nodes;
the PCIE Switch chip is used for respectively interconnecting the plurality of request nodes and the processing nodes;
one end of the CPLD chip is connected with the request nodes, the other end of the CPLD chip is connected with the PCIE Switch chip,
the CPLD chip is configured to receive request signals sent by the plurality of request nodes, send control instructions to the PCIE Switch chip based on the request signals, select one request node to interconnect with the processing node based on the control instructions, and
the processing node is a graphics processor, and the request node is a central processing unit.
7. The server of claim 6, wherein the CPLD chip is further configured to:
and in response to receiving the request signals sent by the plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
8. The server of claim 6, wherein the PCIE Switch chip is further configured to: responding to the control instruction sent by the CPLD chip to process and finish, and returning a finishing signal to the CPLD chip;
the CPLD chip is further configured to: responding to the received completion signal returned by the CPLD chip, and then sending an interconnection signal to the corresponding request node;
the requesting node is configured to: and in response to receiving the interconnection signal sent by the CPLD chip, establishing connection with the processing node through PCI scanning, and carrying out data transmission and related operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111153094.2A CN113900984B (en) | 2021-09-29 | 2021-09-29 | Circuit and server for interconnection and switching of single node and multiple nodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111153094.2A CN113900984B (en) | 2021-09-29 | 2021-09-29 | Circuit and server for interconnection and switching of single node and multiple nodes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113900984A CN113900984A (en) | 2022-01-07 |
| CN113900984B true CN113900984B (en) | 2023-06-20 |
Family
ID=79189399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111153094.2A Active CN113900984B (en) | 2021-09-29 | 2021-09-29 | Circuit and server for interconnection and switching of single node and multiple nodes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113900984B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205050131U (en) * | 2015-08-31 | 2016-02-24 | 浪潮电子信息产业股份有限公司 | Circuit supporting random processing starting and high redundancy of multi-path system |
| CN112612741A (en) * | 2020-12-28 | 2021-04-06 | 苏州浪潮智能科技有限公司 | Multi-path server |
| CN112667556A (en) * | 2020-12-23 | 2021-04-16 | 曙光信息产业(北京)有限公司 | GPU server and image processing system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9965367B2 (en) * | 2014-12-17 | 2018-05-08 | Quanta Computer Inc. | Automatic hardware recovery system |
-
2021
- 2021-09-29 CN CN202111153094.2A patent/CN113900984B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205050131U (en) * | 2015-08-31 | 2016-02-24 | 浪潮电子信息产业股份有限公司 | Circuit supporting random processing starting and high redundancy of multi-path system |
| CN112667556A (en) * | 2020-12-23 | 2021-04-16 | 曙光信息产业(北京)有限公司 | GPU server and image processing system |
| CN112612741A (en) * | 2020-12-28 | 2021-04-06 | 苏州浪潮智能科技有限公司 | Multi-path server |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113900984A (en) | 2022-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20190251654A1 (en) | Data processing method, apparatus, and electronic device | |
| US10476697B2 (en) | Network-on-chip, data transmission method, and first switching node | |
| CN102446158A (en) | Multi-core processor and multi-core processor set | |
| CN111404931B (en) | Remote data transmission method based on persistent memory | |
| CN103092807A (en) | Node controller, parallel computing server system and route method | |
| US9985893B2 (en) | Load sharing method and apparatus, and board | |
| CN111488308B (en) | System and method for supporting multi-processor expansion of different architectures | |
| CN111901164A (en) | Adaptive control method, device, equipment and system for OCP NIC network card | |
| CN112131174A (en) | Method, apparatus, electronic device, and computer storage medium supporting communication between multiple chips | |
| CN115934625B (en) | Doorbell knocking method, equipment and medium for remote direct memory access | |
| EP3285173A1 (en) | Cpu interconnecting apparatus, system and control method, control apparatus therefor | |
| CN106230622A (en) | A kind of cluster implementation method and device | |
| CN113900984B (en) | Circuit and server for interconnection and switching of single node and multiple nodes | |
| WO2022188658A1 (en) | Method and circuit for multiplexing usb interface, and electronic device and storage medium | |
| US20220114132A1 (en) | Data Switch Chip and Server | |
| US6810457B2 (en) | Parallel processing system in which use efficiency of CPU is improved and parallel processing method for the same | |
| JP2559918B2 (en) | Synchronous control method for parallel computers | |
| US7206889B2 (en) | Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes | |
| CN113961489A (en) | Data access method, device, equipment and storage medium | |
| JP3375658B2 (en) | Parallel computer and network for it | |
| US7360007B2 (en) | System including a segmentable, shared bus | |
| CN112463670A (en) | Storage controller access method and related device | |
| CN112433971A (en) | Structure, method and medium for realizing processor self-adaptive SATA and NVME M.2 | |
| CN117472844B (en) | Multi-chip module and data processing method | |
| KR20080043983A (en) | Method and system for communicating between processor systems operating with different operating frequencies |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |