CN113889523A - Semiconductor device based on three-dimensional grid field plate structure and manufacturing method thereof - Google Patents
Semiconductor device based on three-dimensional grid field plate structure and manufacturing method thereof Download PDFInfo
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- CN113889523A CN113889523A CN202010623901.1A CN202010623901A CN113889523A CN 113889523 A CN113889523 A CN 113889523A CN 202010623901 A CN202010623901 A CN 202010623901A CN 113889523 A CN113889523 A CN 113889523A
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- 238000009792 diffusion process Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
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- 230000005684 electric field Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
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- 238000005530 etching Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention discloses a semiconductor device based on a three-dimensional grid field plate structure and a manufacturing method thereof. The semiconductor device includes: the substrate is provided with a first conductive through hole and a second conductive through hole which are respectively matched with the source electrode and the drain electrode; the substrate, the body region, the source contact region and the drain contact region are all of a first conductivity type, and the drift region is of a second conductivity type; the drift region is also provided with at least one groove, part of the gate field plate is also extended into the groove, and a first insulating layer is also arranged between the gate field plate and the groove. The semiconductor device provided by the invention simultaneously considers the effects of the gate field plate and the drift region shallow groove, the gate field plate reduces the surface electric field of the drift region, the voltage of the device is improved, and the on-resistance is reduced.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a semiconductor device based on a three-dimensional grid field plate structure and a manufacturing method thereof, and belongs to the technical field of semiconductors.
Background
A structure of a lateral power device in the prior art is shown in fig. 1, where 72 is a gate, 71 is a gate oxide layer, 42 is a source contact region, 41 is a drain heavily doped contact region, 20 is a lateral drift region, 10 is an epitaxial layer or a substrate, 30 is a channel body region contact region, 52 is a source and interconnection via for connecting the source and the body region, 51 is a drain interconnection via, 61 is a thick oxide layer of the lateral drift region, 62 is a gate field plate, and 21 is a trench for isolation; the conventional lateral power device shown in fig. 1 includes a conventional gate field plate structure, the depletion of the drift region is enhanced by using the gate field plate 62, the quality factors of the breakdown voltage and the on-resistance are improved, the size of the isolation trench 21 in the vertical direction is increased, and the effective lateral drift region length is improved; however, the drift region 20 under the isolation trench 21 of the conventional lateral power device can only rely on the intrinsic depletion of the PN junction, and the field plate enhancement RESURF effect is lacking.
Disclosure of Invention
The invention mainly aims to provide a semiconductor device based on a three-dimensional grid field plate structure and a manufacturing method thereof, so as to overcome the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
an embodiment of the present invention provides a semiconductor device based on a three-dimensional gate field plate structure, including: the substrate is provided with a first conductive through hole and a second conductive through hole which are respectively matched with the source electrode and the drain electrode; the substrate and the body region are of a first conductivity type, and the drift region, the source contact region and the drain contact region are of a second conductivity type; the drift region is also provided with at least one groove, part of the gate field plate is also extended into the groove, and a first insulating layer is also arranged between the gate field plate and the groove.
Furthermore, the gate field plate is continuously covered on the surface of the drift region and the inner wall of the groove.
Furthermore, the first insulating layer continuously covers the surface of the drift region and the inner wall of the groove, and the gate field plate is arranged on the first insulating layer.
Further, the ratio of the depth of the groove to the thickness of the drift region is less than 1: 1.
Further, the grooves and the gate field plates are of an integral structure, a continuous groove is formed in the drift region, a continuous gate field plate is arranged on the drift region, or the grooves are of a distributed structure, the gate field plates are of an integral structure, a plurality of grooves are formed in the drift region at intervals, a continuous gate field plate is arranged on the drift region, the gate field plates are matched with the grooves, or the grooves and the gate field plates are of a distributed structure, a plurality of grooves are formed in the drift region at intervals, a plurality of gate field plates are arranged on the drift region at intervals, each gate field plate is matched with one groove, and the gate field plates are all interconnected with the gate.
Further, a second insulating layer is arranged between the grid electrode and the base material.
Furthermore, the material of the second insulating layer includes silicon dioxide.
Furthermore, the material of the first insulating layer includes silicon dioxide, and a ratio of a thickness of the first insulating layer to a thickness of the second insulating layer is greater than 1:1, for example, the thickness of the first insulating layer is more than 3 times that of the second insulating layer.
Further, the material of the substrate comprises silicon.
Further, the body region and the drift region are formed by local processing of the substrate by means of ion implantation and thermal diffusion.
Further, the source contact region is formed by local processing of the body region by means of ion implantation and thermal diffusion, and the drain contact region is formed by local processing of the drift region by means of ion implantation and thermal diffusion.
The embodiment of the invention also provides a manufacturing method of the semiconductor device based on the three-dimensional grid field plate structure, which comprises the following steps:
providing a substrate, wherein a body region, a drift region, a source contact region and a drain contact region are distributed in the substrate;
forming a gate electrode on the substrate;
processing and forming at least one groove in the drift region;
forming a first insulating layer on the surface of the drift region and the inner wall of the groove, forming a gate field plate interconnected with a gate on the first insulating layer, and enabling the local extension of the gate field plate to be arranged in the groove; and
and respectively manufacturing a first conductive through hole and a second conductive through hole which are matched with the source electrode contact region and the drain electrode contact region.
Further, the method for manufacturing the semiconductor device based on the three-dimensional gate field plate structure specifically comprises the following steps: processing and forming a groove which is continuously distributed in the drift region, and forming a grid field plate which is continuously distributed on the drift region, wherein the grid field plate is matched with the groove; or processing a plurality of grooves distributed at intervals in the drift region, forming a grid field plate distributed continuously on the drift region, wherein the grid field plate is matched with the grooves, or processing a plurality of grooves distributed at intervals in the drift region, manufacturing a plurality of grid field plates distributed at intervals on the surface of the drift region, and each grid field plate is matched with one groove.
Further, the gate electrode is disposed on a second insulating layer disposed on the substrate.
Further, the body region and the drift region are formed by local processing of the substrate by means of ion implantation and thermal diffusion.
Further, the source contact region is formed by local processing of the body region by means of ion implantation and thermal diffusion, and the drain contact region is formed by local processing of the drift region by means of ion implantation and thermal diffusion.
Compared with the prior art, the invention has the advantages that:
1) the invention provides a semiconductor device based on a three-dimensional grid field plate structure, which is characterized in that an integral groove or a plurality of grooves distributed at intervals are formed in a drift region through processing, a grid field plate with a three-dimensional structure is formed on the drift region, and the part of the grid field plate, which is positioned in the groove region, is bent downwards and extends into the groove.
2) The semiconductor device based on the three-dimensional gate field plate structure provided by the invention has the advantages that the effects of the gate field plate and the drift region shallow groove are considered, the surface electric field of the drift region is reduced by the gate field plate, the voltage of the device is improved, the on-resistance is reduced, the effective length of the drift region is increased by the groove structure, and the transverse size of the device is shortened.
3) According to the semiconductor device based on the three-dimensional gate field plate structure, the gate field plate acts above the groove, the area of the device accumulation layer is increased, the quasi-saturation effect of the device can be improved under the gate high-voltage condition, and the semiconductor device has lower on-resistance and effective saturation current.
4) The semiconductor device based on the three-dimensional grid field plate structure can form grooves with different structures according to devices with different indexes, the three-dimensional size of the groove can be designed differently according to the indexes of the devices, and correspondingly, the grid field plate can also be of an integral three-dimensional structure or a distributed three-dimensional structure.
Drawings
Fig. 1 is a schematic structural diagram of a lateral power device in the prior art;
FIG. 2 is a cross-sectional view of a semiconductor device based on a three-dimensional gate field plate structure according to an exemplary embodiment of the present invention;
fig. 3a is a schematic top view of a semiconductor device based on a three-dimensional gate field plate structure in embodiment 1 of the present invention;
fig. 3b is a schematic structural diagram of a semiconductor device based on a three-dimensional gate field plate structure in embodiment 1 of the present invention;
FIG. 3c is a schematic cross-sectional view at BB' of the semiconductor device based on the three-dimensional gate field plate structure in FIG. 3 b;
fig. 4a is a schematic top view of a semiconductor device based on a stereoscopic gate field plate structure in embodiment 2 of the present invention;
fig. 4b is a schematic structural diagram of a semiconductor device based on a three-dimensional gate field plate structure in embodiment 2 of the present invention;
FIG. 4c is a schematic cross-sectional view at BB' of the semiconductor device based on the three-dimensional gate field plate structure in FIG. 4 b;
fig. 5a is a schematic top view of a semiconductor device based on a solid gate field plate structure in embodiment 3 of the present invention;
fig. 5b is a schematic structural diagram of a semiconductor device based on a three-dimensional gate field plate structure in embodiment 3 of the present invention;
FIG. 5c is a schematic cross-sectional view at BB' of the semiconductor device based on the three-dimensional gate field plate structure in FIG. 5 b;
fig. 6 is a schematic flow chart illustrating a process of fabricating a solid gate field plate structure in a semiconductor device based on the solid gate field plate structure according to an exemplary embodiment of the present invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
The embodiment of the invention provides a semiconductor device based on a three-dimensional grid field plate structure on one hand, which comprises: the substrate is provided with a first conductive through hole and a second conductive through hole which are respectively matched with the source electrode and the drain electrode; the substrate and the body region are of a first conductivity type, and the source contact region, the drain contact region and the drift region are of a second conductivity type; the drift region is also provided with at least one groove, part of the gate field plate is also extended into the groove, and a first insulating layer is also arranged between the gate field plate and the groove.
According to the semiconductor device based on the three-dimensional gate field plate structure, the long-strip-shaped continuous groove or the grooves distributed at intervals are formed in the drift region, and the semiconductor devices with different device indexes can be obtained through the grooves with different numbers and different structures.
According to the semiconductor device based on the three-dimensional gate field plate structure, the three-dimensional gate field plate is formed by locally extending the gate field plate in the groove in the drift region, so that the RESURF effect of the semiconductor device is enhanced, the breakdown voltage and the quality factor of the on-resistance of the semiconductor device are improved, electric field lines are bent due to the existence of the groove, and the effective length of the drift region is further improved; in addition, the three-dimensional gate field plate of the semiconductor device based on the three-dimensional gate field plate structure provided by the embodiment of the invention also increases the width of an accumulation layer of the gate in the drift region, weakens the quasi-saturation effect of the semiconductor device under the condition of high gate voltage, reduces the on-resistance of the semiconductor device under the condition of strong conduction, and further improves the effective saturation current of the semiconductor device.
According to the semiconductor device based on the three-dimensional gate field plate structure, the drift region is processed to form the groove, and the groove is filled with the thick oxide layer (namely the first insulating layer), wherein the gate field plate crosses the groove, and the local extension of the gate field plate is arranged in the groove and is used as the field plate of the drift region below the groove; the three-dimensional gate field plate structure formed by arranging the local gate field plate in the groove in the semiconductor device based on the three-dimensional gate field plate structure can reduce the peak electric field of the drift region, enhance the RESURF effect, and fill the groove of the oxide layer to cause the bending of electric field lines, so that the length of the effective drift region is increased, the transverse size of the semiconductor device is shortened, and the semiconductor device can support higher breakdown voltage and lower on-resistance; according to the semiconductor device based on the three-dimensional gate field plate structure, the overlapping area of the gate and the drift region is increased, after the device enters a strong conduction state, the quasi-saturation effect can be improved, the semiconductor device has smaller conduction resistance, and larger saturation current is provided. For a system, the semiconductor device provided by the invention can realize higher efficiency by using smaller device size.
The technical solution, the implementation process and the principle thereof will be further explained with reference to the drawings.
Referring to fig. 2, a semiconductor device based on a three-dimensional gate field plate structure according to an exemplary embodiment of the present invention includes a substrate 10, a gate electrode 72, and a gate field plate 62, wherein the gate field plate 62 and the gate electrode 72 are disposed on the substrate 10, and the gate field plate 62 is interconnected with the gate electrode 72;
a body region 30, a drift region 20, a source contact region 42 and a drain contact region 41 are distributed in the substrate 10, a first conductive through hole 52 is further arranged on the body region 30, a second conductive through hole (which can be understood as a drain interconnection through hole, the same applies below) 51 is further arranged on the drain contact region 41, the first conductive through hole 52 and the second conductive through hole 51 are respectively matched with the source and the drain, the first conductive through hole 52 is mainly used for connecting the source and the body region 30, and the second conductive through hole 51 is mainly used for connecting the drain and the drain contact region 41; the substrate 10 and the body region 30 are both of a first conductivity type, and the source contact region 42, the drain contact region 41, and the drift region 20 are of a second conductivity type;
the drift region 20 further has at least one groove 21 therein, a part of the gate field plate 62 is further extended and disposed in the groove 21, and a first insulating layer 61 is further disposed between the gate field plate 62 and the groove 21.
Specifically, the second through hole 51 of the drift region 20 of the semiconductor device is connected with the heavily doped drain region 41, the heavily doped source region 42 is led out through the first conductive through hole 52, and the semiconductor device controls the opening and closing of a device channel through the gate 72 and the second insulating layer 71.
Specifically, the gate field plate 62 includes a first portion 621, a second portion 622, and a third portion 623, where the second portion 622 is disposed between the first portion 621 and the third portion 623, the first portion 621 and the third portion 623 are disposed outside the recess 21 and directly cover the surface of the drift region 20, the first portion 621 is directly electrically connected to the gate 72, and the second portion 622 is partially or entirely disposed in the recess 21; specifically, the second portion 622 is disposed in the groove in a filling manner to fill the groove 21, or the second portion 622 covers the inner wall (bottom and side wall) of the groove 21.
Specifically, the drift region 20 has a strip-shaped groove 21 continuously arranged along the length direction thereof, or the drift region 20 has a plurality of grooves 21 arranged at intervals along the length direction thereof, the surface of the drift region 20 and the inner walls of the grooves 21 are covered with a first insulating layer 61, the gate field plate 62 is arranged on the first insulating layer 61, the gate field plate 62 is an integral structure continuously distributed on the surface of the drift region, or the gate field plate 62 is a distributed structure at intervals distributed on the surface of the drift region.
Specifically, a second insulating layer (the second insulating layer can also be understood as a gate oxide layer) 71 is further disposed on the substrate 10, and the gate electrode 72 is disposed on the second insulating layer 71.
Specifically, the ratio of the depth of the groove 21 to the thickness of the drift region 20 is less than 1:1, for example, the ratio of the depth of the groove to the thickness of the drift region may be 1:3 or 1: 4.
Specifically, the material of the first insulating layer includes silicon dioxide, the material of the second insulating layer includes silicon dioxide, the thickness of the first insulating layer is more than 3 times that of the second insulating layer, and the thickness of the second insulating layer may be 20nm, for example.
Specifically, the body region 30 and the drift region 20 are formed by local processing of the substrate 10 by means of ion implantation and thermal diffusion, the source contact region 42 is formed by local processing of the body region 30 by means of ion implantation and thermal diffusion, and the drain contact region 41 is formed by local processing of the drift region 20 by means of ion implantation and thermal diffusion.
Referring to fig. 6, a process for manufacturing a stereoscopic gate field plate in a semiconductor device based on a stereoscopic gate field plate structure may include the following steps:
1) providing a substrate 10, locally processing the substrate 10 by means of ion implantation and thermal diffusion (the parameters of ion implantation and thermal diffusion depend on the voltage and current of the device, and are selected by those skilled in the art according to specific situations, and are not particularly limited herein) to form a drift region 20, and processing one or more grooves 21 from the surface of the drift region in a vertical direction (which can be understood as the thickness direction of the drift region) by using an etching process, wherein the grooves 21 are sequentially distributed at intervals along the length direction of the drift region, and the ratio of the depth of the grooves 21 to the depth of the drift region 20 is less than 1;
2) forming an oxide layer on the surface of the substrate 10 including the surface of the drift region and the inner wall of the groove 21 by adopting a thermal oxidation process to serve as a first insulating layer 61, wherein the first insulating layer is made of silicon dioxide, and the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is greater than 1;
3) the morphology of the first insulating layer and the second insulating layer is etched, and the first insulating layer 61 is manufactured so that the morphology of the first insulating layer 61 matches the number and structure of the grooves 21, wherein a thin oxide layer 81 remains on the surface of the substrate,
4) a gate oxide layer, i.e., a second insulating layer 71, is formed on the thin oxide layer 81 by using a thermal oxidation process, the material of the second insulating layer 71 is silicon dioxide, and the thickness of the second insulating layer depends on the operating voltage of the gate, which can be set by a person skilled in the art according to specific situations, for example, the thickness of the second insulating layer can be 20 nm;
5) removing the second insulating layer in the non-gate region, depositing polysilicon on the second insulating layer to form a gate 72, forming a gate field plate 62 on the first insulating layer 61, and etching the polysilicon gate and the gate field plate, wherein part of the gate field plate 62 is continuously arranged on the inner wall of the groove 21, or the gate field plate 62 fills the whole groove 21; when the step 5) is executed, if the filling thickness of the gate field plate is thicker or the depth of the groove is shallower, the gate field plate is caused to fill the groove, which is also one of the embodiments of the three-dimensional gate field plate structure of the present invention.
Of course, the manufacturing of the semiconductor device based on the three-dimensional gate field plate structure further includes the steps of forming a body region, a source contact region, a drain contact region, a first conductive through hole and a second conductive through hole, which are not described herein again.
It should be noted that the ion implantation, the thermal diffusion, the etching process, the thermal oxidation process, and the like used in the embodiments of the present invention are all known to those skilled in the art, and in the specific implementation process, those skilled in the art may use different process parameters according to specific situations, and in the present invention, specific process parameters are not specifically limited.
The semiconductor device based on the three-dimensional grid field plate structure provided by the invention is mainly applied to the semiconductor device in the field of power devices, and comprises a groove in a drift region and a corresponding three-dimensional grid field plate, wherein the groove is positioned in the drift region and comprises an integral structure and a distributed structure; on the other hand, the three-dimensional grid field plate structure utilizes the longitudinal size of the device to reduce the transverse size of the device; more importantly, under the condition that the device is conducted, the gate field plate enhances the accumulation effect of the drift region, improves the quasi-saturation effect of the device, reduces the resistance of the device under conduction and improves the saturation current.
In the semiconductor device based on the three-dimensional gate field plate structure provided in the exemplary embodiment of the present invention, the groove is formed in the drift region, and the gate field plate and the first insulating layer are disposed in the groove, so that on the basis, on one hand, the RESURF effect of the drift region can be enhanced, the quality factors of breakdown voltage and on-resistance can be improved, on the other hand, the overlapping portion of the gate and the drift region can be increased, the quasi-saturation effect of the device can be improved, the resistance in a strong on-state can be reduced, and the saturation current of the device can be improved.
Example 1
Referring to fig. 3a, 3b and 3c, a semiconductor device based on a three-dimensional gate field plate structure according to an exemplary embodiment of the present invention includes a substrate 10, a gate electrode 72, and a gate field plate 62, wherein the gate field plate 62 and the gate electrode 72 are disposed on the substrate 10, and the gate field plate 62 is electrically connected or contacted with the gate electrode 72,
a body region 30 and a drift region 20 are distributed in the substrate 10, a source contact region 42 and a drain contact region 41 are respectively formed in the body region 30 and the drift region 20, a first conductive through hole 52 is further arranged on the body region 30, a second conductive through hole 51 is further arranged on the drain contact region 41, the first conductive through hole 52 and the second conductive through hole 51 are respectively matched with the source electrode and the drain electrode, specifically, the first conductive through hole 52 is mainly used for connecting the source electrode and the body region 30, and the second conductive through hole 51 is mainly used for connecting the drain electrode and the drain contact region 41;
the drift region 20 is also internally provided with a groove 21 which is continuously distributed along the length direction of the drift region, and the gate field plate 62 is covered on the surface of the drift region 20 and the inner wall of the groove 21, so that a three-dimensional gate field plate is formed;
the substrate 10 and the body region 30 are of a first conductivity type, and the drift region 20 is of a second conductivity type.
Specifically, the cutting is performed along AA 'of fig. 3a or 3b, i.e. the cross-sectional structure shown in fig. 2 is obtained, and the cutting is performed along BB' of fig. 3b, i.e. the cross-sectional structure is formed as shown in the cross-sectional structure diagram shown in fig. 3 c.
Specifically, in the semiconductor device based on the three-dimensional gate field plate structure in this embodiment, the grooves 21 are continuously distributed and integrated structures, the gate field plates 62 are also continuously distributed and integrated structures, the gate field plate 62 is continuously covered on the surface of the drift region 20 from the side close to the gate 72, then continuously covered on the inner wall of the groove 21 after the surface of the drift region 20, and then passes through the grooves 21 and extends to the surface of the drift region where the grooves are far from the gate, and the number of the grooves and the number of the gate field plates in this embodiment are both one.
Example 2
Referring to fig. 4a, 4b and 4c, the structure of the semiconductor device based on the stereoscopic gate field plate structure provided in this embodiment is substantially the same as that of the semiconductor device in embodiment 1, except that: in the drift region in this embodiment, a plurality of grooves 21 are formed at intervals along the length direction of the drift region, a plurality of gate field plates 62 are disposed on the surface of the drift region 20, the plurality of gate field plates 62 are all connected to the gate 72, and each gate field plate 62 corresponds to or matches one groove 21.
Specifically, the cutting is performed along AA 'of fig. 4a or 4b, i.e. the cross-sectional structure shown in fig. 2 is obtained, and the cutting is performed along BB' of fig. 4b, i.e. the cross-sectional structure is formed as shown in the cross-sectional structure diagram shown in fig. 4 c.
Specifically, the plurality of grooves 21 and the plurality of gate field plates 62 in the semiconductor device based on the three-dimensional gate field plate structure provided by this embodiment are distributed structures, the plurality of grooves 21 are not communicated with each other, the structure, number and other parameters of the grooves are designed according to the specification of the device, a first insulating layer is arranged on the grooves 21, the plurality of distributed gate field plates 62 are arranged above the first insulating layer, each gate field plate is connected to the gate, but the plurality of gate field plates are not directly connected.
Example 3
Referring to fig. 5a, 5b and 5c, the structure of the semiconductor device based on the stereoscopic gate field plate structure provided in this embodiment is substantially the same as that of the semiconductor device in embodiment 2, except that: the drift region in this embodiment has a plurality of grooves 21 spaced along the length of the drift region, but the surface of the drift region 20 is provided with an integral gate field plate 62, and the gate field plate 62 corresponds to or matches the plurality of grooves 21.
Specifically, the cutting is performed along AA 'of fig. 5a or 5b, i.e. the cross-sectional structure shown in fig. 2 is obtained, and the cutting is performed along BB' of fig. 5b, i.e. the cross-sectional structure is formed as shown in the cross-sectional structure diagram shown in fig. 5 c.
It can be seen from fig. 5b that the plurality of grooves in the embodiment of the present invention are distributed structures, the gate field plate is a monolithic structure, and above the groove 21 is a first insulating layer on which the gate field plate is located.
In the existing lateral power semiconductor device, a source field plate or a gate field plate is generally adopted to reduce the surface electric field distribution of a drift region of the device, so that the breakdown voltage of the device is improved, the on-resistance is reduced, the gate field plate is interconnected with a gate, the thickness of a gate field plate oxide layer (namely a first insulating layer) which is generally positioned above the drift region and between the drift region is larger than that of a gate oxide layer (namely a second insulating layer), and the main function of the gate field plate is to reduce the surface electric field of the drift region; the conventional power semiconductor device also generally uses a shallow oxide trench in the drift region to bend the current path toward the inside of the drift region, thereby increasing the effective drift region length and reducing the lateral size of the device.
According to the semiconductor device based on the three-dimensional gate field plate structure, the drift region is processed to form the groove, and the groove is filled with the thick oxide layer (namely the first insulating layer), wherein the gate field plate crosses the groove, and the local extension of the gate field plate is arranged in the groove and is used as the field plate of the drift region below the groove; the semiconductor device based on the three-dimensional gate field plate structure provided by the embodiment of the invention has the advantages that the three-dimensional gate field plate structure formed by arranging the local gate field plate in the groove can reduce the peak electric field of the drift region, enhance the RESURF effect, and fill the groove of the oxide layer to cause the bending of electric field lines, thereby improving the length of the effective drift region, shortening the transverse size of the semiconductor device, further enabling the semiconductor device to support higher breakdown voltage,
according to the semiconductor device based on the three-dimensional gate field plate structure, the drift region is processed to form the strip-shaped groove or the plurality of grooves distributed at intervals, the gate field plate with the three-dimensional structure is formed on the surface of the drift region, the part of the gate field plate, which is positioned in the groove region, is bent downwards and extends into the groove, and the thickness of the oxide layer of the gate field plate is larger than that of the gate oxide layer.
The semiconductor device based on the three-dimensional gate field plate structure provided by the invention has the advantages that the effects of the gate field plate and the drift region shallow groove are considered, the surface electric field of the drift region is reduced by the gate field plate, the voltage of the device is improved, the on-resistance is reduced, the effective length of the drift region is increased by the groove structure, and the transverse size of the device is shortened.
And the gate field plate acts on the groove, so that the area of the device accumulation layer is increased, the quasi-saturation effect of the device can be improved under the condition of high gate voltage, and the semiconductor device has lower on-resistance and effective saturation current.
In addition, the semiconductor device based on the three-dimensional grid field plate structure provided by the invention can form grooves with different structures according to devices with different indexes, the three-dimensional size of the groove can be designed differently according to the indexes of the devices, and correspondingly, the grid field plate can also be of an integral three-dimensional structure or a distributed three-dimensional structure.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A semiconductor device based on a stereoscopic gate field plate structure, comprising: the substrate is provided with a first conductive through hole and a second conductive through hole which are respectively matched with the source electrode and the drain electrode; the substrate and the body region are of a first conductivity type, and the source contact region, the drain contact region and the drift region are of a second conductivity type; the method is characterized in that: the drift region is also provided with at least one groove, part of the gate field plate is also extended into the groove, and a first insulating layer is also arranged between the gate field plate and the groove.
2. The semiconductor device based on the stereoscopic gate field plate structure as claimed in claim 1, wherein: the gate field plate is continuously covered on the surface of the drift region and the inner wall of the groove.
3. The semiconductor device based on the stereoscopic gate field plate structure as claimed in claim 1 or 2, wherein: the first insulating layer is continuously covered on the surface of the drift region and the inner wall of the groove, and the gate field plate is arranged on the first insulating layer.
4. The semiconductor device based on the stereoscopic gate field plate structure as claimed in claim 3, wherein: the ratio of the depth of the groove to the thickness of the drift region is less than 1: 1.
5. The semiconductor device based on the stereoscopic gate field plate structure as claimed in claim 1, wherein: the drift region is internally provided with a continuous groove, the drift region is internally provided with a continuous grid field plate, or the drift region is internally provided with a plurality of grooves at intervals, the drift region is internally provided with a continuous grid field plate, the grid field plate is matched with the grooves, or the drift region is internally provided with a plurality of grooves at intervals, the drift region is internally provided with a plurality of grid field plates at intervals, each grid field plate is matched with one groove, and the grid field plates are all interconnected with the grid electrode.
6. The semiconductor device based on the stereoscopic gate field plate structure as claimed in claim 1, wherein: a second insulating layer is arranged between the grid and the base material; preferably, the material of the second insulating layer includes silicon dioxide; and/or the material of the first insulating layer comprises silicon dioxide, preferably, the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is more than 1: 1; and/or the material of the substrate comprises silicon.
7. The semiconductor device based on the stereoscopic gate field plate structure as claimed in claim 1, wherein: the body region and the drift region are formed by local processing of the substrate in a mode of ion implantation and heating diffusion; preferably, the source contact region is formed by local processing of the body region by means of ion implantation and thermal diffusion, and the drain contact region is formed by local processing of the drift region by means of ion implantation and thermal diffusion.
8. The method for fabricating a semiconductor device based on a stereoscopic gate field plate structure as claimed in any of claims 1 to 7, comprising:
providing a substrate, wherein a body region, a drift region, a source contact region and a drain contact region are distributed in the substrate;
forming a gate electrode on the substrate;
processing and forming at least one groove in the drift region;
forming a first insulating layer on the surface of the drift region and the inner wall of the groove, forming a gate field plate interconnected with a gate on the first insulating layer, and enabling the local extension of the gate field plate to be arranged in the groove; and
and respectively manufacturing a first conductive through hole and a second conductive through hole which are matched with the source electrode contact region and the drain electrode contact region.
9. The method for manufacturing a semiconductor device based on a three-dimensional grid field plate structure according to claim 8, which specifically comprises: processing and forming a groove which is continuously distributed in the drift region, and forming a grid field plate which is continuously distributed on the drift region, wherein the grid field plate is matched with the groove; or processing a plurality of grooves distributed at intervals in the drift region, forming a grid field plate distributed continuously on the drift region, wherein the grid field plate is matched with the grooves, or processing a plurality of grooves distributed at intervals in the drift region, manufacturing a plurality of grid field plates distributed at intervals on the surface of the drift region, and each grid field plate is matched with one groove; preferably, the gate electrode is disposed on a second insulating layer disposed on the substrate.
10. The method for manufacturing a semiconductor device based on the three-dimensional grid field plate structure according to claim 8, wherein the method comprises the following steps: the body region and the drift region are formed by local processing of the substrate in a mode of ion implantation and heating diffusion; preferably, the source contact region is formed by local processing of the body region by means of ion implantation and thermal diffusion, and the drain contact region is formed by local processing of the drift region by means of ion implantation and thermal diffusion.
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| CN115064582A (en) * | 2022-08-08 | 2022-09-16 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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