CN113852373B

CN113852373B - Successive approximation type analog-to-digital converter with pipeline domino structure

Info

Publication number: CN113852373B
Application number: CN202110939574.5A
Authority: CN
Inventors: 李娅妮; 苏成龙; 刘马良; 张诗鑫; 朱樟明; 杨银堂
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-08-16
Filing date: 2021-08-16
Publication date: 2024-07-12
Anticipated expiration: 2041-08-16
Also published as: CN113852373A

Abstract

The invention provides a successive approximation type analog-to-digital converter with a pipeline domino structure, which comprises the following components: the device comprises an n+1 level sub ADC, a plurality of residual error amplifiers and a preset adjusting module; the input end of the 1 st stage sub ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of each sub ADC comprises a first output end, and the first output end is connected with a preset adjusting module and is used for inputting 5-bit quantized codes generated by each sub ADC to the preset adjusting module so that the preset adjusting module can splice the quantized codes and correct redundant bits to obtain an analog-to-digital conversion result; the 1 st to n th stage sub-ADCs also comprise a second output end, and the second output end is used for taking the signals amplified by the residual amplifier generated by the sub-ADCs as input signals and inputting the signals to the next stage sub-ADCs. The invention improves the conversion speed and the conversion precision of the SAR ADC, can correct the offset voltage in real time in the working process of the comparator, and prevents the performance of the sub ADC from being influenced by offset accumulation.

Description

Successive approximation type analog-to-digital converter with pipeline domino structure

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a successive approximation type analog-to-digital converter with a pipeline domino structure.

Background

With the rapid development of integrated circuits, the performance requirements of ADCs (Analog to Digital Converter, analog-to-digital converters) in the field of portable electronic applications such as wireless communication, image and video are continuously increasing, and the design of high resolution, high conversion rate, low distortion and low power consumption has become a major challenge for the design of analog-to-digital converters.

At present, the analog-to-digital converter mostly adopts a pipeline structure, and the conversion speed, the precision and the power consumption of the analog-to-digital converter are balanced in a conversion mode of cascading a plurality of sub-ADCs and working in a pipeline mode. SAR ADC (Successive Approximation Register, successive approximation analog-to-digital converter) is a commonly used analog-to-digital converter, and in order to implement a high-speed SAR ADC, a time-domain interleaving and pipeline structure is generally adopted in the related art. However, the mismatch between the multiple channels of the time-domain interleaved SAR ADC may seriously affect the performance of the ADC, and the pipelined SAR ADC replaces the full parallel ADC in the pipeline with the SAR ADC, which is limited by the speed of the traditional asynchronous logic SAR ADC.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a successive approximation type analog-to-digital converter with a pipeline domino structure. The technical problems to be solved by the invention are realized by the following technical scheme:

The invention provides a successive approximation type analog-to-digital converter with a pipeline domino structure, which comprises the following components: the device comprises an n+1 level sub ADC, a plurality of residual error amplifiers and a preset adjusting module; wherein,

The sub-ADC comprises an input end and an output end, wherein the input end of the 1 st stage sub-ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of each sub ADC comprises a first output end, and the first output end is connected with the preset adjusting module and is used for inputting the 5-bit quantization code generated by each sub ADC to the preset adjusting module so that the preset adjusting module can splice and correct the 5-bit quantization code generated by each sub ADC to obtain an analog-to-digital conversion result;

the 1 st to n th stage sub-ADCs further comprise a second output end, wherein the second output end is connected to the next stage sub-ADC through the residual error amplifier and is used for taking a signal obtained by amplifying a residual error signal generated by the sub-ADC through the residual error amplifier as an input signal and inputting the signal to the next stage sub-ADC.

In one embodiment of the present invention, the circuit further comprises a first reference voltage signal terminal, a second reference voltage signal terminal and a third reference voltage signal terminal, wherein the signal input terminal comprises a first signal input terminal and a second signal input terminal;

The sub-ADC includes: a first module, a second module, a calibration circuit, and an output module, the first module comprising a comparator: A1-A5, a first type capacitor, a second type capacitor, a first type switch, a second type switch and preset logic circuits corresponding to A1-A5 respectively, wherein the first type switch comprises a plurality of first switch groups, the second type switch comprises a plurality of second switch groups, each first switch group comprises three first switches, and each second switch group comprises three second switches; wherein,

The first input end of each comparator is connected with the first signal input end, the second input end is connected with the second signal input end, and the output end is connected with a preset logic circuit corresponding to the comparator; the first ends of the first type capacitors are connected with the first signal input end, and the second ends of the first type capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three first switches in the first switch group respectively;

the first ends of the second type capacitors are connected with the second signal input end, and the second ends of the second type capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three second switches in the second switch group respectively.

In one embodiment of the present invention, in the 1 st to n-th sub-ADCs, the first type of capacitor includes: cs1 to Cs5, and the second type capacitor includes: the ratio of capacitance values of Cs 6-Cs 10, cs1, cs2, cs3, cs4 and Cs5 is 16:8:4:2:1, and the ratio of capacitance values of Cs6, cs7, cs8, cs9 and Cs10 is 16:8:4:2:1.

In one embodiment of the present invention, the stage 1 sub-ADC further includes a second module including a third type of capacitor, a fourth type of capacitor, a third type of switch, and a fourth type of switch, the third type of switch including a plurality of third switch groups, the fourth type of switch including a plurality of fourth switch groups, each of the third switch groups including three third switches, each of the fourth switch groups including three fourth switches; wherein,

The first ends of the third type capacitors are connected with the first signal input end, and the second ends of the third type capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three third switches in the third switch group respectively;

The first ends of the fourth type capacitors are connected with the second signal input end, and the second ends of the fourth type capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three fourth switches in the fourth switch group respectively.

In one embodiment of the present invention, in the stage 1 sub-ADC, the third type of capacitance includes: cs11 to Cs15, and the second type capacitor includes: the ratio of capacitance values of Cs 16-Cs 20, cs11, cs12, cs13, cs14 and Cs15 is 16:8:4:2:1, and the ratio of capacitance values of Cs16, cs17, cs18, cs19 and Cs20 is 16:8:4:2:1.

In one embodiment of the present invention, the sub-ADC further comprises a calibration circuit for calibrating the offset voltages of A1 to A5, and an output module for storing the 5-bit quantization code generated by the sub-ADC.

In one embodiment of the invention, the power supply signal terminal is further included; the comparator includes a first sub-module and a second sub-module, the first sub-module including a first transistor: m1 to M7 and an inverter: b1, B2, the second submodule comprising a second transistor: m8 to M14 and an inverter: b1 to B4; wherein,

The source electrode of M1 is connected with the power supply signal end, the drain electrode is connected with the source electrode of M2, the grid electrode is connected with the grid electrode of M4, the grid electrode of M2 is connected with the second signal input end, the drain electrode is connected with the drain electrode of M4, the source electrode of M4 is grounded, a first node is arranged between the drain electrode of M1 and the source electrode of M2, the grid electrode of M3 is connected with the second reference voltage signal end, the source electrode is connected with the first node, the drain electrode is connected with the second node, a third node is arranged between the drain electrode of M4 and the drain electrode of M2, the source electrode of M4 is grounded, the grid electrode of M5 is connected with the clock signal, the drain electrode is connected with the second node and the source electrode is grounded, the grid electrode of M6 is connected with the first reset signal, the drain electrode is connected with the second node and the source electrode is grounded, and the grid electrode of M7 is connected with the second reset signal, the drain electrode is connected with the second node and the source electrode is grounded; the input end of the B1 is connected with the drain electrode of the M4, and the output end of the B1 is connected with the input end of the B2;

The source electrode of M8 is connected with the power supply signal end, the drain electrode is connected with the source electrode of M9, the grid electrode is connected with the grid electrode of M11, the grid electrode of M9 is connected with the second signal input end, the drain electrode is connected with the drain electrode of M11, the source electrode of M11 is grounded, a fourth node is arranged between the drain electrode of M8 and the source electrode of M9, the grid electrode of M10 is connected with the second reference voltage signal end, the source electrode is connected with the fourth node, the drain electrode is connected with the fifth node, a sixth node is arranged between the drain electrode of M11 and the drain electrode of M9, the source electrode of M11 is grounded, the grid electrode of M12 is connected with the clock signal, the drain electrode is connected with the fifth node and the source electrode is grounded, the grid electrode of M13 is connected with the first reset signal, the drain electrode is connected with the fifth node and the source electrode is grounded, and the grid electrode of M14 is connected with the second reset signal, the drain electrode is connected with the fifth node and the source electrode is grounded; the input end of B3 is connected with the drain electrode of M11, and the output end of B3 is connected with the input end of B4;

the third node is connected with the grid electrode of M8, and the sixth node is connected with the grid electrode of M1.

In one embodiment of the invention, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super effect transistors.

In one embodiment of the invention, the calibration circuit includes a third transistor: M15-M25, preset current sources, AND gates: c1 and C2, and inverter B5; wherein,

The grid electrode of M15 is connected with the grid electrode of M16, the source electrode of M15 and the source electrode of M16 are both connected with the power supply signal end, the drain electrode of M15 is connected with the source electrode of M17, the grid electrode of M17 is grounded, the drain electrode of M19 is connected with the drain electrode of M21, the source electrode of M21 is grounded, the drain electrode of M16 is connected with the source electrode of M18, the grid electrode of M18 is connected with a first switch signal, the drain electrode of M18 is connected with the drain electrode of M20, a seventh node is arranged between the drain electrode of M18 and the drain electrode of M20, the seventh node is connected with the first reference voltage, the grid electrode of M20 is connected with a second switch signal, the source electrode is connected with the drain electrode of M22, the source electrode of M22 is grounded, the drain electrode of M22 is connected with the preset current source, an eighth node is arranged between the preset current source and the grid electrode of M22, the grid electrode of M23 and the drain electrode of M21 are both connected with the eighth node, and the source electrode of M23 is grounded;

The first input end and the second input end of the comparator are connected through a first switch, the third input end is connected with the first reference voltage, the first output end is connected with the first input end of C1, the second output end is connected with the first input end of C2, the second input end of C1 and the second input end of C2 are both connected to an enabling signal, the grid electrode of M24 is connected with the power signal end, the source electrode of M24 and the source electrode of M25 are connected to a ninth node, the ninth node is connected with the second switch signal, the drain electrode of M24 and the drain electrode of M25 are connected to a tenth node, the tenth node is connected with the output end of C1, the grid electrode of M25 is grounded, and the output end of C2 is connected with the input end of the inverter B5.

Compared with the related art, the invention has the beneficial effects that:

The invention provides a successive approximation type analog-to-digital converter with a pipeline domino structure, which comprises the following components: the device comprises an n+1 level sub ADC, a plurality of residual error amplifiers and a preset adjusting module; the sub-ADC comprises an input end and an output end, wherein the input end of the 1 st stage sub-ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of each sub ADC comprises a first output end, and the first output end is connected with a preset adjusting module and is used for inputting 5-bit quantized codes generated by the sub ADC into the preset adjusting module so that the adjusting module can splice and correct redundant bits of 5-bit quantized codes generated by each sub ADC to obtain an analog-to-digital conversion result; the 1 st to n th level sub-ADCs also comprise a second output end, wherein the second output end is connected to the next level sub-ADC through a residual error amplifier and is used for taking the signal amplified by the residual error amplifier of the residual error signal generated by the sub-ADC as an input signal and inputting the signal into the next level sub-ADC. The invention adopts a multistage sub-ADC structure, improves the conversion speed and the conversion precision of the SAR ADC, and can correct the offset voltage in real time in the working process of the comparator due to the fact that each sub-ADC comprises a calibration circuit, thereby preventing the performance of the sub-ADC from being reduced due to offset accumulation of the comparator.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic structural diagram of a pipeline domino structure successive approximation analog-to-digital converter according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a level 1 sub-ADC according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a2 nd to n th stage sub-ADC according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an n+1st stage sub ADC according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a comparator according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a latch in a comparator according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a calibration circuit according to an embodiment of the present invention;

FIG. 8 is a timing diagram of operation of a level 1 sub-ADC according to an embodiment of the present invention;

FIG. 9 is a timing diagram of operation of a level 2 sub-ADC according to an embodiment of the present invention;

fig. 10 is a timing diagram of operation of the 3 rd stage sub-ADC according to an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Fig. 1 is a schematic structural diagram of a pipeline domino structure successive approximation analog-to-digital converter according to an embodiment of the present invention. Referring to fig. 1, the present invention provides a successive approximation type analog-to-digital converter 100 with a pipelined domino structure, comprising: an n+1 stage sub ADC10, a plurality of differential amplifiers 20, and a preset adjustment module 30; wherein,

The sub-ADC 10 includes an input end and an output end, and the input end of the 1 st stage sub-ADC 10 is connected to the signal input end, for obtaining an input signal after sampling; the output end of each sub-ADC 10 comprises a first output end, and the first output end is connected with the preset adjustment module 30 and is used for inputting the 5-bit quantization code generated by each sub-ADC 10 to the preset adjustment module 30, so that the preset adjustment module 30 performs splicing and redundant bit correction on the 5-bit quantization code generated by each sub-ADC 10 to obtain an analog-to-digital conversion result;

the 1 st to n-th sub-ADC 10 further includes a second output terminal connected to the next sub-ADC 10 through the residual amplifier 20, and configured to input the signal obtained by amplifying the residual signal generated by the sub-ADC 10 through the residual amplifier 20 as an input signal to the next sub-ADC 10.

Fig. 2 is a schematic structural diagram of a 1 st stage sub ADC according to an embodiment of the present invention, fig. 3 is a schematic structural diagram of a 2 nd to n th stage sub ADC according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of an n+1 th stage sub ADC according to an embodiment of the present invention. Referring to fig. 2 to 4, optionally, the pipeline domino structure successive approximation type analog-to-digital converter 100 further includes a first reference voltage signal terminal VREF, a second reference voltage signal terminal VCM, and a third reference voltage signal terminal GND, where the signal input terminals include a first signal input terminal V _IN and a second signal input terminal V _IP;

The sub ADC10 includes: a first module 101, a second module 102, a calibration circuit 103 and an output module 104, the first module 101 comprising a comparator: A1-A5, a first type capacitor, a second type capacitor, a first type switch, a second type switch and a preset logic circuit corresponding to A1-A5 respectively, wherein the first type switch comprises a plurality of first switch groups SW1, the second type switch comprises a plurality of second switch groups SW2, each first switch group SW1 comprises three first switches, and each second switch group SW2 comprises three second switches; wherein,

The first input end of each comparator is connected with a first signal input end V _IN, the second input end is connected with a second signal input end V _IP, and the output end is connected with a preset logic circuit corresponding to the comparator; the first ends of the first type capacitors are connected with the first signal input end V _IN, and the second ends of the first type capacitors are connected to the first reference voltage signal end VREF, the second reference voltage signal end VCM or the third reference voltage signal end GND through three first switches in the first switch group SW1 respectively;

The first ends of the second type capacitors are connected with the second signal input end V _IP, and the second ends are respectively connected to the first reference voltage signal end VREF, the second reference voltage signal end VCM or the third reference voltage signal end GND through three second switches in the second switch group SW 2.

Note that, in this embodiment, each sub-ADC 10 in the 2 nd to n th sub-ADC 10 has the same structure, and the 1 st sub-ADC 10 has a structure different from that of the 2 nd to n th sub-ADC 10, specifically, the 1 st sub-ADC 10 includes the second module 102 in addition to the first module 101.

Optionally, as shown in fig. 2, the level 1 sub-ADC 10 further includes a second module 102, where the second module 102 includes a third type capacitor, a fourth type capacitor, a third type switch, and a fourth type switch, the third type switch includes a plurality of third switch groups SW3, the fourth type switch includes a plurality of fourth switch groups SW4, each third switch group SW3 includes three third switches, and each fourth switch group SW4 includes three fourth switches; wherein,

The first ends of the third type capacitors are connected with the first signal input end V _IN, and the second ends of the third type capacitors are connected to the first reference voltage signal end VREF, the second reference voltage signal end VCM or the third reference voltage signal end GND through three third switches in the third switch group SW3 respectively;

The first ends of the fourth type capacitors are connected to the second signal input terminal V _IP, and the second ends are connected to the first reference voltage signal terminal VREF, the second reference voltage signal terminal VCM, or the third reference voltage signal terminal GND through three fourth switches in the fourth switch set SW4, respectively.

Optionally, as shown in fig. 2-4, the sub-ADC 10 further includes a calibration circuit 103 and an output module 104, wherein the calibration circuit 103 is used for calibrating the offset voltages of A1-A5, and the output module 104 is used for storing the 5-bit quantization code generated by the sub-ADC 10.

Fig. 5 is a schematic diagram of a comparator according to an embodiment of the present invention. As shown in fig. 5, the pipelined domino structure successive approximation type analog-to-digital converter 100 further includes a power supply signal terminal VDD; the comparator comprises a first sub-module 201 and a second sub-module 202, the first sub-module 201 comprising a first transistor: m1 to M7 and an inverter: b1, B2, the second sub-module 202 comprises a second transistor: m8 to M14 and an inverter: b1 to B4; wherein,

The source electrode of M1 is connected with a power signal end VDD, the drain electrode is connected with the source electrode of M2, the grid electrode is connected with the grid electrode of M4, the grid electrode of M2 is connected with a second signal input end V _IP, the drain electrode is connected with the drain electrode of M4, the source electrode of M4 is grounded, a first node N1 is arranged between the drain electrode of M1 and the source electrode of M2, the grid electrode of M3 is connected with a second reference voltage signal end VCM, the source electrode is connected with the first node N1, the drain electrode is connected with a second node N2, a third node N3 is arranged between the drain electrode of M4 and the drain electrode of M2, the grid electrode of M5 is connected with a clock signal, the drain electrode is connected with the second node N2, the source electrode is grounded, the grid electrode of M6 is connected with a first reset signal, the drain electrode is connected with the second node N2, the source electrode is grounded, and the grid electrode of M7 is connected with a second reset signal, the drain electrode is connected with the second node N2, and the source electrode is grounded; the input end of the B1 is connected with the drain electrode of the M4, and the output end of the B1 is connected with the input end of the B2;

The source electrode of M8 is connected with a power supply signal end VDD, the drain electrode is connected with the source electrode of M9, the grid electrode is connected with the grid electrode of M11, the grid electrode of M9 is connected with a second signal input end V _IP, the drain electrode is connected with the drain electrode of M11, the source electrode of M11 is grounded, a fourth node is arranged between the drain electrode of M8 and the source electrode of M9, the grid electrode of M10 is connected with a second reference voltage signal end VCM, the source electrode is connected with a fourth node N4, the drain electrode is connected with a fifth node N5, a sixth node N6 is arranged between the drain electrode of M11 and the drain electrode of M9, the grid electrode of M12 is connected with a clock signal, the drain electrode is connected with the fifth node N5, the source electrode is grounded, the grid electrode of M13 is connected with a first reset signal, the drain electrode is connected with the fifth node N5, the source electrode is grounded, the grid electrode of M14 is connected with a second reset signal, the drain electrode is connected with the fifth node N5, and the source electrode is grounded; the input end of B3 is connected with the drain electrode of M11, and the output end of B3 is connected with the input end of B4;

wherein the third node N3 is connected to the gate of M8 and the sixth node N6 is connected to the gate of M1.

Optionally, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super effect transistors.

In addition, in the present embodiment, the comparators A1 to A5 further include latches as shown in fig. 6 for storing quantization codes generated after quantization is completed.

Fig. 7 is a schematic diagram of a calibration circuit according to an embodiment of the present invention. As shown in fig. 7, in the pipelined domino structure successive approximation type analog-to-digital converter 100, the calibration circuit 103 includes a third transistor: m15 to M25, preset current source IC, and gate: c1 and C2, and inverter B5; wherein,

The grid of M15 is connected with the grid of M16, the source of M15 and the source of M16 are both connected with a power signal end VDD, the drain of M15 is connected with the source of M17, the grid of M17 is grounded, the drain of M19 is connected with the drain of M19, the source of M19 is connected with the drain of M21, the source of M21 is grounded, the drain of M16 is connected with the source of M18, the grid of M18 is connected with a first switch signal SPS, the drain of M18 is connected with the drain of M20, a seventh node N7 is included between the drain of M18 and the drain of M20, the seventh node N7 is connected with a first reference voltage Vc, the grid of M20 is connected with a second switch signal SNS, the source is connected with the drain of M22, the source of M22 is grounded, the grid of M22 is connected with a preset current source IC, the grid of M23 and the grid of M21 are both connected with the eighth node N8, and the source of M23 is grounded;

The first input end and the second input end of the comparator are connected through a first switch, the third input end is connected with a first reference voltage Vc, the first output end is connected with the first input end of C1, the second output end is connected with the first input end of C2, the second input end of C1 and the second input end of C2 are both connected to an enable signal EN, the grid electrode of M24 is connected with a power signal end VDD, the source electrode of M24 and the source electrode of M25 are connected to a ninth node N9, the ninth node N9 is connected with a second switch signal SNS, the drain electrode of M24 and the drain electrode of M25 are connected to a tenth node N10, the tenth node N10 is connected with the output end of C1, the grid electrode of M25 is grounded, and the output end of C2 is connected with the input end of an inverter B5.

Optionally, in the 1 st to n th stage sub-ADC, the first capacitor includes: cs 1-Cs 5, the second type of capacitance includes: the ratio of capacitance values of Cs 6-Cs 10, cs1, cs2, cs3, cs4 and Cs5 is 16:8:4:2:1, and the ratio of capacitance values of Cs6, cs7, cs8, cs9 and Cs10 is 16:8:4:2:1.

Illustratively, the pipelined domino architecture successive approximation type analog-to-digital converter in this embodiment may include a 3-stage 5-bit sub-ADC. With continued reference to fig. 2, CLKS1 is the first stage sampling clock signal for a1 st stage 5bit sub-ADC, and the sampling frequency may be 1GHz, i.e., the period is 1ns, where 250ps is used for sampling and 750ps is used for conversion, residual amplification, and offset calibration during the period of 1 ns. Optionally, the first reference voltage signal terminal vref=0.9 mV, the second reference voltage signal terminal vcm=450 mV, and the vpp=1.8v input signal may be quantized. The first module 101 and the second module 102 sample the first signal input terminal V _IN and the second signal input terminal V _IP at the same time, and the comparator compares the voltages of the first type capacitor and the second type capacitor in the first module 101 and feeds back the comparison result to the preset logic circuits of the first module 101 and the second module 102.

It should be noted that, in the first type of capacitor, the second type of capacitor, the third type of capacitor and the fourth type of capacitor, each capacitor is weighted by 16:8:4:2:1, and the unit capacitance of the third type capacitance and the fourth type capacitance in the second module 102 is larger than the unit capacitance of the first type capacitance and the second type capacitance in the first module 101, the design mode can enable the small capacitance in the first module 101 to realize a faster quantization code conversion process, and the large capacitance in the second module 102 can ensure the accuracy of the residual error level output after quantization is completed, and meanwhile, the requirements of KT/C noise are met. In the conversion period, the residual error amplifier 20 works in a stable state that the inputs are common mode signals, and after the conversion is completed, the capacitor array (namely the third type of capacitor and the fourth type of capacitor) of the second module 102 is connected to the input end of the residual error amplifier 20, so that a multiplication digital-to-analog converter MDAC circuit is formed.

Fig. 8 is a timing diagram of operation of the level 1 sub-ADC according to an embodiment of the invention. Next, please refer to fig. 2 and 8, in which the successive approximation type analog-to-digital converter with the pipeline domino structure includes a 3-stage 5-bit SAR sub-ADC, the operation principle of the 1 st stage sub-ADC is described in conjunction with a timing diagram.

The 1 st stage clock signal CLKS1 is high sampled, low held, CLKS1 is delayed to generate A1 clock signal CLKC5, CLKC5 triggering a first comparison from high to low.

The comparison result of the highest comparator A1 generates CLKC4 through a preset logic circuit, then the same process sequentially generates clock signals CLKC3, CLKC2 and CLKC1 of the comparators A2, A3, A4 and A5, and the output of the last comparator A5 generates a control signal CLKC0 through the preset logic circuit. The 5 comparators continuously perform binary search algorithm on the upper polar plate levels of the first type of capacitor and the second type of capacitor in the first module 101 at a faster speed, meanwhile, the comparison results of A1-A5 are also fed back to a preset logic circuit of the second module 102, the second module 102 follows the first module 101 to generate the same successive approximation process, only the time for the third type of capacitor and the fourth type of capacitor to flip to the stable level is longer, and the process is also the process of making difference between analog input signals in the MDAC and the DAC in the pipeline. The control signal CLKC0 is inverted to generate the latch control signal clk_lock1, the comparison result is stored in the latch structure, no change occurs in the present period, and the conversion period ends.

The calibration RESET signal reset_1 has a high level, and the switch SV1 is turned on to short-circuit the first type of capacitance and the second type of capacitance in the first module 101 together, and to generate the same level of the positive and negative input terminals of the comparator for the calibration process.

In the previous conversion process, the positive and negative input ends of the residual error amplifier 20 are connected to the common mode level, so as to ensure that the residual error amplifier 20 quickly enters a stable direct current bias state in the residual error amplification process. The common mode level control signal clk_vcm1 changes from high to low, indicating that the residual amplification stage begins.

The multiplying dac control signal clk_mdac1 comes almost simultaneously with the high level of CLKs1 of the second stage, and the capacitor array (i.e., the third type of capacitor and the fourth type of capacitor) in the second module 102 is connected to the input terminal of the residual amplifier 20, forming a multiplying dac MDAC module in the pipeline ADC. The first type capacitor and the second type capacitor of the second stage 5bit SAR ADC10 are connected to the output end of the residual error amplifier 20 to become the load of the operational amplifier. The operational amplifier amplifies the difference signal between the analog input on the capacitor plate and the DAC by 16 times to output to the capacitor array of the first and second capacitors. After the completion of the setup of the residual amplified signal, in order to ensure that the residual amplified signal sampled by the second stage is not disturbed, the second stage CLKS2 is turned off before the clk_mdac1 trigger switch. To ensure that the input signal is biased to a dc state that affects the op-amp, clk_mdac1 is turned off prior to the rising edge of the second stage CLKs 2.

In the process that the second module 102 participates in amplification, the upper plates of the first type capacitor and the second type capacitor in the first module 101 are short-circuited to the same level, then the comparator calibration RESET signal reset_c1 is changed to the low level, the calibration enable signal EN1 is triggered to be generated, and in the short pulse time when EN1 is in the high level, two AND gates in the calibration logic do not shield the signals CN1-5/CP1-5 any more, and the voltage VC is adjusted to compensate the offset voltage. (pulse width of EN1 determines charge and discharge time)

The quantization code D15-11 is output by the output control clock signal clk_d1.

The high level of CLKS1 comes and the fast-trigger EN1 signal goes low, masking the comparator output signal. The high level of CLKS1 quickly resets all comparators, leaving the capacitor array lower plates of the first and second modules 101 and 102 connected to VCM, starting a new sampling cycle.

Further, when the pipelined domino architecture successive approximation analog-to-digital converter includes a 3-stage 5-bit sub-ADC, please continue to refer to fig. 3, for a 2 nd stage sub-ADC, CLKS2 is the first stage sampling clock signal, and the frequency may be 1GHz, i.e., the period is 1ns, and likewise, 250ps is used for sampling, 750ps is used for conversion, residual amplification, and offset calibration in one period. Vref=0.9mv, vcm=450 mV, and vpp=1.8v input signals can be quantized, CLKS2 high samples the residual amplified signal VOUTP2/VOUTN2 of the first stage. The capacitor design of the second stage 5bit SAR takes into account the load capacity, slew rate and margin accuracy of the margin amplifier 20. The ratio of the first type of capacitor to the second type of capacitor is 16:8:4:2:1.

Fig. 9 is a timing diagram of operation of the level 2 sub-ADC according to an embodiment of the invention. Please refer to fig. 3 and 9, the operation of the 2 nd stage 5bit SAR sub-ADC is further described:

CLKS2 is high sampled, low held, CLKS2 is also the highest comparator clock CLKC5 that triggers the first comparison during the high-to-low process.

The comparison result of the highest bit comparator A1 generates CLKC4 through a preset logic circuit, and then the same process sequentially generates clock signals CLKC3, CLKC2, CLKC1 of the comparators A2, A3, A4, A5. The output of the last comparator A5 generates a control signal CLKC0 through a preset logic circuit. The comparators A1-A5 sequentially output 5-bit quantization codes, and the quantization codes control the pole plate switch under the capacitor to switch to generate a successive approximation process by a logic circuit, and the successive approximation process is also a process of making difference between analog input signals in the multiplying digital-analog converter MDAC and the DAC in the pipeline. The CLKC0 is inverted to generate the second-stage latch control signal clk_lock2, the comparison result is stored in the latch structure, no change occurs in the present period, and the conversion period ends.

In the previous conversion process, the positive and negative input ends of the operational amplifier are connected to the common mode level. And the operational amplifier is ensured to quickly enter a stable direct current bias state in the residual error amplifying process. The common mode control signal CLK_VCM1 changes from high to low, indicating the start of the residual amplification stage

The multiplication digital-to-analog converter control signal CLK_MDAC2 and the high level of the third-stage clock signal CLKS3 come almost simultaneously, and the second-stage capacitor array is connected to the input end of the operational amplifier to form an MDAC module in the pipeline ADC. And the capacitor array of the second stage 5bit SAR ADC is connected to the output end of the operational amplifier to become the load of the operational amplifier. The operational amplifier amplifies the difference signal between the analog input on the capacitor plate and the DAC by 16 times through negative feedback and outputs the amplified signal to the capacitor array of the third stage. After the completion of the setup of the residual amplified signal, CLKS3 is turned off before the clk_mdac2 trigger switch in order to ensure that the residual amplified signal of the third stage sampling is not disturbed. The residual amplification period ends.

After the falling edge of the third stage clock signal CLKS3, the switch SV2 is turned on, the differential input terminals of the second stage capacitor plates are shorted together, and the circuit enters a calibration period.

When the voltages of the equal capacitance polar plates are the same, the comparator calibration RESET signal RESET_c2 triggers the second-stage 5 comparators to RESET rapidly, and after the RESET is completed, a comparison result under the action of offset voltage is output.

In the high level window of the calibration enable signal EN2, the comparator output results control the current source to charge or discharge, thereby compensating for the offset voltage.

The quantized code D10-6 is output by the output control clock signal clk_d2.

CLKS3 is a third stage sampling clock signal with a frequency of 1GHz and a period of 1ns, where about 250ps is used for sampling and the remaining 750ps is used for conversion, residual amplification, offset calibration. Vref=0.9mv, vcm=450 mV, vpp=1.8v input signals can be quantized, CLKS3 high samples the residual amplified signal VOUTP2/VOUTN2 of the second stage. The third-stage 5-bit SAR sub-ADC does not need to transmit residual errors, so that the ratio of capacitance values of the first type of capacitance to the second type of capacitance is 8, 4, 2 and 1.

Fig. 10 is a timing diagram of operation of the 3 rd stage sub-ADC according to an embodiment of the invention. Referring to fig. 4 and 10, after the CLKs3 is sampled, CLKC4, CLKC3, CLK2, and CLK1 generate and output respective comparison results.

The third stage latches the low level of the control signal clk_lock3, latches the comparison result, and ends the conversion period.

The third stage comparator calibrates the RESET signal reset_c3 high to trigger the comparator RESET. Switch SV3 is turned on triggering a plate short on the differential capacitor. Reset_c3 is the result of the comparison of the output offset at the low level.

And in a high-level pulse window of the third-stage calibration enable signal EN3, the comparison result controls the charge and discharge of the capacitor on the comparator, and the calibration is completed.

The quantized code D5-1 is output by the output control clock signal clk_d3.

According to the above embodiments, the beneficial effects of the invention are as follows:

In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. A pipelined domino architecture successive approximation analog-to-digital converter comprising: the device comprises an n+1 level sub ADC, a plurality of residual error amplifiers and a preset adjusting module; wherein,

the 1 st to n th level sub-ADCs further comprise a second output end, wherein the second output end is connected to the next level sub-ADC through the residual error amplifier and is used for taking a signal amplified by the residual error amplifier of a residual error signal generated by the sub-ADC as an input signal and inputting the signal to the next level sub-ADC;

The circuit also comprises a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end, wherein the signal input end comprises a first signal input end and a second signal input end;

The sub-ADC includes: a first module, a calibration circuit, and an output module, the first module comprising a comparator: A1-A5, a first type capacitor, a second type capacitor, a first type switch, a second type switch and preset logic circuits corresponding to A1-A5 respectively, wherein the first type switch comprises a plurality of first switch groups, the second type switch comprises a plurality of second switch groups, each first switch group comprises three first switches, and each second switch group comprises three second switches; wherein,

the first ends of the second type capacitors are connected with the second signal input end, and the second ends of the second type capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three second switches in the second switch group respectively;

The level 1 sub-ADC further comprises a second module, the second module comprising a third type of capacitance, a fourth type of capacitance, a third type of switch, and a fourth type of switch, the third type of switch comprising a plurality of third switch groups, the fourth type of switch comprising a plurality of fourth switch groups, each third switch group comprising three third switches, each fourth switch group comprising three fourth switches; wherein,

The first ends of the fourth type capacitors are connected with the second signal input end, and the second ends of the fourth type capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three fourth switches in the fourth switch group respectively;

the sub-ADC further comprises a calibration circuit and an output module, wherein the calibration circuit is used for calibrating offset voltages of A1-A5, and the output module is used for storing 5-bit quantization codes generated by the sub-ADC.

2. The pipelined domino architecture successive approximation analog-to-digital converter of claim 1, wherein in the 1 st-n stage sub-ADC, the first type of capacitor comprises: cs1 to Cs5, and the second type capacitor includes: the ratio of capacitance values of Cs 6-Cs 10, cs1, cs2, cs3, cs4 and Cs5 is 16:8:4:2:1, and the ratio of capacitance values of Cs6, cs7, cs8, cs9 and Cs10 is 16:8:4:2:1.

3. The pipelined domino architecture successive approximation analog-to-digital converter of claim 1 wherein in a stage 1 sub-ADC, the third type of capacitance comprises: cs11 to Cs15, and the fourth type of capacitance includes: the ratio of capacitance values of Cs 16-Cs 20, cs11, cs12, cs13, cs14 and Cs15 is 16:8:4:2:1, and the ratio of capacitance values of Cs16, cs17, cs18, cs19 and Cs20 is 16:8:4:2:1.

4. The pipelined domino architecture successive approximation analog-to-digital converter of claim 1, further comprising a power supply signal terminal; the comparator includes a first sub-module and a second sub-module, the first sub-module including a first transistor: m1 to M7 and an inverter: b1, B2, the second submodule comprising a second transistor: m8 to M14 and an inverter: b1 to B4; wherein,

5. The pipelined domino architecture successive approximation analog-to-digital converter of claim 4 wherein M1, M2, M3, M8, M9 and M10 are P-type field effect transistors and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type field effect transistors.

6. The pipelined domino architecture successive approximation analog-to-digital converter of claim 5, wherein said calibration circuit comprises a third transistor: M15-M25, preset current sources, AND gates: c1 and C2, and inverter B5; wherein,

The grid electrode of M15 is connected with the grid electrode of M16, the source electrode of M15 and the source electrode of M16 are both connected with the power supply signal end, the drain electrode of M15 is connected with the source electrode of M17, the grid electrode of M17 is grounded, the drain electrode of M19 is connected with the drain electrode of M21, the source electrode of M21 is grounded, the drain electrode of M16 is connected with the source electrode of M18, the grid electrode of M18 is connected with a first switch signal, the drain electrode of M18 is connected with the drain electrode of M20, a seventh node is arranged between the drain electrode of M18 and the drain electrode of M20 and connected with the first reference voltage signal end, the grid electrode of M20 is connected with a second switch signal, the source electrode of M22 is connected with the drain electrode of M22, the source electrode of M22 is grounded, the grid electrode of M22 is connected with the preset current source, an eighth node is arranged between the grid electrode of M23 and the grid electrode of M21 is connected with the eighth node, and the drain electrode of M23 is grounded;