CN113839672B - Self-calibration successive approximation analog-digital converter utilizing redundant capacitor analog domain - Google Patents
Self-calibration successive approximation analog-digital converter utilizing redundant capacitor analog domain Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract
The invention discloses a self-calibration successive approximation analog-digital converter utilizing a redundant capacitor analog domain, which relates to the field of successive approximation analog-digital converters, wherein a redundant capacitor is added in a low-order capacitor array part of the successive approximation analog-digital converter, upper polar plates of the redundant capacitors are connected and connected with lower polar plates of a bridge capacitor, and the lower polar plates of each redundant capacitor are respectively connected with ground or reference voltage through a two-state switch; the successive approximation analog-to-digital converter adds the redundant capacitor in the low-order capacitor array part, and can perform analog domain self-calibration on other capacitors, especially the high-order capacitor by utilizing the redundant capacitor, so that the linearity of the analog-to-digital converter is improved, the performance is improved, and the added redundant capacitor is used for performing analog domain self-calibration on the capacitor array, so that the complexity of a circuit is simplified, and the design difficulty is reduced.
Description
Technical Field
The invention relates to the field of successive approximation analog-to-digital converters, in particular to a self-calibration successive approximation analog-to-digital converter utilizing a redundant capacitor analog domain.
Background
In recent years, signal measurement systems have been developed more and more rapidly, and extremely high requirements are placed on the speed and accuracy of measurement. Analog-to-digital converter (ADC) is a key module of the measurement system, whose performance directly affects the measurement result. In a common ADC structure, a successive approximation analog-to-digital converter (Successive Approximation Analog-to-Digital Converter, SAR ADC) is becoming the first choice of a measurement system due to its advantages in speed, accuracy and power consumption.
Taking a single-ended successive approximation analog-to-digital converter as an example, the structure of a conventional single-ended 12-bit successive approximation analog-to-digital converter sampled by a lower polar plate is shown in fig. 1, and the conventional single-ended 12-bit successive approximation analog-to-digital converter mainly comprises a capacitor array, a comparator, a successive approximation logic unit and a DAC control logic unit, wherein the capacitor array comprises a low-order capacitor array LSB and a high-order capacitor array MSB. The low-order capacitor array LSB comprises a terminal capacitor C 0 6 low-order capacitors C 1 ～C 6 Capacitance C in low-order capacitor array LSB 0 ～C 6 Is connected to the upper plate of the bridge capacitor C B The upper electrode plate of each capacitor passes through a three-state switch S 0 ～S 6 Connected to ground gnd, reference voltage V ref Or input voltage V IN And (3) upper part. The high-order capacitor array MSB comprises 6 high-order capacitors C 7 ～C 12 High-order capacitor C 7 ～C 12 Is connected to the upper plate of the bridge capacitor C B Lower plate of (2), inverting input terminal of comparator and sampling switch S cm Sampling switch S cm The other end of (2) is connected with the common mode level V cm High-order capacitor C 7 ～C 12 The lower polar plates of (2) respectively pass through a three-state switch S 7 ～S 12 Connected to ground gnd, reference voltage V ref Or input voltage V IN And (3) upper part. The non-inverting input end of the comparator is connected with the common mode level V cm . The output end of the comparator is connected with a successive approximation logic unit, the successive approximation logic unit generates data output, and meanwhile, the DAC control logic unit is used for controlling the states of all switches in the capacitor array.
The capacitor arrays of the MSB and LSB portions are each binary weighted capacitor arrays, i.e. the high order capacitor is twice as large as the low order capacitor, C in the MSB 7 ＝C u ，C 8 ＝2C u Similarly, C 12 ＝32C u The method comprises the steps of carrying out a first treatment on the surface of the In LSB, C 0 ＝C 1 ＝C u ，C 2 ＝2C u Similarly, C 6 ＝32C u ，C u Is the unit capacitance. Bridge capacitor C B And the equivalent capacitance of the LSB part is a unit capacitance C u Thus bridging the capacitor C B ＝(64/63)C u . Weight w occupied by capacitors in LSB and MSB capacitor arrays i ＝2 i-1 I=1 to 12, total capacitance weight w total ＝2 12 。
The successive approximation analog-to-digital converter comprises two stages of sampling and conversion: in the sampling stage, the lower polar plates of all the capacitors in LSB and MSB are all connected with V through corresponding three-state switch gating IN The upper polar plates of all the capacitors in the MSB pass through a sampling switch S cm Connection V cm . During conversion, sampling switch S cm Disconnection, C 12 Is connected to V ref The lower plates of all the other capacitors are connected to gnd, at which time V DAC ＝V cm -V IN +2048LSB，1LSB＝V ref /w total ＝V ref /4096. At this time the comparator compares V DAC And V cm If V is DAC Greater than V cm Then the next transition causes V by switching the capacitive lower plate DAC Subtracting 1024 LSBs from the value of (2); if V DAC Less than V cm Then the next transition causes V by switching the capacitive lower plate DAC After adding 1024LSB … to the value of (c) up to V by conventional successive approximation DAC Close to V cm At this time, the accumulated output result of the comparator is the digital value corresponding to the input voltage. In actual circuit manufacturing, the process deviation can cause the capacitance value of the capacitor array to be not designed as expected, so that errors occur in the result of each quantization in the conversion process, thereby causing the linearity of the ADC to be reduced, seriously affecting the signal-to-noise-and-distortion ratio of the ADC, and further causing the reduction of effective bits.
To solve the above problems, self-calibration of the capacitor array is introduced into a successive approximation analog-to-digital converter for calibrating mismatch of capacitors, and a common analog domain self-calibration successive approximation analog-to-digital converter structure is shown in fig. 2, which is an additional calibration capacitor C of the calibration DAC and MSB part compared to fig. 1 CAL Calibrating the capacitance C CAL ＝C 7 ＝C u Calibrating the capacitance C CAL Is the capacitance weight w of (2) CAL ＝2 6 The same weight w occupied by capacitors in LSB and MSB capacitor arrays i ＝2 i-1 I=1 to 12, then in fig. 2, the total capacitance weight w total ＝2 12 +2 6 . Calibration capacitor C CAL The upper polar plates of all high-order capacitors are connected with the upper polar plates of all high-order capacitors, the DAC control logic unit is connected with the calibration DAC, and the calibration DAC is connected with the calibration capacitor C CAL Is arranged on the lower polar plate.
The successive approximation analog-to-digital converter needs to perform self-calibration between normal operation to quantify mismatch on a capacitor, and the self-calibration process is divided into two stages of sampling and conversion. When for C 12 During calibration, C is added in the sampling stage 12 Is connected to V ref Removing C CAL The lower electrode plate of the other capacitors is connected to gnd, C CAL The lower electrode plate potential of (2) is 0.5V ref The upper polar plates of all the capacitors in the MSB pass through a sampling switch S cm Connection V cm . During the conversion phase, sampling switch S cm Disconnect C 12 Is connected to gnd except C CAL The lower electrode plate of the other capacitors is connected to V ref And (3) upper part. Ideally, when the capacitance is not mismatched, due to C 12 Occupied weight and division C CAL The sum of the weights of the other capacitors is the same, V DAC Should also be V at the sampling stage cm But due to mismatch, actual V DAC ＝V cm +V e12 ，V e12 Is C 12 Error voltages caused by mismatch of (c). Comparator compares V DAC And V cm If V DAC Greater than V cm The output of the calibration DAC is then controlled by 0.5V ref Reduced to 0.25V ref Due to C CAL The weight is 2 6 So V DAC Will decrease (w) CAL /w total )×0.25V ref ＝(2 6 /(2 12 +2 6 ))(2 -2 )V ref ＝(2 4 /(2 12 +2 6 ))V ref ＝16LSB，1LSB＝(V ref /w total )＝V ref /(2 12 +2 6 )，V DAC ＝V cm +V e12 -16LSB; if V DAC Less than V cm ，V DAC ＝V cm +V e12 +16LSB. The value of the calibration DAC is then continually changed such that V DAC Successive approximation to and V cm Equal, the digital input of the calibration DAC is C 12 The corresponding digital values are mismatched. The calibration process of other capacitors is similar to the above, and finally digital values corresponding to the mismatch of all the capacitors can be obtained. The range and accuracy of the calibration is determined by the number of bits of the calibration DAC, generally an 8-bit calibration DAC is sufficient to calibrate a 12-bit ADC. After self calibration, the normal operation of the successive approximation analog-to-digital converter is similar to that of fig. 1, but in the conversion stage, when the voltage of the lower plate of a capacitor at a certain position is switched, the digital value corresponding to the mismatch is backfilled into the calibration DAC to cancel the V caused by the switching of the capacitor DAC The mismatch voltage in the voltage change allows the ADC to obtain good linearity, thereby improving performance. But this requires the addition of a calibration DAC, which increases the complexity and area of the circuit.
Disclosure of Invention
Aiming at the problems and the technical requirements, the inventor provides a self-calibration successive approximation analog-to-digital converter utilizing a redundant capacitor analog domain, and the technical scheme of the invention is as follows:
the successive approximation analog-to-digital converter comprises a capacitor array connected to the input end of a comparator and a successive approximation logic unit connected to the output end of the comparator, wherein the successive approximation logic unit controls the working state of the capacitor array through a DAC control logic unit;
the capacitor array comprises a high-order capacitor array, a low-order capacitor array and a bridging capacitor, wherein the low-order capacitor array comprises a terminal capacitor with a unit capacitor, a plurality of low-order capacitors forming a binary weighted capacitor array from the unit capacitor and a plurality of redundant capacitors forming a binary weighted capacitor array from the unit capacitor, and upper polar plates of all capacitors in the low-order capacitor array are connected and connected with an upper polar plate of the bridging capacitor;
the high-order capacitor array comprises a plurality of high-order capacitors which form a binary weighted capacitor array from a unit capacitor, wherein the upper polar plates of all the high-order capacitors are connected and connected with the lower polar plate of the bridging capacitor, and the upper polar plates of the high-order capacitors are also connected to the comparator and connected to a common mode level through a sampling switch;
the terminal capacitors, all low-order capacitors and all high-order capacitors are respectively connected with the ground, the reference voltage or the input voltage through a three-state switch, and all redundant capacitors are respectively connected with the ground or the reference voltage through a two-state switch;
before the successive approximation analog-digital converter works normally, the mismatch value corresponding to each capacitor to be calibrated is determined by using the redundant capacitor, and when the three-state switch connected with the capacitor to be calibrated is subjected to voltage switching in the normal working process of the successive approximation analog-digital converter, the two-state switch connected with the opposite redundant capacitor is controlled to be subjected to voltage switching according to the mismatch value, so that the self calibration of the capacitor to be calibrated is realized.
The further technical proposal is that the low-order capacitor array comprises T redundant capacitors, and T-1 redundant capacitors form a slave unit capacitor C u A starting binary weighted capacitor array with a capacitance value of 2 respectively 0 C u ～2 T-2 C u The capacity value of the last redundant capacitor is (2 T-1 -1)C u Equivalent capacitance C of all redundant capacitances CAL ＝(2 T -2)C u 。
The further technical proposal is that the equivalent capacitance of the bridge capacitor and the terminal capacitor and the low-order capacitor in the low-order capacitor array is a unit capacitance C u When the equivalent capacitance of the terminal capacitance and all low-order capacitances is C A The equivalent capacitance of all the redundant capacitors is C CAL When the capacitance value of the bridge capacitor is X times of the unit capacitor, X is an integer, and the satisfied relation is:
the further technical scheme is that when determining the corresponding mismatch value of each capacitor to be calibrated:
controlling a three-state switch connected with a capacitor to be calibrated to be connected with a reference voltage, all other three-state switches to be connected with ground, a two-state switch connected with a redundant capacitor with highest capacitance weight to be connected with the reference voltage, all other two-state switches to be connected with ground, and controlling a sampling switch to be closed;
the sampling switch is controlled to be disconnected, the three-state switch connected with the capacitor to be calibrated is switched from the reference voltage to the ground, and the three-state switch with the capacitance weight of the connected capacitor lower than that of the capacitor to be calibrated is switched from the ground gnd to the reference voltage V ref The capacitance weight of the connected capacitor is higher than that of the three-state switch of the capacitor to be calibrated, the state of all the two-state switches is kept unchanged;
and switching voltages of the two-state switches connected with the redundant capacitor in sequence according to the output of the comparator from the high capacitance weight to the low capacitance weight until the voltage value of the input end of the comparator is in a quantization error range, and obtaining a mismatch value corresponding to the capacitor to be calibrated by the accumulated output of the comparator.
According to the further technical scheme, the voltage switching of the binary switches connected with the redundant capacitors is sequentially carried out according to the output of the comparator and the sequence from the big to the small of the capacitor weights, and the method comprises the following steps:
switching the current binary switch connected with the reference voltage and having the lowest capacitance weight of the corresponding redundant capacitor from the reference voltage to the ground, and switching the binary switch of the redundant capacitor with the lower capacitance weight of the next stage from the ground to the reference voltage, so that the voltage of one input end of the comparator connected with the capacitor array is reduced;
or switching the binary switch which is currently connected with the ground and corresponds to the redundant capacitor and has the highest capacitance weight from the ground to the reference voltage, so that the voltage of one input end of the comparator connected with the capacitor array is increased.
The further technical scheme is that the successive approximation analog-to-digital converter is a single-ended successive approximation analog-to-digital converter, one end of the comparator is connected with the capacitor array, and the other end of the comparator is connected with the common mode level.
The further technical scheme is that the successive approximation analog-to-digital converter is a differential successive approximation analog-to-digital converter, and two ends of the comparator are respectively connected with capacitor arrays with the same circuit structure.
The beneficial technical effects of the invention are as follows:
the successive approximation analog-to-digital converter adds a redundant capacitor in a low-order capacitor array part, and can be used for self-calibrating the analog domain of other capacitors in a capacitor array, especially the mismatch of a high-order capacitor, so that the matching degree of the capacitor array is improved, the successive approximation analog-to-digital converter obtains good linearity, the performance of the successive approximation analog-to-digital converter is improved, the added redundant capacitor is used for self-calibrating the analog domain of the capacitor array, the complexity of a circuit is simplified, and the design difficulty is reduced.
In addition, the redundant capacitor can enable the bridge capacitor to be an integer number of unit capacitors, so that manufacturing difficulty is reduced, and matching degree of the capacitor array is further improved.
Drawings
Fig. 1 is a schematic diagram of a conventional 12-bit successive approximation analog-to-digital converter.
Fig. 2 is a schematic diagram of a conventional 12-bit successive approximation analog-to-digital converter with analog domain self-calibration added to the one shown in fig. 1.
Fig. 3 is a schematic diagram of a 12-bit successive approximation analog-to-digital converter based on the logic implementation of the present application.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings.
The application discloses a self-calibration successive approximation analog-to-digital converter utilizing a redundant capacitor analog domain, which comprises a capacitor array connected to the input end of a comparator CMP and a successive approximation logic unit connected to the output end of the comparator CMP, wherein the successive approximation logic unit controls the working state of the capacitor array through a DAC control logic unit.
The successive approximation analog-to-digital converterIs a single-ended successive approximation analog converter, one end of the comparator CMP is connected with the capacitor array, and the other end is connected with the common mode level V cm The comparator CMP may have its non-inverting input connected to the capacitor array and its inverting input connected to the common mode level V cm Or the inverting input terminal of the comparator CMP is connected with the capacitor array, and the non-inverting input terminal is connected with the common mode level V cm This is exemplified in fig. 3.
Alternatively, the successive approximation analog-to-digital converter is a differential successive approximation analog-to-digital converter, and two ends of the comparator CMP are respectively connected with capacitor arrays with the same circuit structure.
Each capacitor array comprises a high-order capacitor array MSB, a low-order capacitor array LSB and a bridge capacitor C B The low-order capacitor array LSB includes a capacitor having a unit capacitor C u Terminal capacitance C of (2) 0 A plurality of slave unit capacitors C u The upper polar plates of all capacitors in the low-order capacitor array are connected and connected with a bridge capacitor C B Is arranged on the upper polar plate of the upper polar plate.
The MSB of the high-order capacitor array comprises a plurality of slave unit capacitors C u The upper polar plates of all the high-order capacitors are connected and connected with a bridging capacitor C B The upper plate of the high-order capacitor is also connected to the comparator CMP and through the sampling switch S cm To a common mode level V cm 。
The terminal capacitor, all low-order capacitors and all high-order capacitors are respectively connected with ground gnd and reference voltage V through a three-state switch ref Or input voltage V IN All redundant capacitors are respectively connected with ground gnd or reference voltage V through a two-state switch ref 。
For an N-bit successive approximation analog-to-digital converter, the low-order capacitor array LSB comprisesThe lower capacitors are respectively marked as C 1 ～C (N/2) For any->The capacitance value of the corresponding low-order capacitor is C j ＝2 j-1 C u . The MSB of the high-order capacitor array comprises +>The high-order capacitors are respectively marked as C (N/2)+1 ～C N For any->The capacitance value of the corresponding high-order capacitor is +.>
Further, in another embodiment, the T redundant capacitors in the low-order capacitor array do not form a complete binary weighted capacitor array, but the T-1 redundant capacitors form a binary weighted capacitor array starting from a unit capacitor and having a capacitance of 2, respectively 0 C u ～2 T-2 C u The capacity value of the last redundant capacitor is (2 T-1 -1)C u Equivalent capacitance C of all redundant capacitances CAL ＝(2 T -2)C u 。
For example, taking n=12 as an example, the low-order capacitor array LSB includes a termination capacitor C 0 The 6 low-order capacitors are C respectively 1 ～C 6 And low-order capacitance C 1 ～C 6 The capacitance values of (C) are in turn C u 、2C u 、4C u 、8C u 、16C u 、32C u Terminal capacitance C 0 ＝C 1 ＝C u . The low-order capacitor array LSB also comprises 6 redundant capacitors which are C respectively c1 ～C c6 And redundancy capacitor C c1 ～C c6 The capacitance values of (C) are in turn C u 、2C u 、4C u 、8C u 、16C u 、31C u . And the MSB of the high-order capacitor array comprises 6 high-order capacitors which are respectively C 7 ～C 12 And high-order capacitor C 7 ～C 12 The capacitance values of (C) are in turn C u 、2C u 、4C u 、8C u 、16C u 、32C u 。
Bridge capacitor C B The equivalent capacitance of the terminal capacitance and the low-order capacitance in the low-order capacitance array LSB is a unit capacitance C u . It is therefore assumed that the terminal capacitance C 0 And the equivalent capacitance of all low-order capacitors is C A The equivalent capacitance of all the redundant capacitors is C CAL Bridge capacitor C B When the capacitance value of (C) is X times of the unit capacitance, X is an integer, C A 、C CAL And C B The following relationships are satisfied:
thus, by adding a redundant capacitor to the low-order capacitor array, the bridge capacitor C can be formed B The capacitance value of (2) is an integer multiple of the unit capacitance C u The manufacturing difficulty is reduced, so that the matching degree of the capacitor array can be effectively improved.
The added redundant capacitor forms a binary weighted capacitor array from the unit capacitor, and the redundant capacitor is used for carrying out self calibration in an analog domain on mismatch of other capacitors in the capacitor array so as to improve the performance of the ADC. The successive approximation analog-to-digital converter performs mismatch calibration on the capacitance to be calibrated in the capacitance array by using the redundant capacitance in a normal working process, wherein the normal working process refers to a process of performing analog conversion. The capacitor to be calibrated at least comprises a high-order capacitor in the capacitor array and can also comprise a low-order capacitor, and because the capacitor weight of the high-order capacitor is higher, the mismatch of the high-order capacitor has a larger influence on the ADC performance, and the ADC performance can be greatly improved by calibrating the mismatch of the high-order capacitor, so that the mismatch calibration can be carried out only on the high-order capacitor, and the operation is simplified.
The successive approximation analog-to-digital converter first determines the mismatch value corresponding to each capacitance to be calibrated using the redundant capacitance before normal operation. Specifically, when determining the mismatch value corresponding to each capacitance to be calibrated:
1. in the sampling stage, the capacitance to be calibrated is controlledThe connected three-state switch being connected to a reference voltage V ref All other three-state switches are connected to ground gnd, and the two-state switch connected to the redundant capacitor with the highest capacitance weight is connected to the reference voltage V ref The binary switches of all other redundant capacitors are connected to ground gnd and control the sampling switch S cm Closing to make the upper polar plates of the high-order capacitor connected with the common mode level V cm 。
2. In the conversion phase, the sampling switch S is controlled cm Disconnecting the tristate switch connected with the capacitor to be calibrated from the reference voltage V ref Three-state switches switched to ground gnd, the capacitance weight of the connected capacitance being lower than the capacitance to be calibrated, are switched from ground gnd to the reference voltage V ref The capacitance weight of the connected capacitor is higher than that of the three-state switch of the capacitor to be calibrated, and the state of the two-state switch of all the redundant capacitors is kept unchanged. If there is no mismatch in the capacitance to be calibrated at this time, since the capacitance weight of the capacitance to be calibrated is the same as the sum of the capacitance weights of the remaining capacitances other than the redundant capacitance of the capacitance to be calibrated, ideally, there is no mismatch, V is provided to the comparator by the capacitance array DAC Should also be V at the sampling stage cm . For example, in FIG. 3, C 12 The occupied capacitance weight is equal to C 0 ～C 11 The sum of the capacitance weights taken up is the same, and C 11 The occupied capacitance weight is equal to C 0 ～C 10 The sum of the occupied capacitance weights is the same.
But in practice, due to the capacitance mismatch, this results in a capacitor array providing V to the comparator DAC V at the sampling stage and the value of (2) cm And if the voltage of the input end of the comparator is within a quantization error range, the mismatch value corresponding to the capacitance to be calibrated is obtained by the accumulated output of the comparator. Specifically, if the non-inverting input end of the comparator is connected to the capacitor array and the output of the comparator is 1, the voltage of the capacitor array representing the non-inverting input end is higher, and the capacitor array is adjusted to make the capacitor arrayThe voltage at the non-inverting input of the column-connected comparator decreases; if the comparator output is 0, the voltage of the capacitor array at the non-inverting input terminal is lower, and the capacitor array is adjusted to raise the voltage at the non-inverting input terminal of the comparator connected with the capacitor array. And/or, if the inverting input end of the comparator is connected with the capacitor array and the output of the comparator is 1, the voltage of the capacitor array representing the inverting input end is lower, and the capacitor array is adjusted at the moment so that the voltage of the inverting input end of the comparator connected with the capacitor array is increased; if the comparator output is 0, the voltage of the capacitor array representing the inverting input terminal is high, and the capacitor array is adjusted so that the voltage of the inverting input terminal of the comparator connected with the capacitor array is reduced. Then in particular:
will currently be connected with reference voltage V ref And the binary switch with the lowest capacitance weight of the corresponding redundant capacitor is controlled by the reference voltage V ref The binary switch of the redundant capacitor with lower capacitance weight of the next stage is switched from ground gnd to the reference voltage V ref The voltage at one input of the comparator connected to the capacitor array is reduced. Alternatively, the binary switch currently connected to ground gnd and having the highest capacitance weight of the corresponding redundant capacitor is switched from ground gnd to reference voltage V ref The voltage at one input of the comparator connected to the capacitor array is raised.
For example, assume that the capacitance to be calibrated is C in FIG. 3 12 Then in the sampling stage, control S 12 Connection V ref ，S 0 ～S 11 Are all connected with gnd and redundant capacitor C c6 Corresponding two-state switch S c6 Connection V ref The rest S c1 ～S c5 Are all connected to gnd and close S cm . During the conversion phase, S cm Disconnection, S 12 Switch to connection gnd, S 0 ～S 11 Switching to connection V ref Ideally, if there is no capacitance mismatch, then due to C 12 The occupied capacitance weight is equal to C 0 ～C 11 The sum of the capacitance weights taken up is the same, at this time V DAC Should also be V at the sampling stage cm But due to mismatch, actual V DAC ＝V cm +V e12 ，V e12 Is C 12 Error voltages caused by mismatch of (c). Comparator compares V DAC And V cm Is the value of (1):
if the comparator outputs 0, then V is represented DAC Greater than V cm At this time C will be c6 Corresponding S c6 Switching to the connection gnd to switch the redundant capacitor C of the next stage of capacitor weight c5 Corresponding S c5 Switching to V ref So that V DAC And (3) lowering. Due to C c6 Is 31, and C c5 The capacitance weight of (2) is 16, so V at this time DAC ＝V cm +V e12 15LSB, i.e. 15LSB reduced. Wherein 1 lsb= (1/w total )V ref ＝(1/(2 12 +62))V ref 。
If the comparator outputs 1, this indicates V DAC Less than V cm At this time C will be c5 Corresponding S c5 Switching to V ref So that V DAC Raised. Due to C c5 The capacitance weight of (2) is 16, so V at this time DAC ＝V cm +V e12 +16LSB, i.e. 16LSB raised.
The two-state switch is then switched according to the logic above, so that V DAC Successive approximation to and V cm Equality, until the voltage value at the input end of the comparator is within a quantization error range, namely within 1LSB, the value accumulated and output by the comparator is C 12 Corresponding mismatch values. And determining the corresponding mismatch values of the other capacitors to be calibrated according to the method. Based on the circuit shown in fig. 3, the calibration range is ±31LSB, and the accuracy is 1LSB.
After the mismatch values corresponding to the capacitors to be calibrated are obtained in advance, when the successive approximation analog-digital converter is in normal operation, and when the three-state switch connected with the capacitors to be calibrated is used for voltage switching, the two-state switch connected with the corresponding redundant capacitor is controlled to be used for voltage switching, so that the self calibration of the capacitors to be calibrated is realized. For differential successive approximation analog-to-digital converters, the operation of the two ends is reversed and similar, as well as the above-described functions.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present invention are deemed to be included within the scope of the present invention.
Claims (7)
1. The self-calibration successive approximation analog-to-digital converter is characterized by comprising a capacitor array connected to the input end of a comparator and a successive approximation logic unit connected to the output end of the comparator, wherein the successive approximation logic unit controls the working state of the capacitor array through a DAC control logic unit;
the low-order capacitor array comprises a terminal capacitor with unit capacitors, a plurality of low-order capacitors forming a binary weighted capacitor array from the unit capacitors and a plurality of redundant capacitors forming a binary weighted capacitor array from the unit capacitors, and upper polar plates of all capacitors in the low-order capacitor array are connected and connected with upper polar plates of the bridging capacitors;
the high-order capacitor array comprises a plurality of high-order capacitors which form a binary weighted capacitor array from a unit capacitor, wherein the upper polar plates of all the high-order capacitors are connected and connected with the lower polar plate of the bridging capacitor, and the upper polar plates of the high-order capacitors are also connected to the comparator and connected to a common mode level through a sampling switch;
the terminal capacitors, all low-order capacitors and all high-order capacitors are respectively connected with the ground, the reference voltage or the input voltage through a three-state switch, and all redundant capacitors are respectively connected with the ground or the reference voltage through a two-state switch;
and when the three-state switch connected with the capacitor to be calibrated is subjected to voltage switching in the normal working process, the successive approximation analog-digital converter controls the two-state switch connected with the opposite redundant capacitor to be subjected to voltage switching according to the mismatch value so as to realize self calibration of the capacitor to be calibrated.
2. The successive approximation analog-to-digital converter according to claim 1, wherein the low-order capacitor array comprises T redundant capacitors, T-1 redundant capacitors forming the slave unit capacitor C u A starting binary weighted capacitor array with a capacitance value of 2 respectively 0 C u ～2 T-2 C u The capacity value of the last redundant capacitor is (2 T-1 -1)C u Equivalent capacitance C of all redundant capacitances CAL ＝(2 T -2)C u 。
3. The successive approximation analog-to-digital converter according to claim 2, wherein the bridge capacitor is a unit capacitor C with equivalent capacitances of the terminal capacitors and the low-order capacitors in the low-order capacitor array u When the equivalent capacitance of the terminal capacitance and all low-order capacitances is C A The equivalent capacitance of all the redundant capacitors is C CAL When the capacitance value of the bridge capacitor is X times of the unit capacitor, X is an integer, and the satisfied relation is:
4. a successive approximation analog-to-digital converter as claimed in any one of claims 1 to 3, wherein, in determining the corresponding mismatch value for each capacitance to be calibrated:
controlling the three-state switches connected with the capacitor to be calibrated to be connected with a reference voltage, all other three-state switches to be connected with ground, connecting the two-state switch connected with the redundant capacitor with the highest capacitance weight to the reference voltage, connecting all other two-state switches to the ground, and controlling the sampling switch to be closed;
the sampling switch is controlled to be disconnected, the three-state switch connected with the capacitor to be calibrated is switched from the reference voltage to the ground, and the three-state switch with the capacitance weight of the connected capacitor lower than that of the capacitor to be calibrated is switched from the ground gnd to the reference voltage V ref The capacitance weight of the connected capacitor is higher than that of the three-state switch of the capacitor to be calibrated, the state of all the two-state switches is kept unchanged;
and switching voltages of the binary switches connected with the redundant capacitors in sequence according to the output of the comparator from the large to the small of the capacitor weight until the voltage value of the input end of the comparator is in a quantization error range, and obtaining the mismatch value corresponding to the capacitor to be calibrated by the accumulated output of the comparator.
5. The successive approximation analog-to-digital converter of claim 4, wherein the voltage switching of the redundancy capacitor connected bi-state switches in order of increasing capacitive weight according to the output of the comparator comprises:
switching a binary switch which is currently connected with a reference voltage and has the lowest capacitance weight of a corresponding redundant capacitor from the reference voltage to the ground, and switching a binary switch of a redundant capacitor with the lower capacitance weight of the next stage from the ground to the reference voltage, so that the voltage of one input end of a comparator connected with the capacitor array is reduced;
or switching the binary switch which is currently connected with the ground and corresponds to the redundant capacitor and has the highest capacitance weight from the ground to the reference voltage, so that the voltage of one input end of the comparator connected with the capacitor array is increased.
6. A successive approximation analog-to-digital converter as claimed in any one of claims 1 to 3, wherein the successive approximation analog-to-digital converter is a single-ended successive approximation analog converter, and wherein the comparator is connected to the capacitor array at one end and to the common mode level at the other end.
7. A successive approximation analog-to-digital converter as claimed in any one of claims 1 to 3, wherein the successive approximation analog-to-digital converter is a differential successive approximation analog-to-digital converter, and two ends of the comparator are respectively connected to the capacitor arrays having the same circuit structure.
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| CN114978179B (en) * | 2022-06-24 | 2024-10-01 | 电子科技大学 | Correctable mixed structure digital-to-analog converter and application thereof |
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| CN116505946B (en) * | 2023-06-21 | 2023-10-13 | 江苏润石科技有限公司 | Analog domain calibration method and device of SAR ADC and SAR ADC |
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