CN113838953A - Simple eutectic LED chip structure and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 230000005496 eutectics Effects 0.000 title claims abstract description 22
- 238000003466 welding Methods 0.000 claims abstract description 55
- 230000000149 penetrating effect Effects 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 8
- 229910015844 BCl3 Inorganic materials 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000011282 treatment Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 9
- 230000001680 brushing effect Effects 0.000 description 6
- 238000005476 soldering Methods 0.000 description 5
- 230000004907 flux Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 2
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
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Abstract
The invention provides a simple eutectic LED chip structure and a manufacturing method thereof, wherein the LED chip structure comprises a P electrode, an N electrode, a Bragg reflection layer, a P welding layer and an N welding layer; the P electrode is arranged below the Bragg reflection layer and is connected with the P welding layer through a first through hole penetrating through the Bragg reflection layer; the N electrode is arranged below the Bragg reflection layer and is connected with the N welding layer through a second through hole penetrating through the Bragg reflection layer; the manufacturing method comprises the steps of manufacturing a step structure, manufacturing a single wafer, manufacturing a P electrode and an N electrode, manufacturing the Bragg reflection layer and manufacturing the P welding layer and the N welding layer.
Description
Technical Field
The invention relates to the technical field of LED chip structures, in particular to a simple eutectic LED chip structure and a manufacturing method thereof.
Background
Compared with the normally-installed LED chip, the flip LED chip has the advantages of low thermal resistance, high current, no routing, close arrangement and the like. In recent years, flip-chip LED chips are more and more emphasized, and many units and scientific and technical enterprises invest in research on the aspect, so that the market scale and specific gravity of the flip-chip LED chips are increased year by year, and particularly, the flip-chip LED chips have great market potential in the aspect of mini chips. Because the mini chip is small enough, when the eutectic operation of the packaging end is carried out, the mini chip cannot be operated by a tin paste mode, and generally the mini chip is operated by a screen printing mode. And mini level screen printing is carried out at the encapsulation end of the mini chip, so that the eutectic difficulty is increased, the cost is increased due to undersize, the electric leakage probability is increased, and the yield is reduced.
In summary, there is a need for a simple eutectic LED chip structure and a method for fabricating the same to solve the problems of high eutectic difficulty, high cost and low yield in screen printing in the prior art.
Disclosure of Invention
The invention aims to provide a simple eutectic LED chip structure and a manufacturing method thereof, and the specific technical scheme is as follows:
a simple eutectic LED chip structure comprises a P electrode, an N electrode, a Bragg reflection layer, a P welding layer and an N welding layer; the P electrode is arranged below the Bragg reflection layer and is connected with the P welding layer through a first through hole penetrating through the Bragg reflection layer; the N electrode is arranged below the Bragg reflection layer and is connected with the N welding layer through a second through hole penetrating through the Bragg reflection layer;
the electrode structures of the P welding layer (and the N welding layer) are a Cr layer, an Al layer, a (Ti layer/Pt layer) N, an Au layer and an Sn layer which are sequentially stacked on the Bragg reflection layer, wherein the Ti layer/Pt layer represents the Ti layer and the Pt layer which are sequentially stacked, N represents the repeated times of the stacked Ti layer and the stacked Pt layer, and the value of N is not less than 1.
Preferably, the thickness of the Cr layer is 5-50A; the thickness of the Al layer is 1000-5000A; the thickness of a single Ti layer is 500-2000A; the thickness of a single Pt layer is 1000-2000A; the thickness of the Au layer is 500-; the thickness of the Sn layer is 40000-100000A.
Preferably, the simple eutectic LED chip structure further comprises a basic structure, wherein the basic structure comprises a substrate, and a buffer layer, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer and a transparent conducting layer which are sequentially stacked on the substrate; arranging a step structure on the N-type semiconductor layer to the transparent conducting layer; the N electrode is arranged on the step structure and is connected with the N-type semiconductor layer; the P electrode is arranged on the transparent conducting layer.
A manufacturing method of the simple eutectic LED chip structure comprises the following steps:
step S1, manufacturing a step structure
After the basic structure is pretreated, the transparent conducting layer, the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer are etched to form a step structure;
step S2, manufacturing single wafer
After the step structure in the step S1 is preprocessed, determining a cutting path area, and etching the cutting path area to the position of the substrate to form a single wafer;
step S3, making P electrode and N electrode
After the single wafer manufactured in the step S2 is pretreated, an N electrode is plated on the N-type semiconductor layer, and a P electrode is plated on the transparent conductive layer; then, removing the redundant metal of the P electrode and the N electrode by a metal stripping method;
step S4, manufacturing Bragg reflection layer
After the overall structure formed in the step S3 is preprocessed, plating a bragg reflection layer, and etching the positions corresponding to the P electrode and the N electrode on the bragg reflection layer respectively to form a first through hole and a second through hole penetrating through the bragg reflection layer;
step S5, manufacturing P welding layer and N welding layer
After the bragg reflection layer in the step S4 is preprocessed, a P welding layer connected to the P electrode and an N welding layer connected to the N electrode are respectively plated on the bragg reflection layer; then, the redundant metal of the P welding layer and the N welding layer is removed through a metal stripping method.
Preferably, the etching in step S1, step S2, and step S4 are all ICP etching.
Preferably, in step S1, the etching process parameters are: ICP power is 300-800W, RF power is 50-150W, cavity pressure is 3-8mtorr, BCl3Flow rate of 5-20sccm, Cl2The flow rate is 30-100sccm, and the etching time is 10-15 min.
Preferably, in step S2, the etching process parameters are: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 30-45 min.
Preferably, in step S4, the etching process parameters are: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, CF4The flow rate is 80-120sccm, O2The flow rate is 16-24sccm, and the etching time is 30-45 min.
Preferably, the pre-treatments in steps S1-S5 each include the steps of spin coating, soft baking, exposing, developing and hardening the pre-treated object in each step, and then copying the pattern on the reticle onto the surface of the pre-treated object; the photoresist is uniformly coated on the surface of the pretreatment object.
Preferably, the steps S1-S5 all include post-treatment, and the post-treatment includes that the product manufactured in the steps S1-S5 is placed into the degumming solution to be soaked for 12-18min, the photoresist on the surface of the product is washed off, and the product is dried by flushing water.
The technical scheme of the invention has the following beneficial effects:
(1) according to the LED chip structure prepared by the invention, the P welding layer and the N welding layer which are manufactured at the end parts of the LED chip structure are provided with the end-sealed Sn layer, and the conductive tin paste is not required to be screen-printed during packaging and welding, so that the eutectic difficulty is greatly reduced. Further, the Ti layer and the Pt layer stacked below the Sn layer can effectively block the diffusion of Sn in the Sn layer.
(2) The LED chip structure manufactured by the manufacturing method has the advantages of low cost and high yield. When the LED chip structure is used, the LED chip structure is usually mounted on an external circuit carrier (such as a circuit board). Specifically, firstly, brushing a layer of insulating rosin soldering flux on a P welding layer and an N welding layer of an LED chip structure; then, the P and N bonding layers of the LED chip structure are assembled on a circuit carrier. Compared with the existing method for brushing soldering flux on the packaging end and brushing solder paste, the method has the advantages that short circuit is avoided and the electric leakage probability is greatly reduced by means of the specific electrode structures of the P welding layer and the N welding layer when the method is used.
In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a simple eutectic LED chip structure in embodiment 1 of the present invention;
the LED comprises a substrate 1, a substrate 2, a buffer layer 3, an N-type semiconductor layer 4, a light emitting layer 5, a P-type semiconductor layer 6, a transparent conducting layer 7, a P electrode 8, an N electrode 9, a Bragg reflecting layer 10, a P welding layer 11, an N welding layer A, a first through hole B and a second through hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
Example 1:
referring to fig. 1, a simple eutectic LED chip structure includes a P electrode 7, an N electrode 8, a bragg reflection layer 9, a P bonding layer 10, and an N bonding layer 11; the P electrode 7 is arranged below the Bragg reflection layer 9 and is connected with the P welding layer 10 through a first through hole A penetrating through the Bragg reflection layer 9; the N electrode 8 is arranged below the Bragg reflection layer 9 and is connected with the N welding layer 11 through a second through hole B penetrating through the Bragg reflection layer 9;
the electrode structures of the P welding layer 10 and the N welding layer 11 are a Cr layer, an Al layer, a (Ti layer/Pt layer) N, an Au layer and an Sn layer which are sequentially stacked on the bragg reflection layer 9, wherein the Ti layer/Pt layer represents a Ti layer and a Pt layer which are sequentially stacked, N represents the number of times of repeating the stacked Ti layer and Pt layer, and N is 2.
The thickness of the Cr layer is 15A; the thickness of the Al layer is 1500A; the thickness of each Ti layer is 1000A; the thickness of a single Pt layer is 1000A; the thickness of the Au layer is 500A; the thickness of the Sn layer is 50000A.
The simple eutectic LED chip structure further comprises a basic structure, wherein the basic structure comprises a substrate 1, and a buffer layer 2, an N-type semiconductor layer 3, a light-emitting layer 4, a P-type semiconductor layer 5 and a transparent conducting layer 6 which are sequentially stacked on the substrate 1; step structures are arranged on the N-type semiconductor layer 3 to the transparent conducting layer 6; the N electrode 8 is arranged on the step structure and is connected with the N-type semiconductor layer 3; the P-electrode 7 is disposed on the transparent conductive layer 6.
A manufacturing method of a simple eutectic LED chip structure comprises the following steps:
step S1, manufacturing a step structure
After the basic structure is pretreated, the transparent conducting layer 6, the P-type semiconductor layer 5, the light emitting layer 4 and the N-type semiconductor layer 3 are etched to form a step structure;
step S2, manufacturing single wafer
After the step structure in the step S1 is preprocessed, determining a dicing street area, and etching the dicing street area to the position of the substrate 1 to form a single wafer;
step S3, making P electrode 7 and N electrode 8
After the single wafer manufactured in the step S2 is pretreated, the N electrode 8 is plated on the N-type semiconductor layer 3 and the P electrode 7 is plated on the transparent conductive layer 6 by using an evaporation station or a sputtering coating method; then, removing the redundant metal of the P electrode 7 and the N electrode 8 by a metal stripping method;
step S4, manufacturing Bragg reflection layer 9
Pretreating the integral structure formed in the step S3 by using an optical evaporation machine, plating a Bragg reflection layer 9, and respectively etching the positions, corresponding to the P electrode 7 and the N electrode 8, of the Bragg reflection layer 9 to form a first through hole A and a second through hole B which penetrate through the Bragg reflection layer 9;
step S5, manufacturing P welding layer 10 and N welding layer 11
After pretreating the bragg reflection layer 9 in step S4, respectively plating a P welding layer 10 connected to the P electrode 7 and an N welding layer 11 connected to the N electrode 8 on the bragg reflection layer 9 by using an evaporation station or a sputter coating method; then, the excess metal of the P-bonding layer 10 and the N-bonding layer 11 is removed by metal lift-off.
The etching in step S1, step S2, and step S4 are each ICP (inductively coupled plasma) etching.
In step S1, the etching process parameters are: ICP power was 500W, RF power was 80W, and chamber pressure was 5mtorr, BCl3Flow rate of 10sccm, Cl2The flow rate is 50sccm, and the etching time is 10-15 min.
In step S2, the etching process parameters are: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 30-45 min.
In step S4, the etching process parameters are: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, CF4The flow rate is 80-120sccm, O2The flow rate is 16-24sccm, and the etching time is 30-45 min.
The pre-processing in steps S1-S5 each include the steps of spin coating, soft baking, exposing, developing and hardening the pre-processed object in each step, and then copying the pattern on the reticle onto the surface of the pre-processed object; the photoresist is uniformly coated on the surface of the pretreatment object.
And the steps S1-S5 all comprise post-treatment, wherein the post-treatment comprises the steps of soaking the product manufactured in the steps S1-S5 in a degumming solution for 12-18min, washing off the photoresist on the surface of the product, and washing by water for drying.
The P-bonding layer 10 and the N-bonding layer 11 formed at the ends of the LED chip structure prepared in embodiment 1 have end-capped Sn layers, and conductive solder paste is not required to be screen-printed during package soldering, which greatly reduces eutectic difficulty. Further, the Ti layer and the Pt layer stacked below the Sn layer can effectively block the diffusion of Sn in the Sn layer. Specifically, when the LED chip structure used, P welding layer 10 and N welding layer 11 need be used with the circuit carrier equipment, and need heat between the two, and heating temperature reaches more than 200 ℃, can lead to Sn layer and Au layer to melt each other, and at this moment, the diffusion of Sn in the Sn layer can effectively be blockked on the Ti layer and the Pt layer that set up, and effectively avoid P welding layer 10 and N welding layer 11's electrode structure to be wholly melted and drop. For the Cr layer in the electrode structure of the P-bonding layer 10 and the N-bonding layer 11 to enhance adhesion, Al is used as a reflective metal to improve the light emitting efficiency of the LED chip.
The LED chip structure manufactured by the manufacturing method of the embodiment 1 has the advantages of low cost and high yield. When the LED chip structure is used, the LED chip structure is usually mounted on an external circuit carrier (such as a circuit board). Specifically, firstly, brushing a layer of insulating rosin soldering flux on a P welding layer 10 and an N welding layer 11 of an LED chip structure; then, the P-bonding layer 10 and the N-bonding layer 11 of the LED chip structure are assembled on the circuit carrier. Compared with the existing method for brushing soldering flux at the packaging end and brushing solder paste, the method has the advantages that short circuit is avoided and the leakage probability is greatly reduced by means of the specific electrode structures of the P welding layer 10 and the N welding layer 11 during use.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A simple eutectic LED chip structure is characterized by comprising a P electrode (7), an N electrode (8), a Bragg reflection layer (9), a P welding layer (10) and an N welding layer (11); the P electrode (7) is arranged below the Bragg reflection layer (9) and is connected with the P welding layer (10) through a first through hole (A) penetrating through the Bragg reflection layer (9); the N electrode (8) is arranged below the Bragg reflection layer (9) and is connected with the N welding layer (11) through a second through hole (B) penetrating through the Bragg reflection layer (9);
the electrode structures of the P welding layer (10) and the N welding layer (11) are a Cr layer, an Al layer and a (Ti layer/Pt layer) which are sequentially stacked on the Bragg reflection layer (9)nThe metal layer comprises a Ti layer, an Au layer and an Sn layer, wherein the Ti layer/the Pt layer represents a Ti layer and a Pt layer which are sequentially stacked, n represents the repeated times of the stacked Ti layer and the stacked Pt layer, and the value of n is not less than 1.
2. The easy eutectic LED chip structure of claim 1, wherein said Cr layer has a thickness of 5-50A; the thickness of the Al layer is 1000-5000A; the thickness of a single Ti layer is 500-2000A; the thickness of a single Pt layer is 1000-2000A; the thickness of the Au layer is 500-; the thickness of the Sn layer is 40000-100000A.
3. The eutectic LED chip structure according to claim 2, further comprising a base structure, wherein said base structure comprises a substrate (1), and a buffer layer (2), an N-type semiconductor layer (3), a light emitting layer (4), a P-type semiconductor layer (5) and a transparent conductive layer (6) sequentially stacked on the substrate (1); step structures are arranged on the N-type semiconductor layer (3) to the transparent conducting layer (6); the N electrode (8) is arranged on the step structure and is connected with the N-type semiconductor layer (3); the P electrode (7) is arranged on the transparent conducting layer (6).
4. A method of fabricating a simplified eutectic LED chip structure according to claim 3, comprising the steps of:
step S1, manufacturing a step structure
After the basic structure is pretreated, the transparent conducting layer (6), the P-type semiconductor layer (5), the light emitting layer (4) and the N-type semiconductor layer (3) are etched to form a step structure;
step S2, manufacturing single wafer
After the step structure in the step S1 is preprocessed, determining a cutting path area, and etching the cutting path area to the position of the substrate (1) to form a single wafer;
step S3, preparing P electrode (7) and N electrode (8)
After the single wafer manufactured in the step S2 is preprocessed, an N electrode (8) is plated on the N-type semiconductor layer (3), and a P electrode (7) is plated on the transparent conductive layer (6); then, removing the redundant metal of the P electrode (7) and the N electrode (8) by a metal stripping method;
step S4, manufacturing Bragg reflection layer (9)
After the integral structure formed in the step S3 is preprocessed, a Bragg reflection layer (9) is plated, and a first through hole (A) and a second through hole (B) penetrating through the Bragg reflection layer (9) are respectively formed by etching at the positions, corresponding to the P electrode (7) and the N electrode (8), on the Bragg reflection layer (9);
step S5, manufacturing P welding layer (10) and N welding layer (11)
After the Bragg reflection layer (9) in the step S4 is pretreated, a P welding layer (10) connected with the P electrode (7) and an N welding layer (11) connected with the N electrode (8) are respectively plated on the Bragg reflection layer (9); then, the excessive metal of the P welding layer (10) and the N welding layer (11) is removed by a metal stripping method.
5. The production method according to claim 4, wherein the etching in step S1, step S2 and step S4 are all ICP etching.
6. The manufacturing method according to claim 5, wherein in step S1, the etching process parameters are: ICP power is 300-800W, RF power is 50-150W, cavity pressure is 3-8mtorr, BCl3Flow rate of 5-20sccm, Cl2The flow rate is 30-100sccm, and the etching time is 10-15 min.
7. The method of claim 5, wherein in step S2, the etching is performedThe technological parameters of etching are as follows: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 30-45 min.
8. The manufacturing method according to claim 5, wherein in step S4, the etching process parameters are: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, CF4The flow rate is 80-120sccm, O2The flow rate is 16-24sccm, and the etching time is 30-45 min.
9. The production method according to claim 5, wherein the pretreatment in steps S1-S5 each include the steps of spin coating, soft baking, exposing, developing and hardening the pretreatment object in each step, and then copying the pattern on the reticle onto the surface of the pretreatment object; the photoresist is uniformly coated on the surface of the pretreatment object.
10. The method of claim 5, wherein the steps S1-S5 each include a post-treatment, and the post-treatment includes immersing the product prepared in the steps S1-S5 in a degumming solution for 12-18min, washing off the photoresist on the surface of the product, and spin-drying the product with water.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116169226A (en) * | 2022-12-08 | 2023-05-26 | 江西兆驰半导体有限公司 | Etching method for Bragg reflection layer through hole in flip LED chip |
| CN116825926A (en) * | 2023-04-26 | 2023-09-29 | 江西兆驰半导体有限公司 | High-yield flip LED chip and preparation method thereof |
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| US20110018022A1 (en) * | 2008-03-13 | 2011-01-27 | Okabe Takehiko | Semiconductor light-emitting device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116169226A (en) * | 2022-12-08 | 2023-05-26 | 江西兆驰半导体有限公司 | Etching method for Bragg reflection layer through hole in flip LED chip |
| CN116169226B (en) * | 2022-12-08 | 2024-05-14 | 江西兆驰半导体有限公司 | Etching method for Bragg reflection layer through hole in flip LED chip |
| CN116825926A (en) * | 2023-04-26 | 2023-09-29 | 江西兆驰半导体有限公司 | High-yield flip LED chip and preparation method thereof |
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