CN113834827B - Multilayer circuit board and offset detection method thereof - Google Patents
Multilayer circuit board and offset detection method thereof Download PDFInfo
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- CN113834827B CN113834827B CN202010590110.3A CN202010590110A CN113834827B CN 113834827 B CN113834827 B CN 113834827B CN 202010590110 A CN202010590110 A CN 202010590110A CN 113834827 B CN113834827 B CN 113834827B
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- 238000001514 detection method Methods 0.000 title claims abstract description 39
- 238000012544 monitoring process Methods 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000007747 plating Methods 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims description 109
- 239000002184 metal Substances 0.000 claims description 109
- 238000000034 method Methods 0.000 claims description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 238000005538 encapsulation Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011889 copper foil Substances 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000003086 colorant Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 4
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N21/95607—Inspecting patterns on the surface of objects using a comparative method
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N2021/95638—Inspecting patterns on the surface of objects for PCB's
- G01N2021/95661—Inspecting patterns on the surface of objects for PCB's for leads, e.g. position, curvature
- G01N2021/95669—Inspecting patterns on the surface of objects for PCB's for leads, e.g. position, curvature for solder coating, coverage
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- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a multilayer circuit substrate and an offset detection method thereof, wherein the offset detection method comprises the following steps: forming a first circuit layer including a first monitor pattern; forming a second circuit layer comprising a second monitoring pattern on the first circuit layer, wherein one of the first monitoring pattern and the second monitoring pattern at least comprises a conductive pattern, and the other one of the first monitoring pattern and the second monitoring pattern at least comprises a reference pattern; conducting the conductive pattern to form a plating layer on the surface of the conductive pattern; judging whether a plating layer exists on the surface of the reference pattern, if so, judging that the reference pattern is deviated to be communicated with the conductive pattern, and if not, judging that the deviation between the first circuit layer and the second circuit layer exceeds a preset value. According to the invention, whether the offset between the multi-layer circuit layers exceeds the preset value is judged by observing whether the surface of the reference pattern is provided with the electroplated layer or not, so that whether the multi-layer circuit substrate is a qualified product is judged, the offset monitoring flow is greatly simplified, and the yield of the client product is greatly improved.
Description
Technical Field
The present invention relates to the field of packaging technologies, and in particular, to a multilayer circuit board and an offset detection method thereof.
Background
A pre-encapsulated substrate, or MIS substrate (Molded Interconnect Substrate molded interconnect substrate), is a package carrier that includes pre-encapsulated multi-layer wiring layers.
Compared with the conventional QFN frame, the pre-packaged substrate has superior winding capability, and can coil the welding wires near the chip, so that the difficulty of the welding wires is reduced, and even the impossible winding of the QFN frame can be completed.
The unique design of the pre-encapsulated substrate brings about the advantages of the pre-encapsulated substrate, and at the same time, the problem is not neglected, namely, the monitoring of the offset among the multiple circuit layers is not realized, because the internal structure of the pre-encapsulated substrate is covered by the encapsulating material, the front circuit layer and the back circuit layer can only see the corresponding patterns, and whether the relative displacement among the multiple circuit layers exceeds the preset value or not is not monitored.
In the prior art, the offset is monitored through the capability setting of the operation machine, however, the machine monitors theoretical conditions, when abnormal conditions occur, the offset actually produced may be greatly different from a preset value, and the result obtained by the machine detection becomes unreliable at the moment, so that some inferior products can flow into the client side, and the quality problem of the client product is caused.
Disclosure of Invention
The invention provides a multilayer circuit board and an offset detection method thereof.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for detecting a displacement of a multilayer circuit board, comprising:
forming a first circuit layer including a first monitor pattern;
forming a second circuit layer comprising a second monitoring pattern on the first circuit layer, wherein one of the first monitoring pattern and the second monitoring pattern at least comprises a conductive pattern, and the other one of the first monitoring pattern and the second monitoring pattern at least comprises a reference pattern;
conducting the conductive pattern to form a plating layer on the surface of the conductive pattern;
judging whether a plating layer exists on the surface of the reference pattern, if so, judging that the reference pattern is deviated to be communicated with the conductive pattern, and judging that the deviation between the first circuit layer and the second circuit layer exceeds a preset value, and if not, judging that the deviation between the first circuit layer and the second circuit layer does not exceed the preset value.
As a further improvement of an embodiment of the present invention, the first monitoring pattern includes at least a first conductive pattern, and the second monitoring pattern includes at least a second reference pattern.
As a further improvement of an embodiment of the present invention, the first monitor pattern includes a first reference pattern and the first conductive pattern disposed around the first reference pattern, the first reference pattern is disposed at a distance from the first conductive pattern, and the second monitor pattern includes at least a second reference pattern that conducts the first reference pattern.
As a further improvement of an embodiment of the present invention, the second monitor pattern further includes a second conductive pattern disposed around the second reference pattern, the second reference pattern being spaced apart from the second conductive pattern, and the second conductive pattern conducting the first conductive pattern.
As a further improvement of an embodiment of the present invention, the step of "turning on the conductive pattern to form a plating layer on the surface of the conductive pattern" further includes the step of:
and forming a third circuit layer comprising a third monitoring pattern on the second circuit layer, wherein the third monitoring pattern comprises a third reference pattern and a third conductive pattern arranged around the third reference pattern, the third reference pattern and the third conductive pattern are arranged at intervals, the third reference pattern is communicated with the second reference pattern, and the third conductive pattern is communicated with the second conductive pattern.
As a further improvement of an embodiment of the present invention, the step of forming a first circuit layer including a first monitor pattern; forming a second circuit layer comprising a second monitoring pattern on the first circuit layer, wherein one of the first monitoring pattern and the second monitoring pattern at least comprises a conductive pattern, and the other one of the first monitoring pattern and the second monitoring pattern at least comprises a reference pattern; the forming of the plating layer on the surface of the conductive pattern by conducting the conductive pattern includes:
forming a first circuit layer on a metal carrier, wherein the first circuit layer comprises a first metal circuit positioned in a functional area and a first monitoring pattern positioned in a non-functional area, and the first monitoring pattern at least comprises a first conductive pattern;
forming a second circuit layer on the first circuit layer, wherein the second circuit layer comprises a second metal circuit which is positioned in a functional area and is communicated with the first metal circuit and a second monitoring pattern which is positioned in a non-functional area, and the second monitoring pattern at least comprises a second reference pattern;
forming an encapsulation layer which encapsulates the first circuit layer and the second circuit layer and is connected with the metal carrier;
grinding the encapsulation layer to expose the surface of the second circuit layer;
Etching part of the metal carrier to expose the surface of the first circuit layer, and conducting the first conductive pattern and the first metal circuit by the rest of the metal carrier;
and conducting the metal carrier in a metal electroplating pool to form electroplated layers on the exposed surfaces of the first conductive pattern and the second conductive pattern, the surface of the first metal circuit and the surface of the second metal circuit.
As a further improvement of an embodiment of the present invention, the step of forming a first circuit layer on the metal carrier; forming a second circuit layer on the first circuit layer specifically includes:
plating copper foil on all surfaces of the metal substrate to form a metal carrier;
attaching a first photoresist film on the upper surface and the lower surface opposite to the metal carrier;
forming a first through hole at a first photoresist film on the upper surface of the metal carrier through an exposure and development process;
plating metal in the first through hole to form a first circuit layer;
attaching a second photoresist film on the first circuit layer and the first photoresist film on the upper surface of the metal carrier;
forming a second through hole at the second photoresist film through an exposure and development process;
plating metal in the second through hole to form a second circuit layer;
Removing the first photoresist film and the second photoresist film.
As a further improvement of an embodiment of the present invention, the step of forming the first circuit layer on the metal carrier specifically includes:
plating copper foil on all surfaces of the metal substrate to form a metal carrier;
attaching a third photoresist film on the lower surface of the metal carrier, and forming a metal film on the upper surface of the metal carrier;
attaching a fourth photoresist film on the metal film;
forming a third through hole at the fourth photoresist film through an exposure and development process;
removing the metal film exposed by the third through hole through an etching process, and forming the first circuit layer by the remaining metal film;
and removing the third photoresist film and the fourth photoresist film.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for detecting a displacement of a multilayer circuit board, comprising:
forming a multilayer circuit substrate comprising a plurality of circuit layers stacked in sequence, wherein an offset detection area is formed in the plurality of circuit layers, and the offset detection area at least comprises reference patterns and conductive patterns which are positioned on different layers;
conducting the conductive pattern to form a plating layer on the surface of the conductive pattern;
Judging whether a plating layer exists on the surface of the reference pattern, if so, judging that the reference pattern is deviated to be communicated with the conductive pattern, and judging that the deviation between the multi-layer circuit layers exceeds a preset value, and if not, judging that the deviation between the multi-layer circuit layers does not exceed the preset value.
As a further improvement of an embodiment of the present invention, the step of forming a multilayer circuit substrate including sequentially stacked multilayer wiring layers having an offset detection region formed therein, the offset detection region including at least a reference pattern and a conductive pattern at different layers specifically includes:
forming a first circuit layer comprising a first monitoring pattern, wherein the first monitoring pattern at least comprises a first conductive pattern;
and forming a second circuit layer comprising a second monitoring pattern on the first circuit layer, wherein the second monitoring pattern at least comprises a second reference pattern.
As a further improvement of an embodiment of the present invention, the first monitor pattern includes a first reference pattern and the first conductive pattern disposed around the first reference pattern, the first reference pattern is disposed at a distance from the first conductive pattern, and the second monitor pattern includes at least a second reference pattern that conducts the first reference pattern.
As a further improvement of an embodiment of the present invention, the second monitor pattern further includes a second conductive pattern disposed around the second reference pattern, the second reference pattern being spaced apart from the second conductive pattern, and the second conductive pattern conducting the first conductive pattern.
In order to achieve one of the above objects, an embodiment of the present invention provides a multi-layered circuit substrate, including a plurality of circuit layers stacked in order, a shift detection area formed by the plurality of circuit layers, and a plating layer, wherein the shift detection area includes at least a reference pattern and a conductive pattern on different layers, the plating layer covers the reference pattern and the conductive pattern when the reference pattern is shifted to turn on the conductive pattern, and the plating layer covers the conductive pattern when the reference pattern and the conductive pattern are spaced apart from each other.
As a further improvement of an embodiment of the present invention, the multilayer circuit substrate includes a first circuit layer and a second circuit layer stacked in sequence, the first circuit layer includes a first monitor pattern, the first monitor pattern includes at least a first conductive pattern, the second circuit layer includes a second monitor pattern, and the second monitor pattern includes at least a second reference pattern.
As a further improvement of an embodiment of the present invention, the first monitor pattern includes a first reference pattern and the first conductive pattern disposed around the first reference pattern, the first reference pattern is disposed at a distance from the first conductive pattern, and the second monitor pattern includes at least a second reference pattern that conducts the first reference pattern.
As a further improvement of an embodiment of the present invention, the second monitor pattern further includes a second conductive pattern disposed around the second reference pattern, the second reference pattern being spaced apart from the second conductive pattern, and the second conductive pattern conducting the first conductive pattern.
As a further improvement of an embodiment of the present invention, the multilayer circuit substrate includes a functional area and a nonfunctional area, the sequentially stacked metal layers formed by the multilayer circuit layers are located in the functional area, and the offset detection area is located in the nonfunctional area.
As a further improvement of an embodiment of the present invention, the multilayer circuit substrate further includes an encapsulation layer encapsulating the multilayer wiring layer, and the exposed portion of the multilayer metal layer is covered with the plating layer.
Compared with the prior art, the invention has the beneficial effects that: according to the embodiment of the invention, the electroplated layer is positioned in the visible area of the multilayer circuit substrate, whether the offset between the multilayer circuit layers exceeds a preset value can be judged by observing whether the electroplated layer is arranged on the surface of the reference pattern, so that whether the corresponding multilayer circuit substrate is a qualified product can be judged, the offset monitoring flow is greatly simplified, the accuracy and the reliability of offset detection are greatly improved, and the yield of the client product can be greatly improved.
Drawings
FIG. 1 is a top view of a multilayer circuit substrate according to an embodiment of the present invention;
fig. 2a is a cross-sectional view of the shift detection region S in the first specific example of the present invention (the shift amount does not exceed a preset value);
fig. 2b is a cross-sectional view of the shift detection region S (the shift amount exceeds a preset value) in the first specific example of the present invention;
FIG. 3 is a schematic view of a vertical projection of a reference pattern and a conductive pattern in a first embodiment of the present invention;
fig. 4a is a cross-sectional view of the shift detection region S in the second specific example of the present invention (the shift amount does not exceed the preset value);
fig. 4b is a cross-sectional view of the shift detection region S (the shift amount exceeds a preset value) in the second specific example of the present invention;
Fig. 5a is a cross-sectional view of an offset detection area S (the offset amount does not exceed a preset value) in a third specific example of the present invention;
fig. 5b is a cross-sectional view of the shift detection region S (the shift amount exceeds a preset value) in the third specific example of the present invention;
fig. 6a is a cross-sectional view of an offset detection area S (the offset amount does not exceed a preset value) in a fourth specific example of the present invention;
fig. 6b is a cross-sectional view of the shift detection region S (the shift amount exceeds a preset value) in a fourth specific example of the present invention;
fig. 7 is a step diagram of a method for detecting offset of a multilayer circuit board according to an embodiment of the present invention;
fig. 8 is a step diagram of a method of detecting displacement of the multilayer circuit substrate according to the third specific example;
fig. 9 to 23 are schematic diagrams of a method of detecting a shift of a multilayer circuit substrate corresponding to a third specific example.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
In the various illustrations of the invention, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for convenience of illustration, and thus serve only to illustrate the basic structure of the inventive subject matter.
Fig. 1, fig. 2a, fig. 2b are schematic views of a multi-layer circuit substrate 100 according to an embodiment of the present invention.
The multilayer circuit board 100 includes multilayer wiring layers 10, 11, an offset detection region S formed of the multilayer wiring layers 10, 11, and a plating layer 20 stacked in this order.
Here, the multilayer circuit substrate 100 is a pre-encapsulation substrate, and the "multilayer wiring layer" means that the multilayer circuit substrate 100 includes two or more wiring layers, and the plating layer 20 is located in an upper region or a lower region of the finally formed multilayer circuit substrate 100, that is, the plating layer 20 is located in a visible region.
The offset detection region S includes at least the reference pattern 112 and the conductive pattern 101 in different layers, and when the reference pattern 112 is offset to turn on the conductive pattern 101, the plating layer 20 covers the reference pattern 112 and the conductive pattern 101, and when the reference pattern 112 and the conductive pattern 101 are spaced apart from each other, the plating layer 20 covers the conductive pattern 101.
Here, the reference pattern 112 and the conductive pattern 101 are located at different wiring layers, and in a normal case (i.e., the offset between the multi-layered wiring layers 10, 11 does not exceed a preset value), the reference pattern 112 and the conductive pattern 101 are spaced apart from each other.
In the process of forming the multilayer circuit substrate 100, a plating process is included, which means that a multilayer circuit board formed by stacking is placed in a metal plating bath containing metal ions, and the conductive pattern 101 is energized, and then the metal ions are deposited on the surface of the energized conductive pattern 101 to form the plating layer 20.
Referring to fig. 2a, when the reference pattern 112 and the conductive pattern 101 are spaced apart from each other, only the conductive pattern 101 is in the energized state in the electroplating process, and the electroplated layer 20 only covers the conductive pattern 101, at this time, it is determined that the offset between the multilayer circuit layers 10 and 11 does not exceed the preset value, and the corresponding multilayer circuit substrate 100 is a qualified product.
Referring to fig. 2b, when the reference pattern 112 is shifted to the conductive pattern 101, the reference pattern 112 and the conductive pattern 101 are both in the conductive state in the electroplating process, and the electroplated layer 20 covers both the reference pattern 112 and the conductive pattern 101, at this time, it is determined that the shift amount between the multilayer circuit layers 10 and 11 exceeds the preset value, and the corresponding multilayer circuit substrate 100 is a defective product.
In other words, the offset detection area S is added in this embodiment, since the electroplated layer 20 is located in the visible area of the finally formed multi-layer circuit substrate 100, whether the offset between the multi-layer circuit layers exceeds the preset value can be determined by observing whether the electroplated layer 20 is located on the surface of the reference pattern 112, so as to determine whether the corresponding multi-layer circuit substrate 100 is a qualified product, thereby greatly simplifying the offset monitoring process and greatly improving the product yield.
The metal ions forming the plating layer 20 may be nickel gold, nickel palladium gold, tin, silver, or the like, and preferably have a metal color that greatly differs from the color of the reference pattern 112 or the conductive pattern 101.
In the present embodiment, the multilayer circuit board 100 includes a functional region P1 and a nonfunctional region P2, and the multilayer metal layer 30 formed by stacking the multilayer wiring layers 10 and 11 in order is located in the functional region P1, and the offset detection region S is located in the nonfunctional region P2.
Here, the functional region P1 is defined as an effective pattern region, i.e., a product region, of the multi-layer circuit substrate 100 that actually performs a signal transmission function and a carrying function, and the non-functional region P2 is defined as other non-effective pattern regions, i.e., non-product regions, of the multi-layer circuit substrate 100 other than the effective pattern region.
The functional region P1 is generally a middle region of the multi-layer circuit substrate 100, the non-functional region P2 is generally an edge region of the multi-layer circuit substrate 100, and each circuit layer includes a metal layer 30 located in the functional region P1, and a reference pattern 112 and/or a conductive pattern 101 located in the non-functional region P2.
It can be understood that, for each circuit layer, the pattern of the non-functional area P2 and the pattern of the functional area P1 are formed together, and the relative positions of the pattern of the non-functional area P2 and the pattern of the functional area P1 are fixed, when the offset of the pattern of the non-functional area P2 (including the reference pattern 112 and the conductive pattern 101) in the multi-layer circuit layer exceeds a preset value, the offset of the pattern of the corresponding functional area P1 also exceeds the preset value, that is, only the offset of the pattern of the reference offset detection area S exceeds the preset value, it can be determined whether the offset between the multi-layer metal layers 30 of the functional area P1 exceeds the preset value, and when the offset between the multi-layer metal layers 30 exceeds the preset value, there is a problem of connection disorder or disconnection between the multi-layer metal layers 30, that is, the multi-layer circuit substrate 100 is a defective product.
In addition, the exposed portions of the multi-layered metal layer 30 are also covered with the plating layer 20, i.e., the metal layer 30 located in the upper and lower regions of the multi-layered circuit substrate 100 is also covered with the plating layer 20, and the plating layer 20 can play an anti-oxidation role for exposed pattern portions.
The multi-layered circuit substrate 100 further includes an encapsulation layer 40 encapsulating the multi-layered circuit layers 10, 11, the encapsulation layer 40 encapsulating the metal layer 30, the reference pattern 112, and/or the edge region and the intermediate gap of the conductive pattern 101.
The multilayer circuit substrate 100 of the present embodiment is described below in a plurality of specific examples.
In a first specific example, referring to fig. 2a, 2b and 3, the multi-layer circuit substrate 100 includes a first circuit layer 10 and a second circuit layer 11 stacked in sequence, and the second circuit layer 11 is located above the first circuit layer 10.
The first circuit layer 10 includes a first monitoring pattern F1, the first monitoring pattern F1 including at least a first conductive pattern 101, and the first monitoring pattern F1 here includes only the first conductive pattern 101.
The second wiring layer 11 includes a second monitoring pattern F2, and the second monitoring pattern F2 includes at least a second reference pattern 112, and the second monitoring pattern F2 includes only the second reference pattern 112.
Fig. 3 illustrates a top view of the first conductive pattern 101 and the second reference pattern 112, that is, illustrates that the first conductive pattern 101 and the second reference pattern 112 are vertically projected onto the same plane, the first conductive pattern 101 is annular, may be hollow square or hollow circular, the second reference pattern 112 is an independent solid pattern, may be square or circular, and the like, the first conductive pattern 101 and the second reference pattern 112 are both center symmetrical patterns, when no offset occurs between the first circuit layer 10 and the second circuit layer 11, the vertical projection of the center of the first conductive pattern 101 and the center of the second reference pattern 112 coincides, and the distance between the vertical projections of the first conductive pattern 101 and the second reference pattern 112 is L, which is the maximum allowable offset (i.e., a preset value) between the first circuit layer 10 and the second circuit layer 11, so that any directional offset between the first circuit layer 10 and the second circuit layer 11 can be monitored.
When the offset of the second monitor pattern F2 relative to the first monitor pattern F1 does not exceed the distance L with reference to the first monitor pattern F1 in the first circuit layer 10, the second reference pattern 112 does not contact the first conductive pattern 101 in conjunction with fig. 2a, and the plating layer 20 covers only the first conductive pattern 101; when the offset of the second monitor pattern F2 relative to the first monitor pattern F1 exceeds the distance L, referring to fig. 2b, the second reference pattern 112 contacts the first conductive pattern 101 such that the plating layer 20 covers both the second reference pattern 112 and the first conductive pattern 101.
Referring to fig. 4a and fig. 4b, which are schematic diagrams of a multi-layer circuit substrate 100a of a second embodiment, structures similar to or identical to those of the first embodiment are denoted by similar or identical numerals, and other embodiments are not repeated herein.
The multi-layered circuit substrate 100a includes a first wiring layer 10a and a second wiring layer 11a stacked in order.
The first circuit layer 10a includes a first monitor pattern F1, the first monitor pattern F1 includes a first reference pattern 102a and a first conductive pattern 101a disposed around the first reference pattern 102a, and the first reference pattern 102a is spaced apart from the first conductive pattern 101 a.
The second circuit layer 11a includes a second monitor pattern F2, and the second monitor pattern F2 includes at least a second reference pattern 112a that conducts the first reference pattern 102a, where the second monitor pattern F2 includes only the second reference pattern 112a.
Here, the first reference pattern 102a and the second reference pattern 112a are solid patterns which are the same in size and are independent, the first conductive pattern 101a is annular, and referring to the description of the first specific example, when no offset occurs between the first wiring layer 10a and the second wiring layer 11a, the first reference pattern 102a and the second reference pattern 112a overlap each other and are conductive each other, and the vertical projections of the centers of the respective patterns coincide, and the pitches between the vertical projections of the first conductive pattern 101a and the first reference pattern 102a are L, so that any directional offset between the first wiring layer 10a and the second wiring layer 11a can be monitored.
When the offset of the second monitor pattern F2 relative to the first monitor pattern F1 does not exceed the distance L with reference to the first monitor pattern F1 in the first circuit layer 10a, the second reference pattern 112a does not contact the first conductive pattern 101a in conjunction with fig. 4a, and the plating layer 20a covers only the first conductive pattern 101a; when the offset of the second monitor pattern F2 with respect to the first monitor pattern F1 exceeds the distance L, referring to fig. 4b, the second reference pattern 112a contacts the first conductive pattern 101a such that the plating layer 20a covers the second reference pattern 112a, the first conductive pattern 101a and the first reference pattern 102a at the same time.
Fig. 5a and 5b are schematic views of a multilayer circuit substrate 100b according to a third specific example.
The multilayer circuit substrate 100b includes a first wiring layer 10b and a second wiring layer 11b stacked in order.
The first circuit layer 10b includes a first monitor pattern F1, the first monitor pattern F1 includes a first reference pattern 102b and a first conductive pattern 101b disposed around the first reference pattern 102b, and the first reference pattern 102b is disposed at a distance from the first conductive pattern 101 b.
The second circuit layer 11b includes a second monitor pattern F2, the second monitor pattern F2 includes a second reference pattern 112b and a second conductive pattern 111b disposed around the second reference pattern 112b, and the second reference pattern 112b is spaced apart from the second conductive pattern 111b.
The first reference pattern 102b turns on the second reference pattern 112b, and the first conductive pattern 101b turns on the second conductive pattern 111b.
Here, the first reference pattern 102b and the second reference pattern 112b are solid patterns having the same size and being independent, the first conductive pattern 101b and the second conductive pattern 111b are ring-shaped, and when no offset occurs between the first circuit layer 10b and the second circuit layer 11b, the first reference pattern 102b and the second reference pattern 112b overlap each other and are conductive each other, the first conductive pattern 101b and the second conductive pattern 111b overlap each other and are conductive each other, the vertical projections of the centers of the respective patterns coincide, and the pitches between the conductive patterns and the corresponding reference patterns are L, so that any directional offset between the first circuit layer 10b and the second circuit layer 11b can be monitored.
When the offset of the second monitor pattern F2 relative to the first monitor pattern F1 does not exceed the distance L with reference to the first monitor pattern F1 in the first circuit layer 10b, the second reference pattern 112b does not contact the first conductive pattern 101b in conjunction with fig. 5a, and the plating layer 20b covers only the first conductive pattern 101b and the second conductive pattern 111b; when the offset of the second monitor pattern F2 with respect to the first monitor pattern F1 exceeds the distance L, referring to fig. 5b, the second reference pattern 112b contacts the first conductive pattern 101b such that the plating layer 20b covers the second reference pattern 112b, the second conductive pattern 111b, the first reference pattern 102b and the first conductive pattern 101b at the same time.
Fig. 6a and 6b are schematic diagrams of a fourth specific example of the multilayer circuit substrate 100 c.
The multilayer circuit substrate 100c includes a first wiring layer 10c, a second wiring layer 11c, a third wiring layer 12c, and a fourth wiring layer 13c stacked in this order.
The first circuit layer 10c includes a first monitor pattern F1, the first monitor pattern F1 includes a first reference pattern 102c and a first conductive pattern 101c disposed around the first reference pattern 102c, and the first reference pattern 102c is spaced apart from the first conductive pattern 101 c.
The second circuit layer 11c includes a second monitor pattern F2, the second monitor pattern F2 includes a second reference pattern 112c and a second conductive pattern 111c disposed around the second reference pattern 112c, and the second reference pattern 112c is spaced apart from the second conductive pattern 111 c.
The third circuit layer 12c includes a third monitoring pattern F3, the third monitoring pattern F3 includes a third reference pattern 122c and a third conductive pattern 121c disposed around the third reference pattern 122c, and the third reference pattern 122c is disposed at a distance from the third conductive pattern 121 c.
The fourth circuit layer 13c includes a fourth monitoring pattern F4, the fourth monitoring pattern F4 includes a fourth reference pattern 132c and a fourth conductive pattern 131c disposed around the fourth reference pattern 132c, and the fourth reference pattern 132c is spaced apart from the fourth conductive pattern 131 c.
The first, second, third and fourth conductive patterns 101c, 111c, 121c and 131c are sequentially stacked and are conductive to each other, and the first, second, third and fourth reference patterns 102c, 112c, 122c and 132c are sequentially stacked and are conductive to each other.
Here, when the first reference pattern 102c, the second reference pattern 112c, the third reference pattern 122c, and the fourth reference pattern 132c are solid patterns having the same size and being independent of each other, the first conductive pattern 101c, the second conductive pattern 111c, the third conductive pattern 121c, and the fourth conductive pattern 131c are solid patterns having the same size and being circular, and the first specific example is described with reference to the first specific example, when no offset occurs between the first wiring layer 10c, the second wiring layer 11c, the third wiring layer 12c, and the fourth wiring layer 13c, the first reference pattern 102c, the second reference pattern 112c, the third reference pattern 122c, and the fourth reference pattern 132c overlap each other and are conductive with each other, the first conductive pattern 101c, the second conductive pattern 111c, the third conductive pattern 121c, and the fourth conductive pattern 131c overlap each other and are conductive with each other, and the vertical projections of the centers of the respective patterns overlap each other, and the distances between each conductive pattern and the corresponding reference patterns are L, so that any one of the line layer 10c, the second wiring layer 11c, the third wiring layer 12c, and the fourth wiring layer 13c can be monitored for offset in any direction.
When the offset amounts of the second monitor pattern F2, the third monitor pattern F3 and the fourth monitor pattern F4 relative to the first monitor pattern F1 do not exceed the distance L with reference to the first monitor pattern F1 in the first circuit layer 10c, referring to fig. 6a, none of the second reference pattern 112c, the third reference pattern 122c and the fourth reference pattern 132c contacts the first conductive pattern 101c, and the plating layer 20c only covers the first conductive pattern 101c and the fourth conductive pattern 131c; when the offset of at least one of the second, third and fourth monitoring patterns F2, F3 and F4 relative to the first monitoring pattern F1 exceeds the distance L, referring to fig. 6b, the offset of the second and third monitoring patterns F2 and F3 relative to the first monitoring pattern F1 exceeds the distance L, and the second and third reference patterns 112c and 122c contact the first conductive pattern 101c such that the plating layer 20c covers the fourth reference pattern 132c, the fourth conductive pattern 131c, the first reference pattern 102c and the first conductive pattern 101c at the same time.
Of course, the number of circuit layers included in the multilayer circuit board 100 is not limited to the above description.
An embodiment of the present invention further provides a method for detecting a misalignment of a multilayer circuit board 100, and the method for detecting a misalignment of a multilayer circuit board 100 includes the steps of:
Forming a multilayer circuit substrate 100 including a plurality of circuit layers 10, 11 stacked in order, the plurality of circuit layers 10, 11 having an offset detection region S formed therein, the offset detection region S including at least a reference pattern 112 and a conductive pattern 101 at different layers;
the method comprises the following steps: forming a first wiring layer 10 including a first monitoring pattern F1, the first monitoring pattern F1 including at least a first conductive pattern 101; a second circuit layer 11 including a second monitor pattern F2 is formed on the first circuit layer 10, the second monitor pattern F2 includes at least a second reference pattern 112, and the offset detection region S includes a first monitor pattern F1 and a second monitor pattern F2.
Conducting the conductive pattern 101 to form a plating layer 20 on the surface of the conductive pattern 101;
whether the reference pattern 112 has the plating layer 20 is determined, if so, the reference pattern 112 is determined to communicate with the conductive pattern 101, and if not, the offset between the multilayer wiring layers 10, 11 exceeds a preset value, and if not, the offset between the multilayer wiring layers 10, 11 does not exceed the preset value.
Here, the number of layers of the wiring layers included in the multilayer circuit substrate 100 is not limited, and the pattern included in each wiring layer at the shift detection region S is also not limited.
Taking the structure of the multilayer circuit board 100b of the third specific example as an example, the offset detection method includes the steps of:
S1: referring to fig. 9 to 12, a first wiring layer 10b including a first monitoring pattern F1 is formed;
s3: referring to fig. 13 to 15, a second circuit layer 11b including a second monitor pattern F2 is formed on the first circuit layer 10b, wherein one of the first monitor pattern F1 and the second monitor pattern F2 includes at least conductive patterns 101b, 111b, and the other includes at least reference patterns 102b, 112b;
here, the multilayer circuit board 100b includes a first wiring layer 10b and a second wiring layer 11b stacked in this order as an example.
The first monitoring pattern F1 and the second monitoring pattern F2 have various forms, and referring to the foregoing specific example, in the first specific example, the first monitoring pattern F1 includes the first conductive pattern 101, and the second monitoring pattern F2 includes the second reference pattern 112; in the second specific example, the first monitoring pattern F1 includes a first reference pattern 102a and a first conductive pattern 101a disposed around the first reference pattern 102a, the first reference pattern 102a being spaced apart from the first conductive pattern 101a, and the second monitoring pattern F2 includes a second reference pattern 112a that turns on the first reference pattern 102 a; in the third specific example, the first monitor pattern F1 includes a first reference pattern 102b and a first conductive pattern 101b disposed around the first reference pattern 102b, the first reference pattern 102b is disposed at a distance from the first conductive pattern 101b, the second monitor pattern F2 includes a second reference pattern 112b and a second conductive pattern 111b disposed around the second reference pattern 112b, the second reference pattern 112b is disposed at a distance from the second conductive pattern 111b, the first reference pattern 102b turns on the second reference pattern 112b, and the first conductive pattern 101b turns on the second conductive pattern 111b, here taking the third specific example as an example.
The steps S1 and S3 specifically include:
s1: referring to fig. 9 to 12, a first circuit layer 10b is formed on the metal carrier 50b, the first circuit layer 10b includes a first metal circuit located in the functional area P1 and a first monitoring pattern F1 located in the non-functional area P2, and the first monitoring pattern F1 includes at least a first conductive pattern 101b;
here, the first metal circuit and the first monitoring pattern F1 are formed together, and the first monitoring pattern F1 includes a first reference pattern 102b and a first conductive pattern 101b disposed around the first reference pattern 102 b.
S3: referring to fig. 13 to 15, a second circuit layer 11b is formed on the first circuit layer 10b, the second circuit layer 11b includes a second metal circuit located in the functional area P1 and electrically connected to the first metal circuit, and a second monitor pattern F2 located in the non-functional area P2, and the second monitor pattern F2 includes at least a second reference pattern 112b;
here, the second metal circuit is formed together with the second monitoring pattern F2, and the second monitoring pattern F2 includes a second reference pattern 112b and a second conductive pattern 111b disposed around the second reference pattern 112 b.
In the present embodiment, the molding method of the first wiring layer 10b and the second wiring layer 11b in steps S1 and S3 specifically includes:
referring to fig. 9 and 10, copper foil 51b is plated on all surfaces of a metal substrate 60b to form a metal carrier 50b;
Referring to fig. 11, a first photoresist film 70b is attached to the opposite upper and lower surfaces of the metal carrier 50 b;
forming a first through hole 71b at the first photoresist film 70b of the upper surface of the metal carrier 50b by an exposure developing process;
referring to fig. 12, a first circuit layer 10b is formed by plating metal in the first via hole 71b;
here, taking the first monitoring pattern F1 in the first wiring layer 10b as an example in fig. 12, the first monitoring pattern F1 includes a first reference pattern 102b and a first conductive pattern 101b disposed around the first reference pattern 102 b.
Referring to fig. 13, a second photoresist film 80b is attached to the first circuit layer 10b and the first photoresist film 70b on the upper surface of the metal carrier 50 b;
forming a second through hole 81b at the second photoresist film 80b by an exposure developing process;
referring to fig. 14, a second circuit layer 11b is formed by plating metal in the second via hole 81b;
here, taking the second monitoring pattern F2 in the second wiring layer 11b as an example in fig. 14, the second monitoring pattern F2 includes a second reference pattern 112b and a second conductive pattern 111b disposed around the second reference pattern 112 b.
Referring to fig. 15, the first photoresist film 70b and the second photoresist film 80b are removed.
In another embodiment, the molding method of the first circuit layer 10b and the second circuit layer 11b in steps S1 and S3 specifically includes:
Referring to fig. 16, copper foil 51b ' is plated on all surfaces of a metal substrate 60b ' to form a metal carrier 50b ';
attaching a third photoresist film 90b 'to the lower surface of the metal carrier 50b', and forming a metal film 92b 'on the upper surface of the metal carrier 50b';
attaching a fourth photoresist film 93b 'on the metal film 92b';
forming a third via hole 94b 'at the fourth photoresist film 93b' by an exposure developing process;
referring to fig. 17, the metal film 92b 'exposed from the third via hole 94b' is removed by an etching process, and the remaining metal film 92b 'forms the first circuit layer 10b';
referring to fig. 18, the third photoresist film 90b 'and the fourth photoresist film 93b' are removed.
It will be appreciated that the second wiring layer may then be formed by the same process.
S5: conducting the conductive pattern 101b to form a plating layer 20b on the surface of the conductive pattern 101 b;
the step S5 specifically comprises the following steps:
referring to fig. 19, an encapsulation layer 40b is formed to encapsulate the first circuit layer 10b and the second circuit layer 11b and connect the metal carrier 50 b;
referring to fig. 20, the encapsulation layer 40b is polished to expose the surface of the second circuit layer 11 b;
referring to fig. 21, a portion of the metal carrier 50b is etched to expose the surface of the first circuit layer 10b, and the remaining metal carrier 50b conducts the first conductive pattern 101b and the first metal circuit;
Referring to fig. 22 and 23, a metal carrier 50b is conducted by a conductive device 300 in a metal plating bath to form a plating layer 20b on the exposed surfaces of the first conductive pattern 101b and the second conductive pattern 111b, the surfaces of the first metal circuit and the surfaces of the second metal circuit.
S7: whether the plating layer 20b is present on the surfaces of the reference patterns 102b and 112b is determined, if so, the reference pattern 112b is determined to be shifted to the communication conductive pattern 101b, and if not, the shift amount between the first wiring layer 10b and the second wiring layer 11b exceeds a preset value, the shift amount between the first wiring layer 10b and the second wiring layer 11b is determined not to exceed the preset value.
Here, the difference between the color of the plating layer 20b and the first and second circuit layers 10b and 11b is large, it may be observed whether the plating layer 20b is present on the surfaces of the first and second reference patterns 102b and 112b after the plating process is completed, if so, it is determined that the amount of shift between the first and second circuit layers 10b and 11b exceeds a preset value, the resulting multilayer circuit substrate 100b is a defective product, and if not, it is determined that the amount of shift between the first and second circuit layers 10b and 11b does not exceed a preset value, and the resulting multilayer circuit substrate 100b is a defective product.
In the present embodiment, since the electroplated layer 20b is located in the visible area of the finally formed multilayer circuit substrate 100b, whether the offset between the multilayer circuit layers 10b and 11b exceeds the preset value can be determined by observing whether the electroplated layer 20b is located on the surfaces of the reference patterns 102b and 112b, so as to determine whether the corresponding multilayer circuit substrate 100 is a qualified product, thereby greatly simplifying the offset monitoring process and greatly improving the product yield.
In addition, the plating layer 20b for observation is directly formed in the original plating process without changing the original process and without increasing the cost.
In this embodiment, in combination with the description of the fourth specific example and the accompanying drawings, the step S5 may further include the steps of:
a third circuit layer 12c including a third monitor pattern F3 is formed on the second circuit layer 11c, the third monitor pattern F3 includes a third reference pattern 122c and a third conductive pattern 121c disposed around the third reference pattern 122c, the third reference pattern 122c is spaced apart from the third conductive pattern 121c, the third reference pattern 122c is conducted to the second reference pattern 112c, and the third conductive pattern 121c is conducted to the second conductive pattern 111c.
That is, when the multi-layer circuit substrate includes multiple circuit layers, the third circuit layer 12c may be formed on the basis of the two circuit layers, or the fourth circuit layer 13c may be formed continuously, and the forming process of the third circuit layer 12c and the fourth circuit layer 13c may be referred to the above description, which is not repeated here.
In summary, the offset detection area S is added in the present invention, since the electroplated layer 20 is located in the visible area of the finally formed multi-layer circuit substrate 100, whether the offset between the multi-layer circuit layers exceeds the preset value can be judged by observing whether the electroplated layer 20 is located on the surface of the reference pattern 112, so as to judge whether the corresponding multi-layer circuit substrate 100 is a qualified product, thereby greatly simplifying the offset monitoring process, greatly improving the accuracy and reliability of offset detection, and greatly improving the yield of the client product.
In addition, the plating layer 20 for observation is directly formed in the original plating process without changing the original process and without increasing the cost.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (7)
1. A method for detecting offset of a multilayer circuit board is characterized by comprising the steps of:
forming a first circuit layer comprising a first monitoring pattern, wherein the first monitoring pattern comprises a first reference pattern and a first conductive pattern arranged around the first reference pattern, and the first reference pattern and the first conductive pattern are arranged at intervals;
forming a second circuit layer comprising a second monitoring pattern on the first circuit layer, wherein the second monitoring pattern comprises a second reference pattern for conducting the first reference pattern and a second conductive pattern arranged around the second reference pattern, the second reference pattern and the second conductive pattern are arranged at intervals, and the second conductive pattern conducts the first conductive pattern; when no offset occurs between the first circuit layer and the second circuit layer, the first reference pattern and the second reference pattern are mutually overlapped and mutually conducted, the first conductive pattern and the second conductive pattern are mutually overlapped and mutually conducted, and the vertical projection of the centers of the patterns is overlapped;
conducting the first conductive pattern to form a plating layer on the surface of the first conductive pattern, wherein the color of the plating layer is different from the color of the first circuit layer and the second circuit layer;
Judging whether a plating layer exists on the surface of the second reference pattern, if so, judging that the second reference pattern is deviated to be communicated with the first conductive pattern, and judging that the deviation between the first circuit layer and the second circuit layer exceeds a preset value, if not, judging that the deviation between the first circuit layer and the second circuit layer does not exceed the preset value;
the multi-layer circuit substrate comprises a functional area and a nonfunctional area, the first circuit layer comprises a first metal circuit positioned in the functional area, a first reference pattern and a first conductive pattern positioned in the nonfunctional area, and the second circuit layer comprises a second metal circuit positioned in the functional area, a second reference pattern and a second conductive pattern positioned in the nonfunctional area; the first metal circuit and the first monitoring pattern are formed together, and the second metal circuit and the second monitoring pattern are formed together;
when the offset between the multi-layer circuit layers does not exceed a preset value, the second reference pattern and the first conductive pattern are spaced apart from each other; when the offset between the multi-layered circuit layers exceeds a preset value, the second reference pattern contacts the first conductive pattern.
2. The method of detecting offset according to claim 1, wherein before the step of turning on the first conductive pattern to form a plating layer on the surface of the first conductive pattern, further comprising the steps of:
and forming a third circuit layer comprising a third monitoring pattern on the second circuit layer, wherein the third monitoring pattern comprises a third reference pattern and a third conductive pattern arranged around the third reference pattern, the third reference pattern and the third conductive pattern are arranged at intervals, the third reference pattern is communicated with the second reference pattern, and the third conductive pattern is communicated with the second conductive pattern.
3. The method of offset detection according to claim 1, wherein the step of forming a first circuit layer including a first monitor pattern; forming a second circuit layer including a second monitor pattern on the first circuit layer, and conducting the first conductive pattern to form a plating layer on a surface of the first conductive pattern, specifically comprising:
forming a first circuit layer on a metal carrier, wherein the first circuit layer comprises a first metal circuit positioned in a functional area and a first monitoring pattern positioned in a non-functional area, and the first monitoring pattern comprises a first conductive pattern and a first reference pattern;
Forming a second circuit layer on the first circuit layer, wherein the second circuit layer comprises a second metal circuit which is positioned in a functional area and is communicated with the first metal circuit, and a second monitoring pattern which is positioned in a non-functional area, and the second monitoring pattern comprises a second conductive pattern and a second reference pattern;
forming an encapsulation layer which encapsulates the first circuit layer and the second circuit layer and is connected with the metal carrier;
grinding the encapsulation layer to expose the surface of the second circuit layer;
etching part of the metal carrier to expose the surface of the first circuit layer, and conducting the first conductive pattern and the first metal circuit by the rest of the metal carrier;
and conducting the metal carrier in a metal electroplating pool to form electroplated layers on the exposed surfaces of the first conductive pattern and the second conductive pattern, the surface of the first metal circuit and the surface of the second metal circuit.
4. The method of claim 3, wherein the step of forming a first circuit layer on the metal carrier; forming a second circuit layer on the first circuit layer specifically includes:
plating copper foil on all surfaces of the metal substrate to form a metal carrier;
Attaching a first photoresist film on the upper surface and the lower surface opposite to the metal carrier;
forming a first through hole at a first photoresist film on the upper surface of the metal carrier through an exposure and development process;
plating metal in the first through hole to form a first circuit layer;
attaching a second photoresist film on the first circuit layer and the first photoresist film on the upper surface of the metal carrier;
forming a second through hole at the second photoresist film through an exposure and development process;
plating metal in the second through hole to form a second circuit layer;
removing the first photoresist film and the second photoresist film.
5. The method of claim 3, wherein the step of forming a first circuit layer on the metal carrier comprises:
plating copper foil on all surfaces of the metal substrate to form a metal carrier;
attaching a third photoresist film on the lower surface of the metal carrier, and forming a metal film on the upper surface of the metal carrier;
attaching a fourth photoresist film on the metal film;
forming a third through hole at the fourth photoresist film through an exposure and development process;
removing the metal film exposed by the third through hole through an etching process, and forming the first circuit layer by the remaining metal film;
And removing the third photoresist film and the fourth photoresist film.
6. A multilayer circuit substrate, characterized in that the multilayer circuit substrate comprises a multilayer circuit layer, an offset detection area and a plating layer which are stacked in sequence, wherein the offset detection area is formed by the multilayer circuit layer and at least comprises reference patterns and conductive patterns which are positioned on different layers, when the reference patterns are offset to conduct the conductive patterns, the plating layer covers the reference patterns and the conductive patterns, and when the reference patterns and the conductive patterns are mutually separated, the plating layer covers the conductive patterns;
the multi-layer circuit substrate comprises a first circuit layer and a second circuit layer which are stacked in sequence, wherein the colors of the electroplated layers are different from those of the first circuit layer and the second circuit layer;
the first circuit layer comprises a first monitoring pattern, wherein the first monitoring pattern comprises a first reference pattern and a first conductive pattern arranged around the first reference pattern, and the first reference pattern and the first conductive pattern are arranged at intervals;
the second circuit layer comprises a second monitoring pattern, the second monitoring pattern comprises a second reference pattern for conducting the first reference pattern and a second conductive pattern arranged around the second reference pattern, the second reference pattern and the second conductive pattern are arranged at intervals, and the second conductive pattern conducts the first conductive pattern; when no offset occurs between the first circuit layer and the second circuit layer, the first reference pattern and the second reference pattern are mutually overlapped and mutually conducted, the first conductive pattern and the second conductive pattern are mutually overlapped and mutually conducted, and the vertical projection of the centers of the patterns is overlapped;
The multi-layer circuit substrate comprises a functional area and a nonfunctional area, wherein a plurality of metal layers which are formed by the multi-layer circuit layer and are stacked in sequence are positioned in the functional area, the offset detection area is positioned in the nonfunctional area, the reference pattern and the conductive pattern are positioned in different circuit layers, the first circuit layer comprises a first metal circuit positioned in the functional area, a first reference pattern and a first conductive pattern positioned in the nonfunctional area, and the second circuit layer comprises a second metal circuit positioned in the functional area, a second reference pattern and a second conductive pattern positioned in the nonfunctional area; the first metal circuit and the first monitoring pattern are formed together, and the second metal circuit and the second monitoring pattern are formed together;
when the offset between the multi-layer circuit layers does not exceed a preset value, the second reference pattern and the first conductive pattern are spaced apart from each other; when the offset between the multi-layered circuit layers exceeds a preset value, the second reference pattern contacts the first conductive pattern.
7. The multilayer circuit substrate of claim 6, further comprising an encapsulation layer encapsulating the multilayer wiring layer, the multilayer metal layer being covered with the plating layer at exposed portions thereof.
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