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CN113809792A - A kind of equalization circuit applied to CubeSat lithium battery pack - Google Patents

A kind of equalization circuit applied to CubeSat lithium battery pack Download PDF

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Publication number
CN113809792A
CN113809792A CN202110950408.5A CN202110950408A CN113809792A CN 113809792 A CN113809792 A CN 113809792A CN 202110950408 A CN202110950408 A CN 202110950408A CN 113809792 A CN113809792 A CN 113809792A
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resistor
pin
capacitor
output end
pole
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CN113809792B (en
Inventor
于永军
李�灿
廖文和
张翔
戴寿沈
侯黎明
刘堃
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014—Circuits for equalisation of charge between batteries
    • H02J7/0019—Circuits for equalisation of charge between batteries using switched or multiplexed charge circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64G—COSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
    • B64G1/00—Cosmonautic vehicles
    • B64G1/22—Parts of, or equipment specially adapted for fitting in or to, cosmonautic vehicles
    • B64G1/42—Arrangements or adaptations of power supply systems
    • B64G1/425—Power storage
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64G—COSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
    • B64G1/00—Cosmonautic vehicles
    • B64G1/22—Parts of, or equipment specially adapted for fitting in or to, cosmonautic vehicles
    • B64G1/42—Arrangements or adaptations of power supply systems
    • B64G1/428—Power distribution and management
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64G—COSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
    • B64G1/00—Cosmonautic vehicles
    • B64G1/22—Parts of, or equipment specially adapted for fitting in or to, cosmonautic vehicles
    • B64G1/42—Arrangements or adaptations of power supply systems
    • B64G1/44—Arrangements or adaptations of power supply systems using radiation, e.g. deployable solar arrays
    • B64G1/443—Photovoltaic cell arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/4207—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells for several batteries or cells simultaneously or sequentially
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014—Circuits for equalisation of charge between batteries
    • H02J7/0018—Circuits for equalisation of charge between batteries using separate charge circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/007188—Regulation of charging or discharging current or voltage the charge cycle being controlled or terminated in response to non-electric parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/007188—Regulation of charging or discharging current or voltage the charge cycle being controlled or terminated in response to non-electric parameters
    • H02J7/007192—Regulation of charging or discharging current or voltage the charge cycle being controlled or terminated in response to non-electric parameters in response to temperature
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
    • H02J7/35—Parallel operation in networks using both storage and other DC sources, e.g. providing buffering with light sensitive cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M2220/00—Batteries for particular applications
    • H01M2220/20—Batteries in motive systems, e.g. vehicle, ship, plane
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
    • H02J2300/20—The dispersed energy generation being of renewable origin
    • H02J2300/22—The renewable source being solar energy
    • H02J2300/24—The renewable source being solar energy of photovoltaic origin
    • H02J2300/26—The renewable source being solar energy of photovoltaic origin involving maximum power point tracking control for photovoltaic sources
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Remote Sensing (AREA)
  • Aviation & Aerospace Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

本发明属于立方星技术领域，具体涉及一种应用于立方星锂电池组的均衡电路。包括电池充电电路、使能电路和均衡子模块。电池充电电路前端接立方星单独为均衡电路提供的太阳能电池阵和热敏电阻，后端接均衡子模块输入端，均衡子模块后端接锂电池的正负极，使能电路在电源下位机的控制下对均衡子模块进行使能，使得均衡子模块的可控开关闭合，电池充电电路便对需要均衡单体电池进行充电。本发明将太阳能电池阵产生的电能补充给电池组能量较低的电池，来实现电池组的均衡，适用于立方星领域，控制简单，安全且效率高。

Figure 202110950408

The invention belongs to the technical field of CubeSat, and particularly relates to an equalization circuit applied to a CubeSat lithium battery pack. Including battery charging circuit, enabling circuit and equalization sub-module. The front end of the battery charging circuit is connected to the solar cell array and thermistor provided by CubeSat for the equalization circuit, the back end is connected to the input end of the equalizer sub-module, and the back end of the equalizer sub-module is connected to the positive and negative electrodes of the lithium battery. The balancing sub-module is enabled under the control of the balancing sub-module, so that the controllable switch of the balancing sub-module is closed, and the battery charging circuit charges the single battery that needs to be balanced. The invention supplements the electric energy generated by the solar cell array to the batteries with lower energy of the battery pack to realize the balance of the battery pack, is suitable for the field of the cube star, has simple control, safety and high efficiency.

Figure 202110950408

Description

Equalizing circuit applied to cube-satellite lithium battery pack
Technical Field
The invention belongs to the technical field of cuboids, and particularly relates to an equalizing circuit applied to a cuboids lithium battery pack.
Background
The power supply system of the solar cell array-storage battery pack is the most widely applied power supply system of the spacecraft at present, and mainly comprises the solar cell array, the storage battery pack and a power supply control device. Currently, most cuboids employ lithium batteries as their battery building blocks.
The lithium battery pack serves as an important component of the cuboidal satellite, and has the main functions of storing electric energy for the cuboidal satellite on the ground and during the on-orbit period and maintaining the electric energy supply of the cuboidal satellite when no external power supply exists. Due to the inconsistency of the monomers, the lithium ion battery has the phenomena of capacity reduction and service life shortening of the battery pack along with the increase of the charging and discharging times of the lithium battery pack.
To solve this problem, the cells in the lithium battery pack need to be balanced, so that the uniformity of each single cell in the lithium battery pack is maintained. Most of the existing satellites adopt a passive equalization mode, and part of the satellites adopt an active equalization mode.
In the passive equalization, a resistor and a controllable switch are connected in parallel on each single lithium battery to perform equalization of the battery, and in the equalization process, redundant energy is consumed on the resistor in the battery with high energy; the passive equalization circuit is simple in structure and control, precious electric energy is lost in the equalization process, and a large amount of heat is generated on the resistor, so that the thermal control management of the satellite is more difficult.
Active balancing generally utilizes energy storage elements such as capacitors, inductors and the like, and a plurality of switches are used for transferring energy from a single battery with high energy to a single battery with low energy, so that the energy transfer of a single battery is realized; the active equalization energy transfer efficiency is high, but the existing active equalization mode needs a large number of devices such as inductors, capacitors and switching tubes, the control strategy and the circuit structure are complex, the reliability is low, and the switching tubes are required to switch on and off the electric energy of the battery at high frequency, so that the problem of electromagnetic interference can be caused.
Disclosure of Invention
The invention aims to provide an equalizing circuit which is safe, reliable, small in size and simple to control and is applied to a cubic satellite lithium battery pack.
The technical solution for realizing the purpose of the invention is as follows: an equalization circuit applied to a cubic satellite lithium battery pack comprises a battery charging circuit, an enabling circuit, more than one high-side equalization submodule and one low-side equalization submodule, wherein the number of the high-side equalization submodules is equal to the number of series-connected lithium batteries minus 1;
the front ends VIN and MP _ GND of the battery charging circuit are respectively connected with the positive end and the negative end of the cube-star solar battery array, the NTC + and NTC-at the front ends are connected with the two ends of the thermistor, and the rear ends output B + and B-;
the front ends enable, D1, C1 and C2 of the enabling circuit are connected with the cube star power lower computer, and the rear end enabling ends of the enabling circuit are respectively connected with enabling ends EN of a plurality of balancing sub-modules;
the front ends of the high-side equalization submodule and the low-side equalization submodule are connected with B + and B-, the rear ends D + of the high-side equalization submodule and the low-side equalization submodule are connected with a positive level of a lithium battery, D-is connected with a negative level of the lithium battery, and an enable end EN is connected with a rear end enable end of an enable circuit.
Furthermore, the lithium battery pack has a three-string structure, and the number of the high-side equalization sub-modules is two and the number of the low-side equalization sub-modules is one; the enabling circuit can provide three enabling ends, and the three enabling ends correspond to the three balancing sub-modules respectively.
Furthermore, each high-side balancing submodule comprises two high-side controllable switches, wherein the front end IN of one high-side controllable switch is connected with B +, the rear end OUT of the one high-side controllable switch is connected with D +, the front end IN of the other high-side controllable switch is connected with B-, the rear end OUT of the other high-side controllable switch is connected with D-, and the enabling pins EN of the two high-side controllable switches are connected together to serve as the enabling pins EN of the high-side balancing submodule;
the low-side balancing submodule comprises a low-side controllable switch and a high-side controllable switch, wherein the front end IN of the high-side controllable switch is connected with B +, the rear end OUT is connected with D +, the front end IN of the low-side controllable switch is connected with B-, the rear end OUT is connected with D-, the enable pins EN of the low-side controllable switch and the high-side controllable switch are connected together to be used as the enable pin EN of the low-side balancing submodule.
Further, the battery charging circuit includes a first integrated chip U1, a first NMOS transistor Q1, a first schottky diode D1, a second diode D2, a first inductor L1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a first light emitting diode LED1, a second light emitting diode LED2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a ninth capacitor C9;
pin No. 0 of the first integrated chip U1 is connected to MP _ GND, pin No. 1 is connected to the output terminal of the third resistor R3 and the input terminal of the fourth capacitor C4, pin No. 2 is connected to the output terminal of the fifth resistor R5 and the input terminal of the eighth resistor R8, pin No. 3 is connected to the negative terminal of the first light emitting diode LED1, pin No. 4 is connected to the output terminal of the sixth resistor R6 and the input terminal of R9, pin No. 5 is connected to the negative terminal of the second light emitting diode LED1, pin No. 6 is connected to the pin No. 7, the input terminal of the sixth capacitor C6 and the input terminal of the sixth resistor R6, pin No. 8 is connected to the output terminal of the eleventh resistor R11, the input terminal of the thirteenth resistor R13 and the output terminal of the eighth resistor C8, pin No. 9 is connected to the output terminal of the ninth capacitor C9, the input terminal of the seventh capacitor C7, the input terminal of the eighth capacitor C8 and the input terminal of the eleventh resistor R11, An input end and an output end B + of a seventh resistor R7 are connected, a pin No. 10 is respectively connected with an input end of a ninth capacitor C9, an output end of a first inductor L1 and an input end of a seventh resistor R7, a pin No. 11 is respectively connected with a pin No. 3 and an MP _ GND of a first NMOS tube Q1, a pin No. 12 is respectively connected with an input end of a second capacitor C2 and a positive end of a second diode D2, a pin No. 13 is connected with a pin No. 4 of a first NMOS tube Q1, a pin No. 14 is respectively connected with pins No. 1 and No. 6 of the first NMOS tube Q1, an output end of a fifth capacitor C5 and an input end of the first inductor L1, a pin No. 15 is connected with a pin No. 2 of the first NMOS tube Q1, and a pin No. 16 is respectively connected with a negative end of the second diode D2 and an input end of the fifth capacitor C5;
the anode VIN of the solar cell array is respectively connected with the input end of a first resistor R1, the input end of a second resistor R2, the input end of a fourth resistor R4, the input end of a tenth resistor R10, the input end of a twelfth resistor R12, the positive end of a first diode D1 and the NTC + end, the cathode of the solar cell array is connected with MP _ GND, and the NTC-at the front end is respectively connected with the output end of a fourth resistor R4 and the input end of a fifth resistor R5; the output end of the first resistor R1 is respectively connected with the output end of the second resistor R2 and the input end of the first capacitor C1; the output end of the first capacitor C1, the output end of the second capacitor C2, the output end of the third capacitor C3, the output end of the fourth capacitor C4, the output end of the sixth capacitor C6, the output end of the seventh capacitor C7, the output end of the eighth resistor R8, the output end of the ninth resistor R9 and the output end of the thirteenth resistor R13 are all connected with MP _ GND respectively; the MP _ GND is connected with an output end B-.
Further, the enabling circuit includes a second integrated chip U2, a first connector P1, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a tenth capacitor C10, an eleventh capacitor C11, and a third light emitting diode LED 3;
the No. 1 pin of the second integrated chip U2 is respectively connected with the output end of a sixteenth resistor R16 and the No. 2 pin of a first connector P1, the No. 2 pin is respectively connected with the input end of a fifteenth resistor R15 and the No. 3 pin of the first connector P1, the No. 3 pin is connected with an output enable end EN3, the No. 4 pin is connected with an output enable end EN2, the No. 5 pin is connected with an output enable end EN1, the No. 6 pin is connected with the input end of a seventeenth resistor R17, the No. 7 pin is connected with the No. 4 pin of a first connector P1, the No. 8 pin is connected with GND, the No. 14 pin is respectively connected with the input end of the fourteenth resistor R14 and the No. 1 pin of the first connector P1, the No. 16 pin is respectively connected with the input end of a tenth capacitor C10, the input end of an eleventh capacitor C11, the input end of the sixteenth resistor R16, the No. 6 pin of the first connector P1 and a power supply P3;
the ground GND is respectively connected with an output end of a fifteenth resistor R14, an output end of a fifteenth resistor R15, an output end of a tenth capacitor C10, an output end of an eleventh capacitor C11, a negative end of a third LED3 lamp and a No. 5 pin of a first connector P1; the output end of the seventeenth resistor R17 is connected to the positive terminal of the third light emitting diode LED 3.
Further, the low-side controllable switch comprises a second NMOS transistor Q2, a third NMOS transistor Q3, a fourteenth resistor R14, a fifteenth resistor R15 and a sixteenth resistor R16;
the D pole of the second NMOS tube is connected with the input end IN, the G pole of the second NMOS tube is respectively connected with the output end of a nineteenth resistor R19 and the input end of a twentieth resistor R20, and the S pole of the second NMOS tube is respectively connected with the output end of a twentieth resistor R20 and the S pole of a third NMOS tube; the G pole of the third NMOS tube is connected with the output end of the eighteenth resistor R18, and the D pole of the third NMOS tube is connected with the output end OUT; the input end of the eighteenth resistor R18 is connected with the input end of the nineteenth resistor R19 and the enabling end EN respectively.
Further, the high-side controllable switch comprises a fourth PMOS transistor Q4, a fifth PMOS transistor Q4, a sixth NMOS transistor, a seventh NMOS transistor, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25 and a twenty-sixth resistor R26;
the S pole of the fourth PMOS tube Q4 is connected with the input end IN and the input end of the twenty-first resistor R21, the G pole of the fourth PMOS tube Q4 is connected with the output end of the twenty-first resistor R21 and the D pole of the sixth NMOS tube Q6, and the D pole of the fourth PMOS tube Q4 is connected with the D pole of the fifth PMOS tube; a G pole of the fifth PMOS tube Q5 is respectively connected with an output end of the twenty-second resistor R22 and a D pole of the seventh NMOS tube Q7, and an S pole of the fifth PMOS tube Q5 is respectively connected with an output end OUT and an input end of the twenty-second resistor R22; a G pole of the sixth NMOS tube is respectively connected with an output end of the twenty-third resistor R23 and an input end of the twenty-fifth resistor R25, and an S pole of the sixth NMOS tube is respectively connected with an output end of the twenty-fifth resistor R25 and GND; and the G pole of the seventh NMOS tube is respectively connected with the output end of the twenty-fourth resistor R24 and the input end of the twenty-sixth resistor R26, and the S pole of the seventh NMOS tube is respectively connected with the output end of the twenty-sixth resistor R26 and GND.
Compared with the prior art, the invention has the remarkable advantages that:
(1) the invention provides an equalizing circuit of a cubic satellite lithium battery pack, which comprises the following equalizing methods: after the satellite runs to an illumination area, judging whether the voltage difference value of each battery in the lithium battery pack is larger than a set threshold value or not; if the voltage of the single lithium battery is greater than the set threshold, the single lithium battery with the lowest voltage in the battery pack is found, and the balancing sub-circuit connected with the single lithium battery with the lowest voltage is controlled to be in a conducting state through the enabling circuit; at the moment, the electric energy generated by the solar cell array is supplemented to the single cells through a cell charging circuit, and after a period of time delay, the process is repeated until the difference value between the single cells in the battery pack is smaller than a set threshold value; therefore, the balance of the lithium battery pack is realized. Compared with the existing passive equalization method of the satellite, the equalization method adopted by the invention has the advantages of small energy loss and small heat; compared with other active equalization methods, the active equalization method has the advantages of less used capacitors, inductors or switching tubes, simple circuit structure and control, low switching frequency of the switching tubes and low switching loss.
(2) The battery charging circuit adopted by the invention selects a charging control chip with the function of regulating input voltage to realize Maximum Power Point Tracking (MPPT); it provides input voltage regulation function, and can reduce charging current when the input voltage is lower than programming voltage; when the input end is powered by the solar cell panel, the input regulating loop can reduce the charging current, so that the solar cell array provides the maximum power output. The maximum power point voltage of the solar cell array changes along with the temperature change, therefore, the battery charging circuit is additionally provided with the thermistor on the input loop, and the programming voltage can change along with the maximum power point voltage of the solar cell array according to the principle that the resistance value of the thermistor changes along with the temperature. The battery charging circuit adopted by the invention can enable the solar battery array to provide the maximum power output under the condition of illumination intensity and temperature change, improves the utilization efficiency of sunlight, increases the current of the battery during balancing and further shortens the balancing time.
(3) The equalizing sub-circuit adopts MOS tubes as controllable switches, the on-resistance Rdson of the MOS tubes is below 26mOhms, and the energy transmission loss is smaller than that when relays or field effect transistors are used as the controllable switches.
(4) The invention adopts the enabling circuit with the analog switch device as the main device, and each output enabling end of the enabling circuit is in a high-resistance state when the battery is not required to be balanced; when the balance is needed, the lower power supply computer controls the four input ends to be in a specified level state, so that the voltage of a certain enabling end is required to be high, and meanwhile, other enabling ends are kept to be in a high-impedance state; and no matter how the states of the four input ends are, at most one enable output end is in a high level, so that misoperation is avoided, a plurality of enable ends are enabled simultaneously, and the problem of short circuit of a certain single battery is further caused. Therefore, the enabling circuit ensures the reliability and mutual exclusivity of the output enabling signal, and further ensures the reliability of the equalizing circuit.
Drawings
Fig. 1 is a schematic diagram of an equalizing circuit framework applied to a cubic lithium battery pack according to the present invention.
Fig. 2 is a schematic diagram of the high side equalization submodule of the present invention.
Fig. 3 is a schematic diagram of a low side equalization submodule of the present invention.
Fig. 4 is a circuit diagram of a battery charging circuit of the present invention.
Fig. 5 is a diagram of an enable circuit of the present invention.
Fig. 6 is a circuit diagram of a low-side controllable switch of the present invention.
Fig. 7 is a circuit diagram of the high-side controllable switch of the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawing figures.
With reference to fig. 1, an equalizing circuit applied to a cubic satellite lithium battery pack includes a battery charging circuit, an enabling circuit, and an equalizing submodule. The front ends VIN and MP _ GND of the battery charging control circuit are respectively connected with the positive end and the negative end of the cube-star solar battery array, the NTC + and NTC-at the front ends are connected with the two ends of the thermistor, and the rear ends output B + and B-. The front ends enable, D1, C1 and C2 of the enabling circuit are connected with the cube-satellite power down computer, and the rear end enabling ends EN1, EN2 and EN3 of the enabling circuit are respectively connected with enabling ends EN of the three balancing sub-modules. The equalizing submodule is divided into a high-side equalizing submodule and a low-side equalizing submodule, the front ends of the high-side equalizing submodule and the low-side equalizing submodule are connected with B + and B-, the rear ends D + of the high-side equalizing submodule and the low-side equalizing submodule are connected with a positive level of a lithium battery, the rear ends D-of the high-side equalizing submodule and the low-side equalizing submodule are connected with a negative level of the lithium battery, and an enabling end EN is connected with a rear enabling end of the enabling circuit.
With reference to fig. 2, the high-side equalizing submodule includes two high-side controllable switches, where a front end IN of one of the high-side controllable switches is connected to B +, a rear end OUT of the high-side controllable switches is connected to D +, a front end IN of the other high-side controllable switch is connected to B-, and a rear end OUT of the other high-side controllable switch is connected to D-, and enable pins EN of the two high-side controllable switches are connected together to serve as enable pins EN of the high-side equalizing submodule.
Furthermore, the equalization sub-circuit comprises more than one high-side equalization sub-module and one low-side equalization sub-module, and the number of the high-side equalization sub-modules is equal to the number of the lithium batteries in series minus 1; in the embodiment of the invention, the lithium battery pack has a three-string structure, so that two high-side equalization sub-modules and one low-side equalization sub-module are provided.
Furthermore, the enabling circuit can provide three enabling ends, and the number of the enabling circuits can be increased according to requirements; in the embodiment of the invention, three enabling ends of one enabling circuit respectively correspond to three equalizing submodules.
With reference to fig. 3, the low-side equalization submodule includes a low-side controllable switch and a high-side controllable switch, wherein the high-side controllable switch has a front end IN connected to B +, a back end OUT connected to D +, a low-side controllable switch has a front end IN connected to B-, a back end OUT connected to D-, a low-side controllable switch and an enable pin EN of the high-side controllable switch are connected together to serve as an enable pin EN of the low-side equalization submodule.
Preferably, with reference to fig. 4, the battery charging circuit includes a first integrated chip U1(BQ24650RVAR), a first NMOS transistor Q1(Si7288DP), a first schottky diode D1(B340LB), a second diode D2(ZLLS350TA), a first inductor L1(10uH), a first resistor R1(3.9R), a second resistor R2(3.9R), a third resistor R3(10R), a fourth resistor R4(475K), a fifth resistor R5(100K), a sixth resistor R6(5.23K), a seventh resistor R7(0.02R), an eighth resistor R8(8.35K), a ninth resistor R9(10K), a tenth resistor R10(10K), an eleventh resistor R11(100K), a twelfth resistor R11 (10K), a thirteenth resistor R11 (11K), a thirteenth resistor R9 (11K), a fourth light emitting diode D11 (11 uc), a fourth light emitting diode (11 uc), a fourth light emitting diode (11 uc 1U 1, 11 f), a fourth light emitting diode (11C 11 f), a light emitting diode (11C 11 f), a fourth light emitting diode (11C 11), a light emitting diode (11 f) and a light emitting diode (11C 11, A fifth capacitor C5(0.1uF), a sixth capacitor C6(1uF), a seventh capacitor C7(20uF), an eighth capacitor C8(22pF), and a ninth capacitor C9(0.1 uF);
pin No. 0 of the first integrated chip U1 is connected to MP _ GND, pin No. 1 is connected to the output terminal of the third resistor R3 and the input terminal of the fourth capacitor C4, pin No. 2 is connected to the output terminal of the fifth resistor R5 and the input terminal of the eighth resistor R8, pin No. 3 is connected to the negative terminal of the first light emitting diode LED1, pin No. 4 is connected to the output terminal of the sixth resistor R6 and the input terminal of R9, pin No. 5 is connected to the negative terminal of the second light emitting diode LED1, pin No. 6 is connected to the pin No. 7, the input terminal of the sixth capacitor C6 and the input terminal of the sixth resistor R6, pin No. 8 is connected to the output terminal of the eleventh resistor R11, the input terminal of the thirteenth resistor R13 and the output terminal of the eighth resistor C8, pin No. 9 is connected to the output terminal of the ninth capacitor C9, the input terminal of the seventh capacitor C7, the input terminal of the eighth capacitor C8 and the input terminal of the eleventh resistor R11, An input end and an output end B + of a seventh resistor R7 are connected, a pin No. 10 is respectively connected with an input end of a ninth capacitor C9, an output end of a first inductor L1 and an input end of a seventh resistor R7, a pin No. 11 is respectively connected with a pin No. 3 and an MP _ GND of a first NMOS tube Q1, a pin No. 12 is respectively connected with an input end of a second capacitor C2 and a positive end of a second diode D2, a pin No. 13 is connected with a pin No. 4 of a first NMOS tube Q1, a pin No. 14 is respectively connected with pins No. 1 and No. 6 of the first NMOS tube Q1, an output end of a fifth capacitor C5 and an input end of the first inductor L1, a pin No. 15 is connected with a pin No. 2 of the first NMOS tube Q1, and a pin No. 16 is respectively connected with a negative end of the second diode D2 and an input end of the fifth capacitor C5;
the anode VIN of the solar cell array is respectively connected with the input end of a first resistor R1, the input end of a second resistor R2, the input end of a fourth resistor R4, the input end of a tenth resistor R10, the input end of a twelfth resistor R12, the positive end of a first diode D1 and the NTC + end, the cathode of the solar cell array is connected with MP _ GND, and the NTC-at the front end is respectively connected with the output end of a fourth resistor R4 and the input end of a fifth resistor R5; the output end of the first resistor R1 is connected with the output end of the second resistor R2 and the input end of the first capacitor C1 respectively.
The output end of the first capacitor C1, the output end of the second capacitor C2, the output end of the third capacitor C3, the output end of the fourth capacitor C4, the output end of the sixth capacitor C6, the output end of the seventh capacitor C7, the output end of the eighth resistor R8, the output end of the ninth resistor R9 and the output end of the thirteenth resistor R13 are all connected with MP _ GND respectively;
the MP _ GND is connected with an output end B-.
Preferably, with reference to fig. 5, the enabling circuit includes a second integrated chip U2(TS3a5017), a first connector P1, a fourteenth resistor R14(4.7K), a fifteenth resistor R15(4.7K), a sixteenth resistor R16(4.7K), a seventeenth resistor R17(510K), a tenth capacitor C10(0.1uF), an eleventh capacitor C11(1uF), and a third light emitting diode LED 3;
the No. 1 pin of the second integrated chip U2(TS3A5017) is respectively connected with the output end of a sixteenth resistor R16 and the No. 2 pin of a first connector P1, the No. 2 pin of the second integrated chip U2(TS3A5017) is respectively connected with the input end of a fifteenth resistor R15 and the No. 3 pin of a first connector P1, the No. 3 pin of the second integrated chip U2(TS3A5017) is connected with an output enable end EN3, the No. 4 pin of the second integrated chip U2(TS3A5017) is connected with an output enable end EN2, the No. 5 pin of the second integrated chip U2(TS3A5017) is connected with an output enable end EN1, the No. 6 pin of the second integrated chip U2(TS3A5017) is connected with the input end of a seventeenth resistor R17, the No. 7 pin of the second integrated chip U2(TS3A5017) is connected with the P8 pin of the first connector P8 pin, the No. 3 pin of the second integrated chip U5017 is connected with a GND pin of the first connector P3527, and the No. 3 pin of the first connector P3514 is connected with the first connector P367 pin of the integrated chip U3614, pin 16 of the second integrated chip U2(TS3A5017) is respectively connected with the input end of a tenth capacitor C10, the input end of an eleventh capacitor C11, the input end of a sixteenth resistor R16, pin 6 of the first connector P1 and a power supply 3V3, and other pins of the second integrated chip U2(TS3A5017) are not used;
the ground GND is respectively connected with an output end of a fifteenth resistor R14, an output end of a fifteenth resistor R15, an output end of a tenth capacitor C10, an output end of an eleventh capacitor C11, a negative end of a third LED3 lamp and a No. 5 pin of a first connector P1;
the output end of the seventeenth resistor R17 is connected to the positive terminal of the third light emitting diode LED 3.
Preferably, in combination with fig. 6, the low-side controllable switch includes a second NMOS transistor Q2(SI3464DV), a third NMOS transistor Q3(SI3464DV), a fourteenth resistor R14(1K), a fifteenth resistor R15(1K), and a sixteenth resistor R16 (10K);
the D pole of the second NMOS tube is connected with the input end IN, the G pole of the second NMOS tube is respectively connected with the output end of a nineteenth resistor R19 and the input end of a twentieth resistor R20, and the S pole of the second NMOS tube is respectively connected with the output end of a twentieth resistor R20 and the S pole of a third NMOS tube;
the G pole of the third NMOS tube is connected with the output end of the eighteenth resistor R18, and the D pole of the third NMOS tube is connected with the output end OUT;
the input end of the eighteenth resistor R18 is connected with the input end of the nineteenth resistor R19 and the enabling end EN respectively.
Preferably, with reference to fig. 7, the high-side controllable switch includes a fourth PMOS transistor Q4(SI3493BDV), a fifth PMOS transistor Q4(SI3493BDV), a sixth NMOS transistor (SI2302CDS), a seventh NMOS transistor (SI2302CDS), a twenty-first resistor R21(100K), a twenty-second resistor R22(100K), a twenty-third resistor R23(1K), a twenty-fourth resistor R24(1K), a twenty-fifth resistor R25(10K), and a twenty-sixth resistor R26 (10K);
the S pole of the fourth PMOS tube Q4 is connected with the input end IN and the input end of the twenty-first resistor R21, the G pole of the fourth PMOS tube Q4 is connected with the output end of the twenty-first resistor R21 and the D pole of the sixth NMOS tube Q6, and the D pole of the fourth PMOS tube Q4 is connected with the D pole of the fifth PMOS tube;
a G pole of the fifth PMOS tube Q5 is respectively connected with an output end of the twenty-second resistor R22 and a D pole of the seventh NMOS tube Q7, and an S pole of the fifth PMOS tube Q5 is respectively connected with an output end OUT and an input end of the twenty-second resistor R22;
a G pole of the sixth NMOS tube is respectively connected with an output end of the twenty-third resistor R23 and an input end of the twenty-fifth resistor R25, and an S pole of the sixth NMOS tube is respectively connected with an output end of the twenty-fifth resistor R25 and GND;
a G pole of the seventh NMOS tube is respectively connected with an output end of a twenty-fourth resistor R24 and an input end of a twenty-sixth resistor R26, and an S pole of the seventh NMOS tube is respectively connected with an output end of a twenty-sixth resistor R26 and GND;
the enable terminal EN is connected to an input terminal of the twenty-third resistor R23 and an input terminal of the twenty-third resistor R23, respectively.
The equalizing process of the equalizing circuit applied to the cubic satellite lithium battery pack comprises the following steps:
firstly, measuring the voltage of a single battery, if the voltage of the BATi is the lowest (assuming that N > -i > -1) in N batteries and the difference value between the voltage of the BATi and the voltage of other single batteries is larger than a set threshold value, the lower computer of the power supply outputs high level through a level high-low control enabling circuit ENi of an input enabling circuit, so that two controllable switches in balancing submodules connected with the BATi in parallel are closed, and the output end of a battery charging circuit is connected with the BATi in parallel.
And secondly, charging the BATi for a certain time by the energy generated by the solar cell panel through a battery charging circuit, so that the voltage of the BATi rises.
The steps are repeated repeatedly to achieve the effect of battery equalization.
The enabling circuit is controlled by a lower computer of a power supply, and the working process of the enabling circuit is as follows:
as shown in table 1, when the battery is not required to be balanced, the front end enable level of the enable circuit is high, and the single output enable terminal of the enable circuit is in a high impedance state no matter whether the levels of C1 and C2 are high or low. When equalization is needed, under the conditions that the front end enable holding level is low and the D1 is high, the C2 is kept low, the C1 is kept high, the D1 is communicated with the EN1, at this time, the D1 is S2 which is EN1, the EN1 is high, and the rest output ends are in a high-impedance state; c2 keeps high level, C1 keeps low level, D1 is communicated with EN2, at this time, D1 is S3 is EN2, EN2 is high level, and the rest of output terminals are in high impedance state; c2 keeps high level, C1 keeps high level, D1 and EN3 are connected, at this time, D1 is S4 is EN3, EN3 is high level, and the rest of the output terminals are in high impedance state.
TABLE 1
enable C2 C1 D1 and S
L L L D1＝S1
L L H D1＝S2＝EN1
L H L D1＝S3＝EN2
L H H D1＝S4＝EN3
H X X OFF
The invention supplements the electric energy generated by the solar cell array to the cell with lower energy of the battery pack so as to realize the balance of the battery pack; by adopting the voltage reduction battery charging circuit with the maximum power point tracking function, the maximum power generated by the solar battery array is ensured, so that the lithium battery is equalized with larger current and shorter equalization time. And an MOS tube is used as a controllable switch, so that energy transmission loss is small. The single-pole four-throw (4:1) analog switch enabling circuit is adopted, so that the reliability and the mutual exclusion of output enabling signals are guaranteed.
Therefore, the method is safer and more reliable, and has high equalization efficiency and strong expandability.

Claims (7)

1. The equalizing circuit applied to the cubic satellite lithium battery pack is characterized by comprising a battery charging circuit, an enabling circuit, more than one high-side equalizing submodule and one low-side equalizing submodule, wherein the number of the high-side equalizing submodules is equal to the number of series-connected lithium batteries minus 1;
the front ends VIN and MP _ GND of the battery charging circuit are respectively connected with the positive end and the negative end of the cube-star solar battery array, the NTC + and NTC-at the front ends are connected with the two ends of the thermistor, and the rear ends output B + and B-;
the front ends enable, D1, C1 and C2 of the enabling circuit are connected with the cube star power lower computer, and the rear end enabling ends of the enabling circuit are respectively connected with enabling ends EN of a plurality of balancing sub-modules;
the front ends of the high-side equalization submodule and the low-side equalization submodule are connected with B + and B-, the rear ends D + of the high-side equalization submodule and the low-side equalization submodule are connected with a positive level of a lithium battery, D-is connected with a negative level of the lithium battery, and an enable end EN is connected with a rear end enable end of an enable circuit.
2. The equalizing circuit of claim 1, wherein the lithium battery pack has a three-string configuration, with two high-side equalizing sub-modules and one low-side equalizing sub-module; the enabling circuit can provide three enabling ends, and the three enabling ends correspond to the three balancing sub-modules respectively.
3. The equalizing circuit of claim 1, wherein each high-side equalizing submodule comprises two high-side controllable switches, wherein one of the high-side controllable switches has a front end IN connected to B +, a rear end OUT connected to D +, and the other of the high-side controllable switches has a front end IN connected to B-, a rear end OUT connected to D-, and enable pins EN of the two high-side controllable switches are connected together to serve as enable pins EN of the high-side equalizing submodule;
the low-side balancing submodule comprises a low-side controllable switch and a high-side controllable switch, wherein the front end IN of the high-side controllable switch is connected with B +, the rear end OUT is connected with D +, the front end IN of the low-side controllable switch is connected with B-, the rear end OUT is connected with D-, the enable pins EN of the low-side controllable switch and the high-side controllable switch are connected together to be used as the enable pin EN of the low-side balancing submodule.
4. The equalizing circuit according to claim 1, wherein the battery charging circuit comprises a first integrated chip U1, a first NMOS transistor Q1, a first schottky diode D1, a second diode D2, a first inductor L1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a first light emitting diode LED1, a second light emitting diode LED2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9;
pin No. 0 of the first integrated chip U1 is connected to MP _ GND, pin No. 1 is connected to the output terminal of the third resistor R3 and the input terminal of the fourth capacitor C4, pin No. 2 is connected to the output terminal of the fifth resistor R5 and the input terminal of the eighth resistor R8, pin No. 3 is connected to the negative terminal of the first light emitting diode LED1, pin No. 4 is connected to the output terminal of the sixth resistor R6 and the input terminal of R9, pin No. 5 is connected to the negative terminal of the second light emitting diode LED1, pin No. 6 is connected to the pin No. 7, the input terminal of the sixth capacitor C6 and the input terminal of the sixth resistor R6, pin No. 8 is connected to the output terminal of the eleventh resistor R11, the input terminal of the thirteenth resistor R13 and the output terminal of the eighth resistor C8, pin No. 9 is connected to the output terminal of the ninth capacitor C9, the input terminal of the seventh capacitor C7, the input terminal of the eighth capacitor C8 and the input terminal of the eleventh resistor R11, An input end and an output end B + of a seventh resistor R7 are connected, a pin No. 10 is respectively connected with an input end of a ninth capacitor C9, an output end of a first inductor L1 and an input end of a seventh resistor R7, a pin No. 11 is respectively connected with a pin No. 3 and an MP _ GND of a first NMOS tube Q1, a pin No. 12 is respectively connected with an input end of a second capacitor C2 and a positive end of a second diode D2, a pin No. 13 is connected with a pin No. 4 of a first NMOS tube Q1, a pin No. 14 is respectively connected with pins No. 1 and No. 6 of the first NMOS tube Q1, an output end of a fifth capacitor C5 and an input end of the first inductor L1, a pin No. 15 is connected with a pin No. 2 of the first NMOS tube Q1, and a pin No. 16 is respectively connected with a negative end of the second diode D2 and an input end of the fifth capacitor C5;
the anode VIN of the solar cell array is respectively connected with the input end of a first resistor R1, the input end of a second resistor R2, the input end of a fourth resistor R4, the input end of a tenth resistor R10, the input end of a twelfth resistor R12, the positive end of a first diode D1 and the NTC + end, the cathode of the solar cell array is connected with MP _ GND, and the NTC-at the front end is respectively connected with the output end of a fourth resistor R4 and the input end of a fifth resistor R5; the output end of the first resistor R1 is respectively connected with the output end of the second resistor R2 and the input end of the first capacitor C1; the output end of the first capacitor C1, the output end of the second capacitor C2, the output end of the third capacitor C3, the output end of the fourth capacitor C4, the output end of the sixth capacitor C6, the output end of the seventh capacitor C7, the output end of the eighth resistor R8, the output end of the ninth resistor R9 and the output end of the thirteenth resistor R13 are all connected with MP _ GND respectively; the MP _ GND is connected with an output end B-.
5. The equalizing circuit according to claim 1, wherein the enabling circuit comprises a second integrated chip U2, a first connector P1, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a tenth capacitor C10, an eleventh capacitor C11, a third LED 3;
the No. 1 pin of the second integrated chip U2 is respectively connected with the output end of a sixteenth resistor R16 and the No. 2 pin of a first connector P1, the No. 2 pin is respectively connected with the input end of a fifteenth resistor R15 and the No. 3 pin of the first connector P1, the No. 3 pin is connected with an output enable end EN3, the No. 4 pin is connected with an output enable end EN2, the No. 5 pin is connected with an output enable end EN1, the No. 6 pin is connected with the input end of a seventeenth resistor R17, the No. 7 pin is connected with the No. 4 pin of a first connector P1, the No. 8 pin is connected with GND, the No. 14 pin is respectively connected with the input end of the fourteenth resistor R14 and the No. 1 pin of the first connector P1, the No. 16 pin is respectively connected with the input end of a tenth capacitor C10, the input end of an eleventh capacitor C11, the input end of the sixteenth resistor R16, the No. 6 pin of the first connector P1 and a power supply P3;
the ground GND is respectively connected with an output end of a fifteenth resistor R14, an output end of a fifteenth resistor R15, an output end of a tenth capacitor C10, an output end of an eleventh capacitor C11, a negative end of a third LED3 lamp and a No. 5 pin of a first connector P1; the output end of the seventeenth resistor R17 is connected to the positive terminal of the third light emitting diode LED 3.
6. The equalizing circuit of claim 3, wherein the low side controllable switch comprises a second NMOS transistor Q2, a third NMOS transistor Q3, a fourteenth resistor R14, a fifteenth resistor R15 and a sixteenth resistor R16;
the D pole of the second NMOS tube is connected with the input end IN, the G pole of the second NMOS tube is respectively connected with the output end of a nineteenth resistor R19 and the input end of a twentieth resistor R20, and the S pole of the second NMOS tube is respectively connected with the output end of a twentieth resistor R20 and the S pole of a third NMOS tube; the G pole of the third NMOS tube is connected with the output end of the eighteenth resistor R18, and the D pole of the third NMOS tube is connected with the output end OUT; the input end of the eighteenth resistor R18 is connected with the input end of the nineteenth resistor R19 and the enabling end EN respectively.
7. The equalizing circuit of claim 3, wherein the high-side controllable switch comprises a fourth PMOS transistor Q4, a fifth PMOS transistor Q4, a sixth NMOS transistor, a seventh NMOS transistor, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, and a twenty-sixth resistor R26;
the S pole of the fourth PMOS tube Q4 is connected with the input end IN and the input end of the twenty-first resistor R21, the G pole of the fourth PMOS tube Q4 is connected with the output end of the twenty-first resistor R21 and the D pole of the sixth NMOS tube Q6, and the D pole of the fourth PMOS tube Q4 is connected with the D pole of the fifth PMOS tube; a G pole of the fifth PMOS tube Q5 is respectively connected with an output end of the twenty-second resistor R22 and a D pole of the seventh NMOS tube Q7, and an S pole of the fifth PMOS tube Q5 is respectively connected with an output end OUT and an input end of the twenty-second resistor R22; a G pole of the sixth NMOS tube is respectively connected with an output end of the twenty-third resistor R23 and an input end of the twenty-fifth resistor R25, and an S pole of the sixth NMOS tube is respectively connected with an output end of the twenty-fifth resistor R25 and GND; and the G pole of the seventh NMOS tube is respectively connected with the output end of the twenty-fourth resistor R24 and the input end of the twenty-sixth resistor R26, and the S pole of the seventh NMOS tube is respectively connected with the output end of the twenty-sixth resistor R26 and GND.
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US20060145662A1 (en) * 2004-12-30 2006-07-06 Industrial Technology Research Institute Hierarchical battery potential equalizing device
CN201199534Y (en) * 2008-01-18 2009-02-25 深圳市比克电池有限公司 Lithium ion battery package and cascade, parallel connection application circuit thereof
CN102064568A (en) * 2010-10-11 2011-05-18 中国科学院青岛生物能源与过程研究所 Active equalizing and protecting system of stackable series-connected lithium battery
CN105207305A (en) * 2015-10-22 2015-12-30 宁波三星医疗电气股份有限公司 Fault indicator monitoring terminal based on solar charging technology
CN110994746A (en) * 2019-12-31 2020-04-10 常州格力博有限公司 Voltage equalization system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060145662A1 (en) * 2004-12-30 2006-07-06 Industrial Technology Research Institute Hierarchical battery potential equalizing device
CN201199534Y (en) * 2008-01-18 2009-02-25 深圳市比克电池有限公司 Lithium ion battery package and cascade, parallel connection application circuit thereof
CN102064568A (en) * 2010-10-11 2011-05-18 中国科学院青岛生物能源与过程研究所 Active equalizing and protecting system of stackable series-connected lithium battery
CN105207305A (en) * 2015-10-22 2015-12-30 宁波三星医疗电气股份有限公司 Fault indicator monitoring terminal based on solar charging technology
CN110994746A (en) * 2019-12-31 2020-04-10 常州格力博有限公司 Voltage equalization system

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