CN113782613B - Split gate MOSFET device - Google Patents
Split gate MOSFET device Download PDFInfo
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- CN113782613B CN113782613B CN202111148366.XA CN202111148366A CN113782613B CN 113782613 B CN113782613 B CN 113782613B CN 202111148366 A CN202111148366 A CN 202111148366A CN 113782613 B CN113782613 B CN 113782613B
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- 101100011794 Caenorhabditis elegans epi-1 gene Proteins 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract 3
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 13
- 238000002347 injection Methods 0.000 claims description 7
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- 238000001465 metallisation Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005524 hole trap Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- 230000003647 oxidation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The invention discloses a split gate MOSFET device, which has the technical scheme that: the semiconductor device comprises a MOSFET, wherein the MOSFET comprises an N + substrate with a bottom layer, an epi1 layer is arranged on the upper layer of the N + substrate, an epi2 layer is arranged on the upper layer of the epi1 layer, a groove is formed in the epi1 layer and the epi2 layer by etching silicon, the depth of an active region in the groove just penetrates through the epi2 layer, the depth of a terminal region in the groove penetrates through the epi2 layer to be 0.5 mu m, first polysilicon, second polysilicon and third polysilicon are respectively deposited in the groove, and P-type impurities B + are injected into the upper layer of the epi2 layer. The invention adopts a separation gate structure, the epi1 at the bottom is thicker, the epi2 at the top is lighter, the bottom of the active region trench is deeper into the epi1 interface, the doping concentration is thicker, the avalanche critical electric field of silicon is increased along with the increase of the doping concentration, the improvement of the withstand voltage is facilitated, and the RSP reaches 6.5mohm.mm2 by taking a 40V device as an example.
Description
Technical Field
The invention relates to the field of MOSFET devices, in particular to a split gate MOSFET device.
Background
In the prior art, a low-voltage MOFEET device, for example, a 40V device is generally adopted as a high-density Trench structure in fig. 1, a red phosphorus substrate sub with thicker doping is generally adopted as a material, two layers of epitaxy are grown on the red phosphorus substrate sub, epi1 doping is generally thicker, the purpose is to reduce the concentration difference between epi1 and the substrate sub so as to reduce the reverse expansion degree of the substrate, and epi2 doping is lighter so as to support the withstand voltage of the device.
Referring to the chinese patent with the prior publication number CN208400855U, a split gate MOSFET device structure is disclosed, which includes an active area, the active area includes a plurality of device cell units connected in parallel, each device cell unit includes a first conductivity type substrate and a first conductivity type drift region, a second conductivity type well region is disposed at the upper part of the first conductivity type drift region, a first type trench and a second type trench disposed at two sides of the first type trench are disposed between the second conductivity type well region, the trenches extend from the surface of the first conductivity type drift region to the inside thereof, a split gate polysilicon, a thick oxide layer and a masking oxide layer are filled in the first type trench, a gate polysilicon and a gate oxide layer are filled in the second type trench, and the inner side of the gate polysilicon is adjacent to the thick oxide layer.
The split gate MOSFET device structure has the advantages of simple manufacturing process, less photoetching times and lower cost, and meanwhile, the width and depth of the trench of the split gate device are easy to control, the voltage resistance of the device is better, and the on-resistance of the device is lower. The split gate MOSFET device structure described above is still relatively high with respect to RSP.
Disclosure of Invention
In view of the problems mentioned in the background art, it is an object of the present invention to provide a split gate MOSFET device to solve the problems mentioned in the background art.
The technical aim of the invention is realized by the following technical scheme:
The utility model provides a split gate MOSFET device, includes the MOSFET tube, the MOSFET tube includes the N + substrate that has the bottom, the upper strata of N + substrate is equipped with the epi1 layer, the upper strata of epi1 layer is equipped with the epi2 layer, through etching silicon in epi1 layer and the epi2 layer forms the slot, the depth just pierces through the epi2 layer in the active region in the slot, the depth that the depth penetrated the epi2 layer in the termination region in the slot is 0.5 mu m, the inside of slot has deposited first polycrystalline silicon and second polycrystalline silicon respectively, the upper end of first polycrystalline silicon has still deposited third polycrystalline silicon, the upper strata of epi2 layer is poured into P type impurity B +, the one end of P type impurity B + is through the lithography and is formed N + injection region, the interior implantation of N + injection region has N +, deposit the medium deposit layer on the P type impurity B +, deposit the metal deposit layer on the medium deposit layer.
By adopting the technical scheme, the 40V MOSFET device adopts a split gate structure, adopts double-layer epitaxy, has thicker epi1 at the bottom, reduces the reverse expansion degree of the substrate on one hand, and has the silicon doping concentration which is lighter than epi1 but thicker than epi2 at the bottom of a deep groove just positioned on the epitaxial interface of epi1 and epi2 on the other hand, and increases with the increase of doping concentration by utilizing the avalanche critical electric field of silicon, thereby improving the withstand voltage; the epi2 at the top is lighter (thicker than the epi2 of the conventional Trench product) than the epi1 at the bottom, and the voltage withstand is increased by applying the charge balance principle, so that better RSP is obtained, and the RSP reaches 6.5mohm.mm 2.
Preferably, two ends of the MOSFET are divided into an active area and a terminal area, the bottom end of the groove in the active area is positioned at the junction surface of the epi1 layer and the epi2 layer, and the bottom end of the groove in the terminal area is positioned inside the epi1 layer.
By adopting the technical scheme, the depth difference of the grooves on the two sides is 0.3-0.5 mu m, the withstand voltage of the terminal area can be ensured to be larger than that of the active area after the device is formed, and the reliability of the device is ensured.
Preferably, the P-type impurity B + pushes on the epi2 layer to form a P-type impurity B + implantation region, and the junction depth of the P-type impurity B + implantation region is 0.7 μm.
By adopting the technical scheme, the P-type impurity B + can effectively improve the conductivity of the MOSFET.
Preferably, an oxide layer is arranged on the inner wall of the groove, and the oxide layer is a thermally grown thin oxide layerAnd CVD depositing an oxide layer
By adopting the technical scheme, the oxide layer can effectively inhibit high-density electron and hole traps, the traps can introduce a fast interface state to cause charge instability under bias voltage and temperature stress, and the defects that the oxide layer near the silicon generates more defects due to tensile stress caused by different thermal expansion coefficients of silicon and silicon dioxide are reduced, so that small spots and oxide layer pinholes caused by uneven local growth rate of the oxide layer are reduced.
Preferably, the silicon doping concentration of the epi1 layer is higher than that of the epi2 layer, and the RSP of the epi2 layer reaches 6.5m ohm.mm 2.
By adopting the technical scheme, the avalanche critical electric field of silicon is increased along with the increase of doping concentration, so that the withstand voltage is improved; the concentration of the top epi2 layer relative to the epi1 layer is lighter (more concentrated than the epi2 of the common Trench product), and the voltage resistance is increased by applying the charge balance principle, so that better RSP (reactive power) is obtained, and the concentration reaches 6.5m ohm.mm 2.
Preferably, the first polysilicon forms a source, the third polysilicon forms a gate, and the second polysilicon forms a drain.
By adopting the technical scheme, an effective external circuit connector can be formed, and the circuit is convenient to connect and use.
Preferably, one end of the metal deposition layer is inserted through one end of the dielectric deposition layer, the P-type impurity B + and the N +.
By adopting the technical scheme, effective circuit connection can be formed, and the use of the MOSFET is convenient.
Preferably, the depth of the trench inside the active region is 2-3 μm, the depth of the trench inside the termination region is 2.3-3.5 μm, and the thickness of the epi 1 layer and the epi2 layer is 2-3 μm.
By adopting the technical scheme, after the device is formed, the withstand voltage of the terminal area is ensured to be greater than that of the active area, and the reliability of the device is ensured.
In summary, the invention has the following advantages:
The 40V MOSFET device adopts a split gate structure, adopts double-layer epitaxy, has thicker epi1 at the bottom, reduces the reverse expansion degree of a substrate on one hand, and has the silicon doping concentration which is lighter than epi1 but thicker than epi2 at the bottom of a deep groove just positioned at the epitaxial interface of epi1 and epi2 on the other hand, and increases with the increase of doping concentration by utilizing the avalanche critical electric field of silicon, thereby improving the withstand voltage; the epi2 at the top is lighter (thicker than the epi2 of the conventional Trench product) than the epi1 at the bottom, and the voltage withstand is increased by applying the charge balance principle, so that better RSP is obtained, and the RSP reaches 6.5mohm.mm 2.
Drawings
FIG. 1 is a schematic diagram of a prior art MOSFET structure of the present invention;
Fig. 2 is a schematic diagram of the MOSFET tube structure of the present invention.
Reference numerals: 1. an N + substrate; 2. an epi1 layer; 3. an epi2 layer; 4. a groove; 5. a first polysilicon; 6. a second polysilicon; 7. a third polysilicon; 8. p-type impurity B +;9、N+ implantation region; 10. n +; 11. a dielectric deposition layer; 12. a metal deposition layer; 13. an active region; 14. a termination region; 15. p-type impurity B + implantation region; 16. and (5) an oxide layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
Referring to fig. 1-2, a split gate MOSFET device includes a MOSFET tube including an N + substrate 1 having a bottom layer, an epi1 layer 2 is provided on the upper layer of the N + substrate 1, an epi2 layer 3 is provided on the upper layer of the epi1 layer 2, a trench 4 is formed in the epi1 layer 2 and the epi2 layer 3 by etching silicon, an active region in the trench 4 just penetrates the epi2 layer 3 to a depth of 0.5 μm in a termination region in the trench 4, a first polysilicon 5 and a second polysilicon 6 are respectively deposited in the trench 4, a third polysilicon 7 is also deposited on an upper end of the first polysilicon 5, a P-type impurity B + 8 is implanted in the upper layer of the epi2 layer 3, an N + is implanted in the P-type impurity B + by photolithography to form an N + implantation region 9,N + in the implantation region 9, a dielectric deposition layer 11 is deposited on the P-type impurity B +, and a metal deposition layer 12 is deposited on the dielectric deposition layer 11.
By adopting the technical scheme, the 40V MOSFET device adopts a split gate structure, adopts double-layer epitaxy, has a thicker epi1 layer 2 at the bottom, reduces the reverse expansion degree of a substrate on one hand, and has a silicon doping concentration which is lighter than that of the epi1 layer 2 and is thicker than that of the epi2 layer 3 at the interface just at the epitaxial interface of the epi1 layer 2 and the epi2 layer 3 at the bottom of a deep groove on the other hand, and increases with the increase of doping concentration by utilizing the avalanche critical electric field of silicon, thereby improving the withstand voltage; the epi2 layer 3 at the top is thinner than the epi1 layer 2 at the bottom, and is thicker than the epi2 layer 3 of the common Trench product, and the voltage resistance is increased by applying the charge balance principle, so that better RSP (reactive power plasma) is obtained, and the RSP reaches 6.5m ohm.mm 2.
In this embodiment, it is preferable that the two ends of the MOSFET tube are divided into an active area 13 and a termination area 14, and the bottom end of the trench 4 in the active area 13 is located at the junction surface of the epi1 layer 2 and the epi2 layer 3, and the bottom end of the trench 4 in the termination area 14 is located inside the epi1 layer 2. The effect is that the depth difference of the grooves 4 on the two sides is 0.3-0.5 mu m, the withstand voltage of the terminal area 14 can be ensured to be larger than that of the active area 13 after the device is formed, and the reliability of the device is ensured.
In this embodiment, it is preferable that the P-type impurity B + is advanced on the epi2 layer 3 to form the P-type impurity B + implantation region 15, and the junction depth of the P-type impurity B + implantation region 15 is 0.7 μm. The effect is that the setting of the P-type impurity B + can effectively improve the conductivity of the MOSFET.
In this embodiment, preferably, the inner wall of the trench 4 is provided with an oxide layer 16, and the oxide layer 16 is a thermally grown thin oxide layerAnd CVD depositing an oxide layerThe oxide layer 16 has the effects of effectively inhibiting high-density electron and hole traps which can introduce a fast interface state to cause charge instability under bias and temperature stress, reducing the difference of thermal expansion coefficients of silicon and silicon dioxide to generate tensile stress so as to cause more defects of the oxide layer nearby the silicon, and reducing small spots and oxide pinholes caused by uneven local growth rate of the oxide layer.
In this embodiment, the epi1 layer 2 preferably has a higher silicon doping concentration than the epi2 layer 3, and the epi2 layer 3 has an RSP of 6.5mohm.mm 2. The effect is that the avalanche critical electric field of silicon is increased along with the increase of doping concentration, so that the withstand voltage is improved; the concentration of the top epi2 layer 3 relative to the epi1 layer 2 is thinner, compared with the epi2 of the common Trench product, the voltage resistance is increased by applying the charge balance principle, so that better RSP (reactive power plasma) is obtained, and the concentration reaches 6.5m ohm.mm 2.
In this embodiment, the first polysilicon 5 forms a source, the third polysilicon 7 forms a gate, and the second polysilicon 6 forms a drain. The effect is, can form effectual external circuit joint, be convenient for carry out the connection of circuit and use.
In this embodiment, preferably, one end of the metal deposition layer 12 is inserted through one end of the dielectric deposition layer 11, the P-type impurity B + and the N +. The effect is, can form effectual circuit connection, the use of the MOSFET pipe of being convenient for.
In this embodiment, it is preferable that the depth of the trench 4 inside the active region 13 is 2-3 μm, the depth of the trench 4 inside the termination region 14 is 2.3-3.5 μm, and the thicknesses of the epi1 layer 2 and the epi2 layer 3 are 2-3 μm. The effect is that after the device is formed, the voltage withstand of the terminal area 14 is ensured to be larger than that of the active area 13, and the reliability of the device is ensured.
The preparation method comprises the following steps:
The first step: growing an N epitaxial layer on the N + substrate 1, namely an epi1 layer 2, and generating an epi2 layer 3 on the epi1 layer 2, wherein if a 40VN red phosphorus substrate is adopted, the resistivity of the epi1 layer 2 and the epi2 layer 3 is respectively 0.01-0.08ohm.cm and 0.1-0.2ohm.cm, and the epitaxial thickness is 2-3 mu m;
and a second step of: depositing silicon dioxide on the epi2 layer 3 to a thickness of 0.6 μm as a masking layer, and photoetching and etching the masking layer to form a pattern;
And a third step of: the silicon dioxide masking layer is used as a barrier, silicon is etched to form the groove 4, the trench CD of the terminal area 14 is larger than that of the active area 13, and the etching rate is high, so that the depth of the groove 4 of the terminal area 14 exceeds 0.3-0.5 mu m of the active area 13, the withstand voltage of the terminal area 14 can be ensured to be larger than that of the active area 13 after the device is formed, and the reliability of the device is ensured;
fourth step: forming a thermally grown thin oxide layer on the surface of epi2 layer 3 and within trench 4 Depositing an oxide layer
Fifth step: depositing polysilicon, etching the polysilicon, forming polysilicon at the bottom of the groove 4, and removing the oxide layer at the upper part;
fifth step: then HDP deposition oxide layer, CMP is carried out, and then etching is carried out until the thickness of the isolation oxide layer is
Sixth step: then gate oxidation, polysilicon deposition and polysilicon back etching are carried out;
Seventh step: p-type impurity B + is implanted on epi2 layer 3 and P-type impurity B + is advanced to form P-type impurity B + implanted region 15 with a junction depth of about 0.7 μm;
Eighth step: then N + photoetching is carried out at one end of the P-type impurity B+8 to form an N + injection region 9, and then N + is injected;
ninth step: performing dielectric deposition on the P-type impurity B+8 to form a dielectric deposition layer 11, and performing dielectric lithography and hole corrosion;
Tenth step: and then, depositing a metal deposition layer 12 on the dielectric deposition layer 11, photoetching and etching to respectively lead out a grid electrode, a source electrode, thinning the back surface, etching back surface silicon and metalizing the back surface to form a drain electrode.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A split gate MOSFET device comprising a MOSFET tube, characterized by: the MOSFET comprises an N + substrate (1) with a bottom layer, wherein an epi1 layer (2) is arranged on the upper layer of the N + substrate (1), an epi2 layer (3) is arranged on the upper layer of the epi1 layer (2), the doping concentration of the epi2 layer (3) is lower than that of the epi1 layer (2), a groove (4) is formed in the epi1 layer (2) and the epi2 layer (3) through etching silicon, the depth in an active area in the groove (4) just penetrates through the epi2 layer (3), so that the bottom in the active area in the groove (4) is positioned on an epitaxial interface of the epi1 layer (2) and the epi2 layer (3), and the doping concentration of the interface is higher than that of the epi2 layer (3) and lower than that of the epi1 layer (2). The depth of the epi2 layer (3) in the termination region in the trench (4) is 0.5 mu m, the first polysilicon (5) is deposited in the active region in the trench (4), the second polysilicon (6) is deposited in the termination region in the trench (4), the third polysilicon (7) is also deposited at the upper end of the first polysilicon (5), the P-type impurity B + (8) is injected into the upper layer of the epi2 layer (3), the N + injection region (9) is formed in the upper layer of the epi2 layer (3) through photoetching, the N + injection region (9) is internally injected with the N-type impurity (10), the medium deposition layer (11) is deposited on the P-type impurity B + (8), and the metal deposition layer (12) is deposited on the medium deposition layer (11).
2. A split gate MOSFET device according to claim 1, characterized in that: the two ends of the MOSFET are divided into an active area (13) and a terminal area (14), the bottom end of the groove (4) in the active area (13) is positioned at the junction surface of the epi1 layer (2) and the epi2 layer (3), and the bottom end of the groove (4) in the terminal area (14) is positioned inside the epi1 layer (2).
3. A split gate MOSFET device according to claim 1, characterized in that: the P-type impurity B + (8) advances on the epi2 layer (3) to form a P-type impurity B + injection region (15), and the junction depth of the P-type impurity B + injection region (15) is 0.7 mu m.
4. A split gate MOSFET device according to claim 1, characterized in that: an oxide layer (16) is arranged on the inner wall of the groove (4), and the oxide layer (16) is a thermally grown thin oxide layer 500A and a CVD deposited oxide layer 1000A-1500A.
5. A split gate MOSFET device according to claim 1, characterized in that: the silicon doping concentration of the epi1 layer (2) is higher than that of the epi2 layer (3), and the RSP of the epi2 layer (3) reaches 6.5mohm.mm 2.
6. A split gate MOSFET device according to claim 1, characterized in that: the first polysilicon (5) forms a source, the third polysilicon (7) forms a gate, and the second polysilicon (6) forms a drain.
7. A split gate MOSFET device according to claim 1, characterized in that: one end of the metal deposition layer (12) is penetrated and inlaid at one end parts of the dielectric deposition layer (11), the P-type impurity B + (8) and the N-type impurity (10).
8. A split gate MOSFET device according to claim 2, characterized in that: the depth of the trench (4) inside the active region (13) is 2-3 μm, the depth of the trench (4) inside the termination region (14) is 2.3-3.5 μm, and the thickness of the epi1 layer (2) and the epi2 layer (3) are both 2-3 μm.
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| CN105655402A (en) * | 2016-03-31 | 2016-06-08 | 西安龙腾新能源科技发展有限公司 | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same |
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| US8338887B2 (en) * | 2005-07-06 | 2012-12-25 | Infineon Technologies Ag | Buried gate transistor |
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| US20100090274A1 (en) * | 2008-10-10 | 2010-04-15 | Force Mos Technology Co. Ltd. | Trench mosfet with shallow trench contact |
| CN204391119U (en) * | 2015-01-23 | 2015-06-10 | 无锡同方微电子有限公司 | A kind of two trench field-effect pipe |
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