CN113746848B - Parallel programmable group packaging device and method - Google Patents
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- H—ELECTRICITY
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- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
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Abstract
The invention relates to the technical field of communication, and provides a parallel programmable group packaging device and a method. The method comprises the following steps: acquiring the packet header vector, and generating a first addressing address according to the element classes contained in the packet header vector and the element quantity in each element class; and finding out a corresponding packet rule in a memory according to the first addressing address, and completing packet packing on the data in the packet header vector according to the packet rule. The programmable scheme of the group package rule and addressing provided by the invention can break the limitation that the type of the analysis protocol is fixed and cannot be expanded.
Description
[ technical field ] A
The invention relates to the technical field of communication, in particular to a parallel programmable group packaging device and a method.
[ background of the invention ]
The data packet packer of the switch forwarding engine packs the header of a network protocol message, takes the header of a data frame from the forwarding engine and description information (descriptors) such as corresponding port information, storage addresses and the like as input data, and analyzes, identifies and extracts key fields in the data to output the key fields to a subsequent search engine in the forwarding engine. In an actual data packet packaging device module, besides parsing and field extraction of a message header, the actual data packet packaging device module also carries a descriptor of an original input, and the descriptor is transmitted to a later stage along a pipeline along the message, but does not participate in a packaging process.
Software Defined Networking (SDN) is a new Network creation architecture, a way to implement Network virtualization. For the parsing technology of the network protocol data packet header, the SDN is required to support a user-defined protocol, that is, a chip can identify and restore different data frame formats through software programming, which requires that the hardware design of the packet parser has certain flexibility, that is, the same hardware can support a packet package of the user-defined protocol through software configuration.
In a high-performance Ethernet switch chip, a data packet packaging unit generally adopts a pipeline structure at present, all input data packets are transmitted step by step according to the same pipeline, and the middle of the data packet packaging unit can not be paused so as to ensure that data can not be jammed in the switch chip. The operations of packet restoration are sequentially arranged in the assembly line according to the protocol encapsulation hierarchical sequence, most of network data packet grouping processes can be regarded as a multi-branch tree structure, and extraction and matching are carried out on corresponding domains of tree nodes of the layer at each layer, so that packet header generation of the protocol of the layer is realized. In view of this, overcoming the drawbacks of the prior art is a problem to be solved urgently in the art.
[ summary of the invention ]
The invention aims to solve the technical problems that the prior serial pipeline structure introduces larger time delay, the processing capacity of a single pipeline processing unit is limited, only a limited packet header can be combined, a fixed-architecture packet packing device can only support the prior protocol, and the expansibility is low.
The invention adopts the following technical scheme:
in a first aspect, the invention provides a parallel programmable packet packing method, wherein a packet header vector is composed of all input data to be packed; the data to be packaged is divided into different element classes according to different byte lengths, and the method comprises the following steps:
acquiring the packet header vector, and generating a first addressing address according to the element class contained in the packet header vector and the number of elements in each element class;
and finding out a corresponding packet rule in a memory according to the first addressing address, and completing packet packing on the data in the packet header vector according to the packet rule.
Preferably, the data to be packed in the packet header vector is arranged according to a nesting relationship of each layer of protocols, and the packing of the data in the packet header vector according to the packing rule specifically includes:
splitting the packet header vector into one or more packet packing units according to the nesting relationship of each layer of protocol in the packet packing rule;
the split group package units are transmitted to each group package processing module in parallel;
and each group package processing module generates a second addressing address according to the acquired element classes contained in the group package unit and the element quantity in each element class, positions the second addressing address to a corresponding group package sub-rule in the group package rule, and completes group package on the data in the group package unit according to the group package sub-rule.
Preferably, the element class is set according to a type of a byte length corresponding to each parameter included in the packet header vector; wherein the kind of the byte length at least comprises one or more of 1 byte, 2 bytes and 4 bytes.
Preferably, the group package processing module supports 64 bytes of any 16 element completion group packages, wherein 64 bytes are divided into 16 containers with the size of 4 bytes, and the 4 bytes are the maximum value of the byte length in each element class; then the completing the group packaging of the data in the group packaging unit according to the group packaging sub-rule specifically includes:
the group package processing module puts each element analyzed by the group package unit into 16 containers with the size of 4 bytes;
the group packet processing module uses 15 one-out-of-four selectors to respectively correspond to the 16 containers with the size of 4 bytes, data in the previous container is positioned by the one-out-of-four selector to be connected in series after the effective data bit in the next container is positioned, and the effective data in the 16 th container is sequentially connected in series, so that the invalid data in each container is extruded, and a 64-byte real effective packet header section is formed.
Preferably, the process of forming 64 bytes of truly valid packet header segments, which is performed in one computer processing clock cycle, is performed 15 times with a four-out-of-one selector operation, which correspondingly extrudes invalid data in each container.
Preferably, the container is embodied as a register.
It is preferable thatN types of element classes are specifically contained in the packet header vector, and the number of elements in the ith type of element class is marked as a i Wherein i ranges from 1 to n; generating a first addressing address according to the element classes contained in the packet header vector and the element numbers in each element class, specifically:
first addressing address = f (a) 1 ,a 2 ,...,a i )；
Wherein f is a corresponding function, and is used for obtaining a unique value corresponding to each packet header through a result obtained by solving through the function f under the currently maintained group package rule.
Preferably, the element classes contained in the group package unit acquired by the group package processing module include m types, and the number of elements in the jth element class is denoted by b j Wherein j ranges from 1 to m; then, each group packet processing module generates a second addressing address according to the obtained element classes contained in the group packet unit and the number of elements in each element class, specifically:
second addressing address = f (b) 1 ,b 2 ,...,b j )；
Wherein, f is a corresponding function, and is used for obtaining a unique value corresponding to each packet header through a result obtained by the function f under the currently maintained group package rule.
Preferably, the group packing unit includes: one or more of IPv4, IPv6, ARP, eth, otag, and ptag.
In a second aspect, the present invention further provides a parallel programmable group packaging device, configured to implement the parallel programmable group packaging method in the first aspect, where the group packaging device includes:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the parallel programmable group packaging method of the first aspect.
In a third aspect, the present invention also provides a non-transitory computer storage medium having stored thereon computer-executable instructions for execution by one or more processors for performing the parallel programmable group packaging method of the first aspect.
The programmable scheme of the group package rule and the addressing can break the limitation that the type of the analysis protocol is fixed and cannot be expanded.
In the preferred implementation scheme of the invention, the online high-speed packaging is realized through the introduction and design of the register, and in the current project, the linear speed processing of 1 beat and 1 packet is achieved. And the support and low delay of the user-defined protocol are realized.
The division of elements in the group package unit and the corresponding parallel processing mechanism provided in the preferred scheme of the invention can ensure the realizability and the high efficiency of the online processing capability in any hardware design needing to improve the processing capability through multithreading in parallel.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a flow chart of a parallel programmable group packing method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating the effect of a grouping rule provided by an embodiment of the present invention;
FIG. 3 is a flow chart of a parallel programmable group packing method according to an embodiment of the present invention;
FIG. 4 is a block diagram of a programmable group wrapper provided by an embodiment of the present invention;
FIG. 5 is a diagram illustrating the effect of a programmable bank register according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the effect of a grouping rule provided by an embodiment of the present invention;
FIG. 7 is a diagram illustrating a data structure partitioning method according to an embodiment of the present invention;
figure 8 is a block diagram of a programmable group wrapper provided by an embodiment of the present invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
the embodiment 1 of the invention provides a parallel programmable packet packing method, wherein a packet header vector consists of all input data to be packed; the data to be packed is divided into different element classes according to different byte lengths, as shown in fig. 1, the method includes:
in step 201, a Packet Header Vector (PHV) is obtained, and a first addressing address is generated according to an element class included in the Packet Header Vector and the number of elements in each element class.
N types of element classes are contained in the packet head vector, and the number of elements in the ith type of element class is marked as a i Wherein i ranges from 1 to n; generating a first addressing address according to the element classes contained in the packet header vector and the element numbers in each element class, specifically:
first addressing address = f (a) 1 ,a 2 ,...,a i )；
Wherein, f is a corresponding function, and is used for obtaining a unique value corresponding to each packet header through a result obtained by the function f under the currently maintained group package rule.
For example, as an example, the simplest implementation of the function f is to take the above a 1 ,a 2 ,...,a i As a function of the corresponding packet header in the addressing memory. This is achieved byFor example, as shown in fig. 2, the first addressing address may find the address a at the time, where the current packet header vector corresponds to fig. 2, where the current packet header vector is formed by nesting a first packet unit, a second packet unit, a third packet unit, a fourth packet unit, and a fifth packet unit one by one, and the packet sub-rules under the corresponding packet units are also recorded in the packet units in fig. 2; at this time, the complete packet packing rule of the packet header vector can be obtained through the first addressing address. In order to improve the processing efficiency, the set of rules as shown in fig. 2 are stored in the SRAM memory in advance. The group packing unit includes one or more of IPv4, IPv6, ARP, eth, otag, and ptag, where each group packing unit represents a type of packet header protocol format, and the corresponding protocol format is the existing concept and is not described herein in detail. In the embodiment of the present invention, each header protocol format is composed of a plurality of fields, and in a preferred implementation of the present invention, each of the constituent fields is set to have a maximum length of not more than 4 bytes.
Compared with the implementation mode, the embodiment of the present invention further provides another packet rule management mode, which is different from fig. 2 and will be specifically set forth in the following extended implementation schemes. As the present invention, both of the two group rule management methods are within the scope of the present invention.
In step 202, a corresponding set of packet rules is found in the memory according to the first addressing address, and the data in the packet header vector is packed according to the set of packet rules.
The package rule and the addressing programmable scheme provided by the embodiment of the invention can break the limitation that the type of the analysis protocol is fixed and cannot be expanded.
In an implementation scenario of the embodiment of the present invention, data to be packaged in the packet header vector is arranged according to a nesting relationship of each layer of protocol, where it is described that data in the packet header vector is not chaotic, but is divided in advance according to each layer of protocol, and then the data in the packet header vector is packaged according to the packaging rule, as shown in fig. 3, the method specifically includes:
in step 301, according to the nesting relationship of each layer of protocol in the packet packing rule, the packet header vector is split into one or more packet packing units.
Still taking fig. 2 as an example, if the first row structure is taken as a packet header vector for example, the corresponding packet header vector may be divided into a first group packet unit, a second group packet unit, a third group packet unit, a fourth group packet unit, and a fifth group packet unit.
In step 302, the split group package units are transmitted to each group package processing module in parallel.
Taking fig. 4 as an example, an effect diagram showing that the packet header vectors are transmitted to the group packet processing unit in parallel is shown. Similarly, for implementation of the embodiment of the present invention, the above steps 201 to 202 may also be implemented by a single process, but as a preferred implementation, the packet rule addressing manner proposed by the present invention may support a parallel architecture as shown in fig. 4.
In step 303, each group packet processing module generates a second addressing address according to the obtained element class included in the group packet unit and the number of elements in each element class, locates the corresponding group packet sub-rule in the group packet rule, and completes group packet for the data in the group packet unit according to the group packet sub-rule.
In the embodiment of the present invention, through the division of elements in the group packaging unit and the corresponding parallel processing mechanism proposed in the preferred scheme of steps 301 to 303, in any hardware design requiring parallel processing capability enhancement through multithreading, the mechanism can ensure the realizability and the high efficiency of the processing capability on the line.
In the embodiment of the present invention, the element class is set according to the class of the byte length corresponding to each parameter included in the packet header vector; wherein the kind of the byte length at least comprises one or more of 1 byte, 2 bytes and 4 bytes. With the expansion of the protocol, the byte lengths corresponding to the parameters specified in the corresponding protocol are not necessarily just the ones listed above, and may also be expanded to 8 bytes, 16 bytes, and so on, and therefore, the above-mentioned setting of the byte length should not be taken as a factor for limiting the scope of the present invention.
Moreover, for convenience of description, in the subsequent extended real-time mode of the present invention, the maximum value of the corresponding byte length is also limited to 4 bytes for content explanation, but as for those skilled in the art, it is not necessary to creatively work to extend the maximum value of the byte number of the subsequent embodiment to 8 bytes, 16 bytes, etc., and therefore, a simple adjustment of the byte number should fall within the protection scope of the present invention.
As another core improvement point in the implementation process of the present invention, the on-line high-speed packet packing is implemented by using a register (for example, implemented by using the packet header combination engine in fig. 4 in cooperation with the container shown in fig. 5, where the container in fig. 5 is the register), so as to achieve the effect of line-speed processing of 1 beat 1 packet. In combination with the embodiment of the present invention, taking fig. 4 as a scene example, the group package processing module supports 64 bytes any 16 elements to complete group package, where 64 bytes are divided into 16 containers each having a size of 4 bytes, and the 4 bytes are the maximum value of the byte length in each element class; in fig. 4, the group packet processing modules represented as 4 parallel processing modules are respectively configured to process writing of a packet header L2 layer, a packet header L3 layer, a packet header L4 layer, and a packet header L5 layer, and then complete group packet of data in the group packet unit according to the group packet sub-rule, with reference to fig. 5, specifically include:
the group package processing module puts each element parsed from the group package unit into 16 containers each having a size of 4 bytes. The group packet processing module uses 15 one-out-of-four selectors respectively corresponding to the 16 containers with the size of 4 bytes, data in the previous container is positioned by the one-out-of-four selector and then is connected in series after effective data bits in the next container are positioned, and the effective data bits are sequentially connected in series after effective data in the 16 th container, so that invalid data in each container are extruded out, and a 64-byte real effective packet head section is formed.
In the above preferred implementation of the embodiment of the present invention, the on-line high-speed packet packaging is implemented through the introduction and design of the register, and in the current project, the line speed processing of 1 beat and 1 packet is achieved. And the support and low delay of the user-defined protocol are realized.
The packaging processing module extracts elements from the packaging unit, and the packaging sub-rule ensures that the header data is valid; wherein the elements stored in each container are mapped with valid byte lengths in a matching manner, wherein the valid byte lengths include 0 byte, 1 byte, 2 bytes and 4 bytes, as shown in fig. 5, the directions are from left to right, the selector starts from the last container (namely, the leftmost one in fig. 5 is in the packed vector, and the corresponding packed element is arranged in the last packed element), the four-choice selector specifies the next splicing position of the valid positions from the unified 4-byte container each time, so that the previously spliced data is further spliced after the valid data of the next container, namely, in the third column in fig. 5, the 3 rd byte position in the third container (wherein the byte positions in the container are all ordered from the 1 st byte) is selected by the second selector to be the splicing position, and then the spliced data in the second column is spliced to the 3 rd byte position of the third container in the line, so as to obtain the data content below the third column in fig. 5. The effective byte length is that effective data in each container is spliced from bottom to top, the head part of the 64 bytes is formed finally, an effective packet head section is stored, and the tail part of the 64 bytes is used for storing a packet of an invalid packet head section.
As another packet rule management mode proposed by the embodiment of the present invention, it is also a rule management mode better suitable for the implementation of the architecture shown in fig. 4, the protocol header matching and identifying 1, the protocol header matching and identifying 2, the protocol header matching and identifying 3, and the protocol header matching and identifying 4 in fig. 4 can be understood as virtual modules for performing the following addressing, where the packet header L2 layer packet, the packet header L3 layer packet, the packet header L4 layer packet, and the packet header L5 layer packet can be understood as virtual modules after obtaining the packet sub-rule, and the corresponding packet header combining engine 1, the packet header combining engine 2, the packet header combining engine 3, and the packet header combining engine 4 can be understood as virtual modules that complete the packet operation of the corresponding element in the packet vector according to the packet sub-rule.
The number of element classes contained in the package unit obtained by the package processing module is m, and the number of elements in the jth element class is marked as b j Wherein j ranges from 1 to m as an example; then, each group packet processing module generates a second addressing address according to the obtained element classes contained in the group packet unit and the number of elements in each element class, specifically:
second addressing address = f (b) 1 ,b 2 ,...,b j )；
Wherein, f is a corresponding function, and is used for obtaining a unique value corresponding to each packet header through a result obtained by the function f under the currently maintained group package rule.
In this case, the second addressing address can be applied to the group packing rule as shown in fig. 2, i.e. as an offset address under the first addressing address; for example, in case the first addressing address has acknowledged address a, the second addressing address described above may be accurate to the third group of packet units in fig. 2.
As shown in fig. 6, a second packet rule maintenance method provided in this embodiment of the present invention is different from the first packet rule maintenance method described in the embodiment 1 with reference to fig. 2 in that packet units corresponding to each protocol are identified by relatively independent addresses, as shown in fig. 6, address a corresponds to a first packet unit, address B corresponds to a second packet unit, address C corresponds to a third packet unit, address D corresponds to a fourth packet unit, and address E corresponds to a fifth packet unit. At this time, for the architecture shown in fig. 4, the parallel execution of each group Packet processing Unit takes the form shown in fig. 7 (the group Packet Unit is represented as PHU in the figure, and is called Packet Header Unit all), where m is 3, i.e. it indicates that there are three types of elements of 1 byte, 2 bytes and 4 bytes, and then the corresponding element number b of each type of element 1 ＝K,b 2 ＝N，b 3 In the case of = M, the address D of the fourth group of cells in fig. 6 can be obtained by solving the function f (K, N, M).
Finally, in order to store the contents of the packet rules more flexibly in practical situations, a corresponding mapping relationship may be established between the calculation result of the function f and the actual address, that is, as long as it is ensured that the calculation result is unique in each packet header protocol, the mapping relationship may be used to establish an addressing relationship with the packet sub-rules in the actual SRAM.
In a specific operation process, if only the function f is used, and only the element class and the element number are introduced, so that the unique result value of the function f cannot be obtained, variables such as a hierarchy type, a packet header length and the like can be further introduced.
Example 2:
fig. 8 is a schematic diagram of an architecture of a parallel programmable group packer according to an embodiment of the present invention. The parallel programmable group packer of the present embodiment comprises one or more processors 21 and a memory 22. In fig. 8, one processor 21 is taken as an example.
The processor 21 and the memory 22 may be connected by a bus or other means, and fig. 8 illustrates the connection by a bus as an example.
The memory 22, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs and non-volatile computer-executable programs, such as the parallel programmable packaging method of embodiment 1. The processor 21 executes the parallel programmable packet packing method by executing non-volatile software programs and instructions stored in the memory 22.
The memory 22 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 22 may optionally include memory located remotely from the processor 21, which may be connected to the processor 21 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The program instructions/modules are stored in the memory 22 and, when executed by the one or more processors 21, perform the parallel programmable packet packing method of embodiment 1 described above, e.g., perform the various steps shown in fig. 1 and 3 described above.
It should be noted that, because the contents of information interaction, execution process, and the like between the group packaging device and the modules and units in the system are based on the same concept as the processing method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the embodiments may be performed by associated hardware as instructed by a program, which may be stored on a computer-readable storage medium, which may include: read Only Memory (ROM), random Access Memory (RAM), magnetic or optical disks, and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. A parallel programmable packet packing method is characterized in that a packet header vector is composed of all input data to be packed; the data to be packaged is divided into different element classes according to different byte lengths, and the method comprises the following steps:
acquiring the packet header vector, and generating a first addressing address according to the element classes contained in the packet header vector and the element quantity in each element class;
finding out a corresponding packet packing rule in a memory according to the first addressing address, and packing the data in the packet header vector according to the packet packing rule;
the group package processing module supports any 16 elements of 64 bytes to complete group package, wherein 64 bytes are divided into 16 containers with the size of 4 bytes, and the 4 bytes are the maximum value of the byte length in each element class;
the group package processing module puts each element analyzed from the group package unit into 16 containers with the size of 4 bytes;
the group packet processing module uses 15 selectors with one out of four to respectively correspond to the 16 containers with 4 bytes in size, data in the previous container is positioned by the selectors with one out of four to be connected in series after the effective data bit in the next container is positioned, and the effective data in the 16 th container is sequentially connected in series, so that the invalid data in each container is extruded, and a 64-byte real effective packet head section is formed; wherein the first selector corresponds from the second container;
wherein, the step of concatenating the valid data bits in the next container located by the one-out-of-four selector from the data in the previous container specifically comprises:
selecting a splicing position in a third container through a second selector, wherein the splicing position is a byte next to a valid byte bit in the third container; and splicing the spliced data in the first selector to the splicing position of the third container cached by the second selector, thereby obtaining the data content of the second selector.
2. The parallel programmable packet packing method according to claim 1, wherein the data to be packed in the packet header vector is arranged according to a nesting relationship of protocols of respective layers, and the packing of the data in the packet header vector according to the packing rule specifically includes:
splitting the packet header vector into one or more packet packing units according to the nesting relationship of each layer of protocol in the packet packing rule;
the split group package units are transmitted to each group package processing module in parallel;
and each group package processing module generates a second addressing address according to the acquired element classes contained in the group package unit and the element number in each element class, positions the second addressing address to a corresponding group package sub-rule in the group package rule, and completes the group package of the data in the group package unit according to the group package sub-rule.
3. A parallel programmable packet packing method according to claim 1 or 2, wherein the element class is set according to the type of byte length corresponding to each parameter included in the packet header vector; wherein the kind of the byte length at least comprises one or more of 1 byte, 2 bytes and 4 bytes.
4. A parallel programmable packetization method as in claim 1 in which 15 out-of-four selector operations, in response to squeezing out invalid data in each container, constitute a 64 byte true valid header fragment process, completed in one computer processing clock cycle.
5. A parallel programmable group packing method according to claim 1 or 4, characterized in that said containers are in particular registers.
6. A parallel programmable packet packing method according to claim 1, wherein n types of element classes are contained in said packet header vector, and the number of elements in the i-th element class is denoted by a i Wherein i ranges from 1 to n; generating a first addressing address according to the element classes contained in the packet header vector and the element numbers in each element class, specifically:
first addressing address = f (a) 1 ,a 2 ,...,a i )；
Wherein, f is a corresponding function, and is used for obtaining a unique value corresponding to each packet header through a result obtained by the function f under the currently maintained group package rule.
7. The parallel programmable group packaging method according to claim 2, wherein the group packaging unit obtained by the group packaging processing module specifically includes m types of element classes, and the number of elements in the jth type of element class is identified as b j Wherein j ranges from 1 to m; then, each group packet processing module generates a second addressing address according to the element class included in the obtained group packet unit and the number of elements in each element class, which specifically includes:
second addressing address = f (b) 1 ,b 2 ,...,b j )；
Wherein, f is a corresponding function, and is used for obtaining a unique value corresponding to each packet header through a result obtained by the function f under the currently maintained group package rule.
8. A parallel programmable group packing method according to claim 1, characterized in that the group packing unit comprises: one or more of IPv4, IPv6, ARP, eth, otag, and ptag.
9. A parallel programmable group packer, the group packer comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the parallel programmable group packaging method of any of claims 1-8.
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| WO2017024978A1 (en) * | 2015-08-13 | 2017-02-16 | 阿里巴巴集团控股有限公司 | Short message transmission and reception method and device |
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