CN113721989A

CN113721989A - Multiprocessor parallel operation system and computer architecture

Info

Publication number: CN113721989A
Application number: CN202110811048.0A
Authority: CN
Inventors: 陆放
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-07-19
Filing date: 2021-07-19
Publication date: 2021-11-30

Abstract

The invention relates to the technical field of computer architecture and software operating system, in particular to a multiprocessor parallel operating system and a computer architecture. The multiprocessor parallel operating system and the computer architecture provided by the invention have the advantages that different function groups can respectively and simultaneously cooperate to run various functions of the operating system, and simultaneously, because the software of each function group runs independently and simultaneously without interference, the speed can be greatly improved, and the traditional complex and low-efficiency operating system is divided into a plurality of simple function group software which are respectively independent and can simultaneously run efficiently, so that the simple and high-efficiency multiprocessor parallel operating system is formed.

Description

Multiprocessor parallel operation system and computer architecture

Technical Field

The invention relates to the technical field of computer architectures and software operating systems, in particular to a multiprocessor parallel operating system and a computer architecture.

Background

The current computer architecture and operating system are based on a single processor running a number of different programs in an interrupted manner, but suffer from the following disadvantages: 1. because the processor needs to save the environment state of the existing program before the processor switches to operate another program midway for returning the processor to continue operating and recovering the environment state for use, frequent switching wastes a large amount of processor time and memory, so that the operating efficiency of the system is greatly reduced; 2. operating systems have become very complex due to the problems of running numerous programs with different functions separately in time segments using a single processor, different programs having different priority and latency response times, and the like.

The operating system using a single processor to execute programs with different functions in a time-sharing manner in an interrupt mode is due to the fact that early chip technology lags behind and the processor is very expensive, but the advantages of the prior art cannot be brought into play by using the traditional computer architecture and the complex software operating system architecture due to the high development of the current chip technology.

In view of this, there is a need for improvements and enhancements in the prior art.

Disclosure of Invention

The invention aims to solve the defects of the prior art and provides a software operating system with simple and efficient structure and a corresponding computer architecture. The invention distributes the operating system function classification to a plurality of processors to run simultaneously respectively so as to avoid or reduce the frequent switching of the processors among different programs and greatly simplify the complexity of the software operating system.

In order to achieve the above object, the technical solution of the multiprocessor parallel operating system provided by the present invention is as follows:

a multi-processor parallel operating system that breaks down an operating system into functional groups according to its functionality, the functional groups comprising one or more operating system functions, each of the functional groups being run with one or more processors.

The invention also has the following preferable technical scheme:

further, the multiprocessor parallel operating system comprises a processor shared memory buffer used for issuing or receiving tasks and transmitting data.

Furthermore, the multiple processors can issue or receive tasks through the processor shared memory buffer, and can use multiple or one processor to complete one or multiple tasks through data transmission.

Further, the processors may each run various operating systems, which may be the same or different.

In another aspect of the present invention, a computer architecture is also provided, which includes the multiprocessor parallel operating system.

Advantageous effects of the invention

The multiprocessor parallel operating system and the computer architecture can comprise software and hardware of a user interface functional group, software and hardware of an application functional group, software and hardware of a large-capacity storage input and output functional group, software and hardware of a network connection functional group, software and hardware of a network browser functional group, software and hardware of an external device functional group and the like. Each functional group mutually communicates and coordinates to issue task transmission data and the like through a processor shared memory buffer area which can be read and written by each processor so as to complete tasks required by users. Thus, different function groups can respectively and simultaneously cooperate to run various functions of the operating system. The complexity is greatly reduced since the software of the respective functional groups only needs to perform a single or a few functions. Meanwhile, because the software of each function group runs independently and simultaneously without interference, the speed can be greatly improved, and the traditional complex and low-efficiency operating system is divided into a plurality of simple function group software which are independent and can run simultaneously and efficiently, thereby forming a simple and efficient multiprocessor parallel operating system. The system has several processors running different or same operating systems, including available traditional operating system, and thus has greatly raised system speed.

Drawings

FIG. 1 illustrates a structural schematic diagram of a computer architecture of the present invention.

Detailed Description

According to the above basic principles of multiprocessor parallel operating systems and computer architectures, there are many different designs, one of which is:

the design includes user interface function processor, application function processor(s), large capacity memory I/O function processor, network connection function processor, network tour processor and external equipment function processor. And task issuing and data exchange are carried out among the functional processors through the processor shared memory buffer area. The function processors run the functions as follows:

1. user interface function processor runs user interface operating system program to execute the following tasks

All user interface functions are run, including but not limited to the following:

A. the user input is read and displayed by presenting the user interface to the display function processor issuing the task.

B. And issuing related tasks to the related processors according to the input of the user and coordinating the operation of the function processing to complete the functions required by the user. Which interfaces with the various processors by issuing and receiving tasks and inputting and outputting data, etc. through the processor shared memory buffer.

2. The application function processor runs one or more applications requested to be run by a user, and receives tasks, input/output data and the like through the processor shared memory buffer to interface with each processor. It may be necessary to run other functional processors to issue tasks through the processor's shared memory buffer.

3. The display function processor includes a display memory to implement the display functions (which may include one or more displays) required by the system. Which interfaces with the various processors by accepting tasks and input/output data, etc. through the processor shared memory buffer. It can run other function processor to issue task through processor shared memory buffer area if necessary

4. The multi-interface high-speed memory (comprising a processor shared memory buffer area which can be read and written by each processor and is used for issuing or receiving tasks and transmitting data, a task issuing area and a data exchange area of each processor are respectively provided in the processor shared memory buffer area, the task issuing area comprises a task issuing instruction number, a task state number and the like, the task issuing instruction number comprises a required task type number, a processor number for executing the task, a data exchange address and the like, the task state number comprises a request type of the task, the task is completed during task execution, and the like), and the task and data handover among the processors and the required storage during the operation of the processors are provided.

5. The mass storage I/O function processor reads data from the mass storage (such as a hard disk and the like) to each processor or vice versa according to the task instruction. Which interfaces with the various processors by accepting tasks and input/output data, etc. through the processor shared memory buffer. It may be necessary to run other functional processors to issue tasks through the processor's shared memory buffer.

6. The network connection function processor processes all network connections (including WIFI and the like) and data transceiving functions. Which interfaces with the various processors by accepting tasks and input/output data, etc. through the processor shared memory buffer. It may be necessary to run other functional processors to issue tasks through the processor's shared memory buffer.

7. And the network browser function processor executes the network browser function. Which interfaces with the various processors by accepting tasks and input/output data, etc. through the processor shared memory buffer. It may be necessary to run other functional processors to issue tasks through the processor's shared memory buffer.

8. And the external equipment function processor is used for processing all external equipment functions. Which interfaces with the various processors by accepting tasks and input/output data, etc. through the processor shared memory buffer. It may be necessary to run other functional processors to issue tasks through the processor's shared memory buffer.

After the system is powered on, each processor (user interface removal processor) respectively starts to run a respective operating system to scan the shared memory buffer of the processor until a task request is found, and then a relevant task program is run.

The user interface processor starts to run an operating system of the user interface processor, then scans the user input and the shared memory buffer area of the processor, if the user input is found, the user input is carried out according to the input of the user, the related sub-processors are assigned with tasks by setting a task state number of an instruction number and the like in the shared memory buffer area of the processor, the data are mutually transmitted with the related processors according to the requirement to complete the task required by the user, and the task state number is set to be in a completion state after the task is completed. If other processors have task requests for the user interface processor, the user interface processor performs corresponding processing according to the request type to complete the request.

The application processor can be one or more than one application which can run one or more than one different application at the same time, and the application processor downloads and runs the application after receiving the task and the application program address through the shared memory buffer of the processor. When the functions needing to be processed by other processors are met in operation, tasks are issued through the shared memory buffer of the processors, and data are transmitted to and from the related sub-processors according to needs. Each processor may also issue tasks and communicate data to and from the associated processor as needed through the processor's shared memory buffer as needed for its other processor functions. Thus, multiple processors can issue or receive tasks and perform data transmission between each other through the processor shared memory buffer, so that multiple or one processor can be used to complete one or more tasks.

Compared with the prior art, the method and the device distribute the functions of the operating system to the function processors for execution, thereby greatly simplifying the complexity of the operating system. The operating systems are distributed in each functional processor to independently run in parallel, and switching is very simple without switching back and forth among different programs, so that tasks can be completed at high speed without a high-performance processor. The software system run by each processor is not complex because of single function or few functions, and each functional processor does not need high-performance devices except for the application functional processor which needs higher-performance devices. The overall computer speed will be greatly increased. I.e., processors that can be produced using a few levels of lower chip technology, can reach and even exceed the computer speed of existing processors produced using the highest level of chip technology. Thereby greatly reducing the production cost and the requirement for high-grade chip technology.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims

1. A multi-processor parallel operating system which decomposes an operating system into functional groups according to its functions, the functional groups including one or more operating system functions, each of the functional groups being run with one or more processors.

2. A multiprocessor parallel operating system according to claim 1, comprising a processor shared memory buffer for issuing or accepting tasks and transferring data.

3. A multiprocessor parallel operating system according to claim 1, wherein the processors can issue or receive tasks to or from each other via a processor shared memory buffer, and data transfer is performed to enable one or more processors to complete one or more tasks.

4. A multiprocessor parallel operating system according to claim 1, wherein the processors are each operable to run the same or different operating systems.

5. A computer architecture comprising a multiprocessor parallel operating system as claimed in any one of claims 1 to 4.