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CN113690318B - Longitudinal BCD device and preparation method thereof - Google Patents

Longitudinal BCD device and preparation method thereof Download PDF

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CN113690318B
CN113690318B CN202111237759.8A CN202111237759A CN113690318B CN 113690318 B CN113690318 B CN 113690318B CN 202111237759 A CN202111237759 A CN 202111237759A CN 113690318 B CN113690318 B CN 113690318B
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hvpw
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CN113690318A (en
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刘雯娇
杨世红
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Shaanxi Reactor Microelectronics Co ltd
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Shaanxi Reactor Microelectronics Co ltd
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Abstract

The invention provides a longitudinal BCD device and a preparation method thereof, and mainly solves the problems that the existing LDMOSFET drain electrode region is large in occupied area, large in on-resistance and poor in VDMOSFET compatibility. According to the invention, the deep P well HVPW is added in the CMOS device region of the longitudinal BCD device, so that a diode is formed between the HVPW and the N-type epitaxial layer N-EPI. When the VDMOSFET device is operating normally, the diode formed between the N-EPI and the HVPW is turned off in the reverse direction, and reverse breakdown cannot occur. The arrangement avoids the influence on the CMOS device in the BCD when the voltage is applied to the drain electrode of the VDMOSFET.

Description

Longitudinal BCD device and preparation method thereof
Technical Field
The invention relates to the technical field of monolithic integration processes, in particular to a longitudinal BCD device and a preparation method thereof.
Background
The BCD (BIPOLAR-CMOS-DMOS) integration process is a single-chip integration process technology, and BIPOLAR transistors, CMOS (complementary metal oxide semiconductor field effect transistors) and DMOSFET (double-diffused metal oxide semiconductor field effect transistors) devices are simultaneously manufactured on the same chip. It integrates the advantages of each device, and has good performance when each device is self-standing. The integrated BCD process can greatly reduce power consumption, improve system performance, save cost and have better reliability.
There are two main types of DMOSFETs: a lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET and a vertical double-diffused metal oxide semiconductor field effect transistor VDMOSFET. At present, a relatively mature BCD process is a planar structure, and a DMOSFET compatible with the planar structure process generally adopts an LDMOSFET. When the LDMOSFET is required to achieve a high breakdown voltage, a drift region (a drift region has a low impurity concentration) needs to be designed in the structure, so that the drain region occupies a large area, and the on-resistance of the device is increased. The VDMOSFET has very high withstand voltage, a longitudinal structure, a drain electrode led out from the back of a wafer, unsuitability for combination with an integrated circuit with a planar structure and poor compatibility.
Disclosure of Invention
The invention aims to solve the problems of large occupied area, larger on-resistance and poorer compatibility of a conventional LDMOSFET drain region, and provides a structure of a longitudinal BCD device and a preparation method thereof.
In order to achieve the purpose, the invention adopts the following technical scheme:
a vertical BCD device comprises
An N-type substrate;
an N-type epitaxial layer formed on the upper surface of the N-type substrate;
an oxide layer formed on the N-type epitaxial layer through local oxidation isolation;
a P-Body region and an HVPW region are sequentially arranged in the N-type epitaxial layer; the implanted ions of the P-Body region and the HVPW region are both P-type ions;
an N + contact region is arranged on the upper surface of the P-Body region to form a source electrode of the VDMOSFET device, a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Body region and on one side of the N + contact region from bottom to top, and the gate oxide layer and the polycrystalline silicon layer partially cover the upper surface of the P-Body region to form a grid electrode of the VDMOSFET device;
the drain electrode of the VDMOSFET device is led out from the back surface of the N-type substrate;
a P-Well region and an N-Well region are sequentially arranged in the HVPW region; the implanted ions of the P-Well area are P-type ions, and the implanted ions of the N-Well area are N-type ions;
the upper surface of the P-Well area is provided with two N + contact areas to form a drain electrode and a source electrode of an NMOS (N-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Well area and between the two N + contact areas to form a gate electrode of the NMOS device in the CMOS;
the upper surface of the N-Well area is provided with two P + contact areas to form a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the N-Well area and between the two P + contact areas to form a gate electrode of the PMOS device in the CMOS;
and P + contact regions are respectively arranged on the upper surface of the HVPW region, the left region of the P-Well region and the right region of the N-Well region to form a leading-out terminal of the HVPW.
Further, an HVNW area is arranged in the HVPW area, the HVNW area is positioned on the right side of the P-Well area, the N-Well area is arranged in the HVNW area, and N + contact areas are respectively arranged on the upper surface of the HVNW area and on the left side and the right side of the N-Well area to form an outlet of the HVNW.
Further, the resistivity of the N-type substrate is 0.002-0.004 ohm cm.
Furthermore, the thickness of the N-type epitaxial layer is 6.4-6.8 um, and the resistivity is 1.0-1.2 ohm cm.
Furthermore, the oxide layer is isolated through LOCOS local oxidation, and the thickness of the oxide layer is 7600-9300 angstroms.
The preparation method of the longitudinal BCD device comprises the following steps:
step one, selecting an N-type substrate with a crystal orientation of <100 >;
growing an N-type epitaxial layer on an N-type substrate;
performing a local oxidation process on the surface of the N-type epitaxial layer to realize local oxidation isolation and form an oxide layer;
forming an HVPW region in the N-type epitaxial layer by using a photomask of the HVPW through a photoetching process, and implanting boron ions into the HVPW region through an ion implantation process;
fifthly, forming an ion implantation area of the P-Well through a photoetching process by utilizing a photomask of the P-Well, and performing P-type ion implantation on the ion implantation area to form a P-Well area; forming an N-Well ion implantation area by using an N-Well photomask through a photoetching process, and performing N-type ion implantation on the N-Well ion implantation area to form an N-Well area; wherein the process sequence of the N-Well region and the P-Well region can be interchanged;
growing a gate oxide layer on the N-type epitaxial layer, depositing a polycrystalline silicon layer on the gate oxide layer, defining a gate region by using a photomask of a gate through a photoetching process, and etching the polycrystalline silicon layer of the gate to form gates of a VDMOSFET device, a PMOS device in a CMOS and an NMOS device;
forming a P-Body ion implantation area by using a P-Body photomask through a self-aligned photoetching process, and performing P-type ion implantation on the P-Body ion implantation area to form a P-Body area;
step eight, respectively utilizing N + photomasks to form an N + ion implantation area in a P-Body area and a P-Well area through a self-aligned photoetching process, carrying out N-type ion implantation on the N + ion implantation area to form an N + contact area, and forming a source electrode of a VDMOSFET device and a drain electrode and a source electrode of an NMOS device in a CMOS; forming a P + ion implantation area in the N-Well area and the HVPW area by utilizing a P + photomask through a self-aligned photoetching process, performing P-type ion implantation on the P + ion implantation area to form a P + contact area, and respectively forming a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS and a leading-out end of the HVPW area; wherein the process sequence of the N + contact region and the P + contact region can be interchanged;
step nine, forming an intermediate medium layer, a contact hole and a metal layer;
and step ten, thinning the lower end face of the N-type substrate according to the back face thinning process of the VDMOSFET device, gilding the thinned lower end face, and leading out the drain electrode of the VDMOSFET device from the lower end face of the N-type substrate.
Further, after forming the HVPW region in step four, the method further comprises the step of forming an HVNW region: forming an HVNW region in the HVPW region by using a mask of the HVNW deep N well through a photoetching process, and then performing ion implantation on the HVNW region;
in the eighth step, an N + ion implantation area is formed in the P-Body area, the P-Well area and the HVNW area through a self-aligned photoetching process by utilizing an N + photomask respectively, N-type ion implantation is carried out on the N + ion implantation area to form an N + contact area, and a source electrode of a VDMOSFET device, a drain electrode and a source electrode of an NMOS device in a CMOS and a leading-out end of the HVNW are formed; and forming a P + ion implantation area in the N-Well area and the HVPW area by utilizing a P + photomask through a self-aligned photoetching process, performing P-type ion implantation on the P + ion implantation area to form a P + contact area, and respectively forming a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS and a leading-out end of the HVPW area. Wherein the process sequence of the N + contact region and the P + contact region can be interchanged;
further, the HVNW region is implanted with phosphorus at an ion implantation energy of 70-90 KeV and at an ion implantation dose of 8E13cm-2~9.5E13cm-2。
Furthermore, in the fourth step, the ion implantation energy of the HVPW region is 80-100 KeV, and the ion implantation dose is 1.7E13cm-2~2.0E13cm-2。
Further, in the tenth step, the thickness of the thinned back surface of the wafer is 150-180 um, and the gold-plated material is Ti/Ni/Ag.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention provides a longitudinal BCD device, wherein a DMOSFET of the device adopts a VDMOSFET, and a drain electrode is led out from the back surface of the BCD device. Under the same withstand voltage, the structure not only can greatly reduce the area of the chip and improve the utilization rate of the chip, but also can reduce the on-resistance.
2. According to the invention, the deep P well HVPW is added in the CMOS device region of the longitudinal BCD device, so that a diode is formed between the HVPW and the N-type epitaxial layer N-EPI. When the VDMOSFET device is operating normally, the diode formed between the N-EPI and the HVPW is turned off in the reverse direction, and reverse breakdown cannot occur. The arrangement avoids the influence on the CMOS device in the BCD when the voltage is applied to the drain electrode of the VDMOSFET.
3. The vertical BCD device is additionally provided with a layer of HVNW deep N-type Well, the HVNW deep N-type Well regulates the reverse voltage withstanding of a diode formed between the HVPW and the HVNW, and the vertical BCD device is mainly used for preventing the diode formed between the N-Well and the HVPW of the PMOS in the CMOS from being reversely broken down to influence the normal work of the PMOS.
Drawings
Fig. 1 is a schematic structural diagram of a vertical BCD device according to a first embodiment of the invention;
FIG. 2 is a schematic diagram of a second step in a method for fabricating a vertical BCD device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a third step in a method for fabricating a vertical BCD device according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a fourth step in a method for fabricating a vertical BCD device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of step five of a method for manufacturing a vertical BCD device according to an embodiment of the invention;
fig. 6 is a sixth schematic diagram of a method for manufacturing a vertical BCD device according to an embodiment of the invention;
fig. 7 is a seventh schematic diagram of a method for manufacturing a vertical BCD device according to an embodiment of the invention;
fig. 8 is a schematic diagram illustrating an eighth step in a method for manufacturing a vertical BCD device according to an embodiment of the invention;
fig. 9 is a ninth schematic diagram of a step in a method for manufacturing a vertical BCD device according to an embodiment of the invention;
fig. 10 is a ten-step schematic diagram of a method for fabricating a vertical BCD device according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of a vertical BCD device according to a second embodiment of the present invention;
fig. 12 is a schematic view of a third step in the method for manufacturing a vertical BCD device according to the second embodiment of the present invention;
fig. 13 is a schematic diagram of step four in the method for manufacturing a vertical BCD device according to the second embodiment of the present invention;
fig. 14 is a schematic diagram of step eight in the method for manufacturing a vertical BCD device according to the second embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention and are not intended to limit the scope of the present invention.
The invention provides a longitudinal BCD device, wherein a DMOSFET of the longitudinal BCD device adopts a VDMOSFET, and a drain electrode is led out from the back surface of the BCD device. Under the same withstand voltage, the structure not only can greatly reduce the area of the chip and improve the utilization rate of the chip, but also can reduce the on-resistance.
Example one
Fig. 1 is a schematic structural diagram of a vertical BCD device, which takes an N-type planar VDMOSFET device as an example, and may also be a VDMOSFET device with a structure such as a trench or a super junction. The vertical BCD device can realize the effects of reducing the on-resistance and the area of a chip, but has a problem that the voltage applied to the drain electrode of the VDMOSFET can influence the CMOS device in the BCD device. Therefore, it is necessary to increase the deep P-well HVPW in the CMOS device area so that a diode is formed between the HVPW and the N-EPI. When the VDMOSFET device normally works, the diode formed between the N-EPI and the HVPW is reversely cut off, and reverse breakdown cannot occur, so that the reverse breakdown voltage of the diode formed between the N-EPI and the HVPW is required to be larger than the breakdown voltage of the VDMOSFET. In addition, the structure is a realization process for adding a layer of deep P well HVPW to the CMOS device region on the basis of a VDMOSFET device, and the process generally adopts the following steps: photoetching, etching and ion implantation (or diffusion), the existing process technology is mature, the implementation is relatively simple, and the difficulty of the process is not increased. In the figure, G1 is the gate of a VDMOSFET device; d1 is the drain of VDMOSFET device; s1 is the source of the VDMOSFET device; g2 is the grid of NMOS device in CMOS; d2 is the drain of the NMOS device in the CMOS; s2 is the source of the NMOS device in the CMOS; g3 is the grid of PMOS device in CMOS; d3 is the drain of PMOS device in CMOS; s3 is the source of the PMOS device in the CMOS; VC1 is the outlet of HVPW. The specific structure of the vertical BCD device in this embodiment is as follows, including:
an N-type substrate;
an N-type epitaxial layer formed on the upper surface of the N-type substrate;
an oxide layer formed on the upper surface of the N-type epitaxial layer through local oxidation isolation;
a P-Body region and an HVPW region are sequentially arranged in the N-type epitaxial layer; the implanted ions of the P-Body region and the HVPW region are P-type ions;
an N + contact region is arranged on the upper surface of the P-Body region to form a source electrode of the VDMOSFET device, a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Body region and on one side of the N + contact region from bottom to top, and the gate oxide layer and the polycrystalline silicon layer partially cover the upper surface of the P-Body region to form a grid electrode of the VDMOSFET device;
the drain electrode of the VDMOSFET device is led out from the back surface of the N-type substrate;
a P-Well region and an N-Well region are sequentially arranged in the HVPW region; the implanted ions in the P-Well area are P-type ions, and the implanted ions in the N-Well area are N-type ions;
two N + contact areas are arranged on the upper surface of the P-Well area to form a drain electrode and a source electrode of an NMOS (N-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Well area and between the two N + contact areas to form a gate electrode of the NMOS device in the CMOS;
two P + contact areas are arranged on the upper surface of the N-Well area to form a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the N-Well area and between the two P + contact areas to form a gate electrode of the PMOS device in the CMOS;
and P + contact regions are respectively arranged on the upper surface of the HVPW region, the left region of the P-Well region and the right region of the N-Well region to form a leading-out terminal of the HVPW.
The preparation method of the longitudinal BCD device comprises the following steps:
selecting an N-type substrate with a crystal orientation of <100> according to the electrical requirements of a VDMOSFET device, wherein the resistivity of the N-type substrate is about 0.002-0.004 ohm cm;
growing an N-EPI (N-EPI-layer) on an N-type substrate, wherein the thickness and the resistivity of the N-EPI are determined by the source-drain breakdown voltage and the on-resistance of the VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor), the thickness of the N-EPI is 6.4-6.8 um, and the resistivity is 1.0-1.2 ohm cm, as shown in figure 2;
performing a local oxidation process on the N-EPI to realize LOCOS local oxidation isolation, wherein the thickness of an oxidation layer is 7600-9300 angstroms, as shown in FIG. 3;
step four, firstly, forming an HVPW ion implantation area by using a photomask of the HVPW through a photoetching process, and then, carrying out ion implantation on the HVPW area through the ion implantation process, wherein ions implanted by the HVPW are boron, the implantation energy is 80-100 KeV, and the implantation dose is 1.7E13cm-2~2.0 E 13cm-2As shown in fig. 4;
step five, forming a back grid region in the CMOS device, wherein the NMOS device forms a P-Well ion implantation region through a photoetching process by utilizing a P-Well photomask, and performs P-type ion implantation to the P-Well ion implantation region to form a P-Well region; the PMOS device utilizes a photomask of N-Well to form an ion implantation area of the N-Well through a photoetching process, and N-type ion implantation is carried out on the ion implantation area to form the N-Well area. Wherein the process sequence for the P-Well region and the N-Well region can be interchanged, as shown in FIG. 5;
growing a gate oxide layer, depositing a polycrystalline silicon layer on the gate oxide layer, defining a gate region by using a photomask of the gate through a photoetching process, and removing redundant gate oxide layers and polycrystalline silicon through an etching process to form gates of a VDMOSFET device, a PMOS device in a CMOS and an NMOS device, as shown in FIG. 6;
step seven, forming a back grid region in the VDMOSFET device, forming a P-Body ion implantation region through a self-aligned photoetching process by utilizing a P-Body photomask, and performing P-type ion implantation on the P-Body ion implantation region to form a P-Body region, wherein the P-Body region is shown in figure 7;
step eight, respectively utilizing N + photomasks to form an N + ion implantation area in a P-Body area and a P-Well area through a self-aligned photoetching process, carrying out N-type ion implantation on the N + ion implantation area to form an N + contact area, and forming a source electrode of a VDMOSFET device and a drain electrode and a source electrode of an NMOS device in a CMOS; and forming a P + ion implantation area in the N-Well area and the HVPW area by utilizing a P + photomask through a self-aligned photoetching process, performing P-type ion implantation on the P + ion implantation area to form a P + contact area, and respectively forming a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS and a leading-out end of the HVPW area. Wherein the process sequence of the N + contact region and the P + contact region may be interchanged, as shown in fig. 8;
step nine, the subsequent processes are conventional processes, such as the formation of an intermediate dielectric layer, a contact hole, a metal layer and the like, and all the processes of the front surface of the wafer are completed, as shown in fig. 9;
step ten, thinning the back of the wafer according to a back thinning process of the VDMOS, wherein the thinned thickness is about 150-180 um, plating gold on the wafer after thinning, wherein the gold-plated material is Ti/Ni/Ag, and the drain D1 of the VDMOS is led out from the back of the wafer, as shown in FIG. 10.
Example two
In the embodiment, on the basis of the longitudinal BCD device in the first embodiment, an HVNW deep N-type Well is added, and the main function is to prevent a diode formed between N-Well and HVPW of PMOS in CMOS from being in reverse breakdown and influencing the normal operation of PMOS. Since N-Well is mainly used for adjusting the channel parameter of PMOS, and at the same time, it is difficult to take into account the reverse voltage resistance of HVPW, a layer of HVNW deep N Well is added to adjust the reverse voltage resistance of the diode formed between HVPW and HVPW, and the reverse voltage resistance must be larger than the breakdown voltage resistance of PMOS. As shown in fig. 11, VC2 is an outlet of the HVNW, and the specific structure of the vertical BCD device in this embodiment is as follows:
an N-type substrate;
an N-type epitaxial layer formed on the upper surface of the N-type substrate;
an oxide layer formed on the upper surface of the N-type epitaxial layer through local oxidation isolation;
a P-Body region and an HVPW region are sequentially arranged in the N-type epitaxial layer; the implanted ions of the P-Body region and the HVPW region are P-type ions;
an N + contact region is arranged on the upper surface of the P-Body region to form a source electrode of the VDMOSFET device, a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Body region and on one side of the N + contact region, and the gate oxide layer and the polycrystalline silicon layer partially cover the upper surface of the P-Body region to form a grid electrode of the VDMOSFET device; the drain electrode of the VDMOSFET device is led out from the back surface of the N-type substrate;
a P-Well region and an HVNW region are arranged in the HVPW region, the HVNW region is positioned at the right side of the P-Well region, and the N-Well region is arranged in the HVNW region; the implanted ions in the P-Well area are P-type ions, and N-type ions are implanted in the N-Well area;
two N + contact areas are arranged on the upper surface of the P-Well area to form a drain electrode and a source electrode of an NMOS (N-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Well area and between the two N + contact areas to form a gate electrode of the NMOS device in the CMOS; n + contact regions are respectively arranged on the upper surface of the HVNW region and on the left side and the right side of the N-Well region, and form leading-out terminals of the HVNW.
Two P + contact areas are arranged on the upper surface of the N-Well area to form a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the N-Well area and between the two P + contact areas to form a gate electrode of the PMOS device in the CMOS;
and P + contact regions are respectively arranged on the upper surface of the HVPW region, the left region of the P-Well region and the right region of the N-Well region to form a leading-out terminal of the HVPW.
The vertical BCD device in the embodiment is additionally provided with a layer of HVNW deep N-type Well on the basis of the structure of the embodiment, and the main function of the vertical BCD device is to prevent a diode formed between N-Well and HVPW of PMOS in CMOS from being in reverse breakdown and influencing the normal operation of the PMOS. Since N-Well is mainly used for adjusting the channel parameter of PMOS, and at the same time, it is difficult to take into account the reverse voltage resistance of HVPW, a layer of HVNW deep N Well is added to adjust the reverse voltage resistance of the diode formed between HVPW and HVPW, and the reverse voltage resistance must be larger than the breakdown voltage resistance of PMOS.
The method for manufacturing the vertical BCD device in this embodiment includes the steps of:
selecting an N-type substrate with a crystal orientation of <100> according to the electrical requirements of a VDMOSFET device, wherein the resistivity of the N-type substrate is about 0.002-0.004 ohm cm;
growing N-EPI of an N-type epitaxial layer on the N-type substrate, wherein the thickness and the resistivity of the N-EPI are determined by the source-drain breakdown voltage and the on-resistance of the VDMOSFET device, the thickness of the N-type epitaxial layer is 6.4-6.8 um, and the resistivity is 1.0-1.2 ohm cm;
step three, as shown in fig. 12, performing a local oxidation isolation process on the N-EPI to realize LOCOS local oxidation isolation, wherein the LOCOS oxidation isolation region is increased for realizing isolation of the HVNW from the PMOS;
step four, firstly, forming an HVPW ion implantation area by using a photomask of the HVPW through a photoetching process, and then, carrying out ion implantation on the HVPW area through an ion implantation process, wherein ions implanted by the HVPW are boron, the implantation energy is 80-100 KeV, and the implantation dosage is 1.7E13cm-2~2.0E13cm-2；
As shown in fig. 13, after forming the HVPW region, a mask of an HVNW deep N-well is added, the HVNW region is formed by photolithography, and then the HVNW region is ion-implanted by ion implantation, wherein the ion implanted by the HVNW is phosphorus, the implantation energy is 70-90 KeV, and the implantation dose is 8E13cm-2~9.5E13cm-2；
Step five, forming a back grid region in the CMOS device, wherein the NMOS device forms a P-Well ion implantation region through a photoetching process by utilizing a P-Well photomask, and performs P-type ion implantation to the P-Well ion implantation region to form the P-Well region; forming an N-Well ion implantation area by the PMOS device through a photomask of the N-Well by a photoetching process, and performing N-type ion implantation on the N-Well ion implantation area to form an N-Well area; wherein the process sequence of the P-Well region and the N-Well region can be interchanged;
growing a gate oxide layer, depositing a polycrystalline silicon layer on the gate oxide layer, defining a gate region by using a photomask of the gate through a photoetching process, and removing redundant gate oxide layers and polycrystalline silicon layers through an etching process to form gates of a VDMOSFET device, a PMOS device in a CMOS and an NMOS device;
forming a back grid region in the VDMOSFET device, forming a P-Body ion implantation region by utilizing a P-Body photomask through a self-aligned photoetching process, and performing P-type ion implantation on the P-Body ion implantation region to form a P-Body region;
step eight, as shown in fig. 14, forming N + ion implantation regions in the P-Body region, the P-Well region and the HVNW region by using N + photomasks through a self-aligned photolithography process, and performing N-type ion implantation to form N + contact regions, thereby forming a source of the VDMOSFET device, a drain and a source of an NMOS device in the CMOS, and a leading-out terminal of the HVNW; forming a P + ion implantation area in the N-Well area and the HVPW area by utilizing a P + photomask through a self-aligned photoetching process, performing P-type ion implantation on the P + ion implantation area to form a P + contact area, and respectively forming a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS and a leading-out end of the HVPW area; wherein the process sequence of the N + contact region and the P + contact region can be interchanged;
step nine, the subsequent processes are conventional processes, such as the formation of an intermediate dielectric layer, a contact hole, a metal layer and the like, and all the processes of the front surface of the wafer are completed;
step ten, thinning the back of the wafer according to a back thinning process of the VDMOSFET device, wherein the thinned thickness is about 150-180 um, carrying out gold plating on the wafer after thinning, wherein the gold plated material is Ti/Ni/Ag, and the drain D1 of the VDMOSFET is led out from the back of the wafer.

Claims (6)

1. A vertical BCD device, comprising: comprises that
An N-type substrate;
an N-type epitaxial layer formed on the upper surface of the N-type substrate;
an oxide layer formed on the N-type epitaxial layer through local oxidation isolation;
a P-Body region and an HVPW region are sequentially arranged in the N-type epitaxial layer; the implanted ions of the P-Body region and the HVPW region are both P-type ions;
an N + contact region is arranged on the upper surface of the P-Body region to form a source electrode of the VDMOSFET device, a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Body region and on one side of the N + contact region from bottom to top, and the gate oxide layer and the polycrystalline silicon layer partially cover the upper surface of the P-Body region to form a grid electrode of the VDMOSFET device;
the drain electrode of the VDMOSFET device is led out from the back surface of the N-type substrate;
a P-Well region and an N-Well region are sequentially arranged in the HVPW region; the implanted ions of the P-Well area are P-type ions, and the implanted ions of the N-Well area are N-type ions;
the upper surface of the P-Well area is provided with two N + contact areas to form a drain electrode and a source electrode of an NMOS (N-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the P-Well area and between the two N + contact areas to form a gate electrode of the NMOS device in the CMOS;
the upper surface of the N-Well area is provided with two P + contact areas to form a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS, and a gate oxide layer and a polycrystalline silicon layer are arranged on the upper surface of the N-Well area and between the two P + contact areas to form a gate electrode of the PMOS device in the CMOS;
p + contact areas are respectively arranged on the upper surface of the HVPW area, in the left area of the P-Well area and in the right area of the N-Well area, so as to form a leading-out end of the HVPW; a diode is formed between the HVPW region and the N-type epitaxial layer, when the VDMOSFET device works normally, the diode formed between the N-type epitaxial layer and the HVPW region is cut off in a reverse direction and cannot break down in the reverse direction, and the reverse breakdown voltage of the diode formed between the N-type epitaxial layer and the HVPW region is larger than the breakdown voltage of the VDMOSFET;
an HVNW region is arranged in the HVPW region, the HVNW region is positioned on the right side of the P-Well region, the N-Well region is arranged in the HVNW region, and N + contact regions are respectively arranged on the upper surface of the HVNW region and on the left side and the right side of the N-Well region to form an outlet of the HVNW; the HVNW region is used for adjusting the reverse withstand voltage of a diode formed between the N-Well region and the HVPW region and preventing the diode formed between the N-Well region and the HVPW region of the PMOS in the CMOS from reverse breakdown;
the resistivity of the N-type substrate is 0.002-0.004 ohm cm;
the thickness of the N-type epitaxial layer is 6.4-6.8 um, and the resistivity is 1.0-1.2 ohm cm;
the oxide layer is isolated through LOCOS local oxidation, and the thickness of the oxide layer is 7600-9300 angstroms.
2. A method of fabricating a vertical BCD device according to claim 1, comprising the steps of:
step one, selecting an N-type substrate with a crystal orientation of <100 >;
growing an N-type epitaxial layer on an N-type substrate;
performing a local oxidation process on the surface of the N-type epitaxial layer to realize local oxidation isolation and form an oxide layer;
forming an HVPW region in the N-type epitaxial layer by using a photomask of the HVPW through a photoetching process, and implanting boron ions into the HVPW region through an ion implantation process;
fifthly, forming an ion implantation area of the P-Well through a photoetching process by utilizing a photomask of the P-Well, and performing P-type ion implantation on the ion implantation area to form a P-Well area; forming an N-Well ion implantation area by using an N-Well photomask through a photoetching process, and performing N-type ion implantation on the N-Well ion implantation area to form an N-Well area;
growing a gate oxide layer on the N-type epitaxial layer, depositing a polycrystalline silicon layer on the gate oxide layer, defining a gate region by using a photomask of a gate through a photoetching process, and etching the polycrystalline silicon layer of the gate to form gates of a VDMOSFET device, a PMOS device in a CMOS and an NMOS device;
forming a P-Body ion implantation area by using a P-Body photomask through a self-aligned lithography process, and performing P-type ion implantation on the P-Body ion implantation area to form a P-Body area;
step eight, respectively utilizing N + photomasks to form an N + ion implantation area in a P-Body area and a P-Well area through a self-aligned photoetching process, carrying out N-type ion implantation on the N + ion implantation area to form an N + contact area, and forming a source electrode of a VDMOSFET device and a drain electrode and a source electrode of an NMOS device in a CMOS; forming a P + ion implantation area in the N-Well area and the HVPW area by utilizing a P + photomask through a self-aligned photoetching process, performing P-type ion implantation on the P + ion implantation area to form a P + contact area, and respectively forming a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS and a leading-out end of the HVPW area;
step nine, forming an intermediate medium layer, a contact hole and a metal layer;
step ten, thinning the lower end face of the N-type substrate according to the back face thinning process of the VDMOSFET device, plating gold on the thinned lower end face, and leading out the drain electrode of the VDMOSFET device from the lower end face of the N-type substrate.
3. The method of claim 2, wherein: after forming the HVPW region in step four, further comprising the step of forming an HVNW region: forming an HVNW region in the HVPW region by using a mask of the HVNW deep N well through a photoetching process, and then performing ion implantation on the HVNW region;
in the eighth step, an N + ion implantation area is formed in the P-Body area, the P-Well area and the HVNW area through a self-aligned photoetching process by using a photomask of N +, an N + contact area is formed by carrying out N-type ion implantation on the N + ion implantation area, and a source electrode of the VDMOSFET device, a drain electrode and a source electrode of an NMOS device in the CMOS and a leading-out end of the HVNW are formed; and forming a P + ion implantation area in the N-Well area and the HVPW area by utilizing a P + photomask through a self-aligned photoetching process, performing P-type ion implantation on the P + ion implantation area to form a P + contact area, and respectively forming a drain electrode and a source electrode of a PMOS (P-channel metal oxide semiconductor) device in the CMOS and a leading-out end of the HVPW area.
4. The production method according to claim 3, characterized in that: the HVNW region is implanted with phosphorus, the ion implantation energy is 70-90 KeV, and the ion implantation dosage is 8E13cm-2~9.5E13cm-2。
5. The method of claim 4, wherein: in the fourth step, the ion implantation energy of the HVPW region is 80-100 KeV, and the ion implantation dose is 1.7E13cm-2~2.0E13cm-2。
6. The method of claim 5, wherein: in the tenth step, the thickness of the thinned back surface of the wafer is 150-180 um, and the gold-plated material is Ti/Ni/Ag.
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