CN113629141B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113629141B CN113629141B CN202010373406.XA CN202010373406A CN113629141B CN 113629141 B CN113629141 B CN 113629141B CN 202010373406 A CN202010373406 A CN 202010373406A CN 113629141 B CN113629141 B CN 113629141B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure comprises: a substrate; a composite nanowire structure located on the surface of the substrate, the composite nanowire structure including a first region, a second region located on the first region, and a plurality of first nanowires and a plurality of second nanowires arranged in a direction perpendicular to the surface of the substrate, the plurality of first nanowires being located in the first region, the plurality of second nanowires being located in the second region, gaps being provided between the plurality of first nanowires, between the plurality of second nanowires, between adjacent first and second nanowires, and between the substrate and first nanowires, and a width of the first nanowires being smaller than a width of the second nanowires in an extension direction of the first nanowire channel; and the source-drain doping layers are positioned on the surface of the substrate and on two sides of the composite nanowire structure. Thus, the performance of the semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.
Background
With further advances in semiconductor technology, integrated circuit devices are becoming smaller in size, and conventional fin field effect transistors (finfets) have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a gate-all-around (GAA) structure field effect transistor is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin type field effect transistor with the channel gate-around structure is further increased, thereby improving the performance of the semiconductor device.
However, the performance of semiconductor devices is still in need of improvement.
Disclosure of Invention
The invention provides a semiconductor structure and a method for forming the semiconductor structure, which aims to improve the performance of the semiconductor structure. .
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a composite nanowire structure located on the surface of the substrate, the composite nanowire structure including a first region, a second region located on the first region, and a plurality of first nanowires and a plurality of second nanowires arranged in a direction perpendicular to the surface of the substrate, the plurality of first nanowires being located in the first region, the plurality of second nanowires being located in the second region, gaps being provided between the plurality of first nanowires, between the plurality of second nanowires, between adjacent first and second nanowires, and between the substrate and first nanowires, and a width of the first nanowires being smaller than a width of the second nanowires in an extension direction of the first nanowire channel; and the source-drain doping layers are positioned on the surface of the substrate and on two sides of the composite nanowire structure.
Optionally, the source-drain doped layer includes a first source-drain doped layer covering the first region, and a second source-drain doped layer covering the second region, wherein a first ion is provided in the first source-drain doped layer, a second ion is provided in the second source-drain doped layer, and a conductivity type of the first ion is the same as a conductivity type of the second ion.
Optionally, the concentration of the first ion ranges from 5.0e20atom/cm 3～4.0e21atom/cm3; the concentration of the second ion ranges from 2.0e21atom/cm 3～8.0e21atom/cm3, and the concentration of the second ion is greater than the concentration of the first ion.
Optionally, the method further comprises: and the electric interconnection structure is positioned on the surface of the second source-drain doped layer.
Optionally, the ratio of the width of the first nanowire to the width of the second nanowire ranges from 1/3 to 2/3.
Optionally, the width of the first nanowire ranges from 1 nm to 10 nm.
Optionally, the width of the second nanowire ranges from 1 nm to 15 nm.
Optionally, the substrate surface has a fin structure, and the composite nanowire structure is located on a top surface of the fin structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a composite nanowire structure on the surface of the substrate, wherein the composite nanowire structure comprises a first region, a second region located on the first region, a plurality of first nanowires and a plurality of second nanowires which are arranged in a direction vertical to the surface of the substrate, the plurality of first nanowires are located in the first region, the plurality of second nanowires are located in the second region, gaps are formed among the plurality of first nanowires, among the plurality of second nanowires, between adjacent first nanowires and second nanowires and between the substrate and the first nanowires, and in the extending direction of the first nanowire channel, the width of the first nanowires is smaller than the width of the second nanowires; and after the composite nanowire structure is formed, forming source-drain doped layers positioned on two sides of the composite nanowire structure on the surface of the substrate.
Optionally, the source-drain doped layer includes a first source-drain doped layer covering the first region, and a second source-drain doped layer covering the second region, wherein a first ion is provided in the first source-drain doped layer, a second ion is provided in the second source-drain doped layer, a conductivity type of the first ion is the same as a conductivity type of the second ion, and a concentration of the second ion is greater than a concentration of the first ion.
Optionally, the method for forming the source-drain doped layer includes: forming an initial source-drain doped layer on the surface of the substrate and the side-by-side surface of the composite nanowire structure, wherein the initial source-drain doped layer is internally provided with the first ions; and carrying out a first ion implantation process on the initial source-drain doped layer of the second region.
Optionally, the process parameters of the first ion implantation process include: the implantation angle of the ions ranges from 7 degrees to 25 degrees, and the implantation angle is the direction of the implantation direction and the normal line of the surface of the substrate; the dose range for ion implantation was 8.0e14atom/cm 2～1.0e16atom/cm2.
Optionally, the method further comprises: and after the source-drain doped layer is formed, forming an electric interconnection structure on the surface of the second source-drain doped layer.
Optionally, the method of forming the composite nanowire structure includes: forming a plurality of initial nanowires on the substrate, and sacrificial layers between adjacent initial nanowires and between the initial nanowires and the surface of the substrate; forming a third side wall on the side wall of the initial nanowire in the second region; and etching the initial nanowire of the first region by taking the third side wall as a mask.
Optionally, the method further comprises: and after the sacrificial layer is formed and before the third side wall is formed, forming a first side wall on the side wall surface of the sacrificial layer.
Optionally, the method for forming the third side wall includes: forming an initial third side wall on the side wall surfaces of the initial nanowires and the side wall surfaces of the first side walls; modifying the initial third side wall of the second region; and after the initial third side wall of the second region is subjected to modification treatment, etching the initial third side wall to remove the initial third side wall of the first region and form the third side wall.
Optionally, the process of modifying the initial third sidewall of the second region includes a second ion implantation process, and process parameters of the second ion implantation process include: the implantation angle of the ions ranges from 7 degrees to 25 degrees, and the implantation angle is the direction of the implantation direction and the normal line of the surface of the substrate.
Optionally, the method further comprises: and forming a pseudo gate structure on the surface of the composite nanowire structure before forming the third side wall, wherein the pseudo gate structure spans the composite nanowire structure.
Optionally, the dummy gate structure includes: the device comprises a pseudo gate positioned on the surface of the composite nanowire structure, a second side wall positioned on the side wall of the pseudo gate and a pseudo gate barrier layer positioned on the top surface of the pseudo gate.
Optionally, the method further comprises: and removing the sacrificial layer and the dummy gate structure after the source-drain doped layer is formed, so as to form a gate structure on the surface of the composite nanowire structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
In the semiconductor structure provided by the technical scheme of the invention, the source-drain doped layer with higher ion concentration is formed in the first region later, and the source-drain doped layer with lower ion concentration is formed in the second region later. Because the composite nanowire structure comprises a plurality of first nanowires positioned in the first region and a plurality of second nanowires positioned in the second region, and the width of the first nanowires is smaller than that of the second nanowires in the extending direction of the first nanowire channels, on one hand, the second nanowires with larger widths can increase the length of the channels, reduce Schottky barriers and interface resistances aiming at source-drain doped layers with high ion concentration, thereby reducing short channel effects and improving the performance of the semiconductor structure; on the other hand, the first nanowire with smaller width is aimed at the source-drain doped layer with lower ion concentration, so that the length of the first nanowire is reduced while short channel effect is not easy to generate, and parasitic resistance on the first nanowire is reduced, and the performance of the semiconductor structure is improved.
Further, the second source-drain doped layer located in the second region is in contact with the electrical interconnection structure, and since the first source-drain doped layer is provided with first ions, the second source-drain doped layer is provided with second ions, and the concentration of the second ions is larger than that of the first ions, contact resistance generated between the second source-drain doped layer and the electrical interconnection structure can be reduced by increasing the concentration of the ions in the second source-drain doped layer, and therefore performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure;
fig. 2 to 11 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices is still in need of improvement. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure.
Referring to fig. 1, the method includes: a substrate 100, wherein the substrate 100 is provided with a fin structure, and the fin structure comprises a plurality of nanowires 101; a gate structure surrounding the first nanowire 101, the gate structure comprising a gate dielectric layer 103, a work function layer 104 located on the gate dielectric layer 103, and a gate layer 105 located on the work function layer 104; side walls 106 located on the side walls of the gate structures; source-drain doped layers 107 located in the fin portions on both sides of the gate structure; a dielectric layer 102 on the substrate, wherein the gate structure is located in the dielectric layer 102; an electrical interconnect structure (not shown) is located within the dielectric layer 108, the electrical interconnect structure being electrically interconnected with the source drain doped layer 107.
Therefore, through the electric interconnection structure, the source-drain doped layer and the outside can be electrically interconnected, so that the circuit design requirement is met.
However, in the above embodiment, in order to reduce the parasitic resistance between the source-drain doped layer 107 and the electrical interconnection structure, the ion concentration of the top region of the source-drain doped layer 107 is increased, so that the nanowire 101 located between the top regions of the source-drain doped layer 107 is affected by the higher ion concentration, and a short channel effect is easily generated, thereby resulting in poor performance of the semiconductor structure.
In order to solve the above problems, the present invention provides a semiconductor structure, including: a substrate; a composite nanowire structure located on the surface of the substrate, the composite nanowire structure including a first region, a second region located on the first region, and a plurality of first nanowires and a plurality of second nanowires arranged in a direction perpendicular to the surface of the substrate, the plurality of first nanowires being located in the first region, the plurality of second nanowires being located in the second region, gaps being provided between the plurality of first nanowires, between the plurality of second nanowires, between adjacent first and second nanowires, and between the substrate and first nanowires, and a width of the first nanowires being smaller than a width of the second nanowires in an extension direction of the first nanowire channel; and the source-drain doping layers are positioned on the surface of the substrate and on two sides of the composite nanowire structure. Thereby improving the performance of the semiconductor structure.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 11 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2 and 3, fig. 2 is a schematic cross-sectional view of the X-X1 direction in fig. 3, and a substrate 200 is provided.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Wherein the multi-component semiconductor material formed by III-V elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the surface of the substrate 200 has a fin structure 201.
In this embodiment, a number of initial nanowire material layers 211 are formed on the substrate 200, and initial sacrificial material layers 210 are located between adjacent initial nanowire material layers 211 and between the initial nanowire material layers 211 and the surface of the substrate 200. Specifically, the several initial nanowire material layers 211 are formed on the fin structure 201, and initial sacrificial material layers 210 are located between adjacent initial nanowire material layers 211 and between the initial nanowire material layers 211 and the top surface of the fin structure 201.
The initial nanowire material layer 211 is used for forming initial nanowires later, and the initial nanowires are used for forming a composite nanowire structure, wherein the composite nanowire structure comprises a first nanowire and a second nanowire, the composite nanowire structure comprises a first region I and a second region II positioned on the first region I in a direction perpendicular to the surface of the substrate 200, and the first nanowire is positioned in the first region I, and the second nanowire is positioned in the second region II.
The initial sacrificial material layer 210 is used for subsequent formation of an initial sacrificial layer and a sacrificial layer.
In this embodiment, the material of the initial nanowire material layer 211 comprises polysilicon and the material of the initial sacrificial material layer 210 comprises silicon germanium. The silicon germanium and the monocrystalline silicon have a larger etching selectivity ratio, so that the first nanowire and the second nanowire are not damaged by an etching process when the sacrificial layer is removed later.
In this embodiment, the method for forming the fin structure 201, the initial nanowire material layer 211, and the initial sacrificial material layer 210 includes: forming a plurality of first material layers (not shown) on the surface of the substrate 200, and second material layers (not shown) between adjacent first material layers and between the first material layers and the surface of the substrate 200; forming a first mask layer on the top surface of the first material layer part; the first material layer, the second material layer and a portion of the substrate 200 are etched with the first mask layer as a mask until an opening (not shown) is formed in the substrate 200 to form a fin structure 201 on the surface of the substrate 200, and the initial nanowire material layers 211 and the initial sacrificial material layer 210 are formed on the fin structure 201.
The first material layer is used to form the initial nanowire material layer 211.
The second material layer is used to form the initial sacrificial material layer 210.
In this embodiment, the process of forming the first material layer includes a deposition process or an epitaxial growth process, and the deposition process includes a chemical vapor deposition process or an atomic layer deposition process, and the like.
In this embodiment, the process of forming the second material layer includes a deposition process including a chemical vapor deposition process, an atomic layer deposition process, or the like, an epitaxial growth process, a spin-on process, or an oxidation process including a thermal oxidation process, or the like.
In this embodiment, the process of etching the first material layer, the second material layer, and the substrate 200 includes a dry etching process or a wet etching process.
In this embodiment, after the fin structure 201 is formed, the first mask layer is removed.
In this embodiment, after the openings are formed, a first dielectric layer 202 is formed within the openings.
The first dielectric layer 202 is used for isolating current between adjacent semiconductor devices on one hand, and protecting the substrate 200 and the fin layer 201 on the other hand, so that the influence of the formation process in the subsequent semiconductor structure forming process on the substrate 200 and the fin layer 201 is reduced.
The material of the first dielectric layer 202 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
In this embodiment, the material of the first dielectric layer 202 is silicon oxide.
The process of forming the first dielectric layer 202 includes a deposition process or a spin-on process.
Referring to fig. 4 on the basis of fig. 2, a dummy gate structure 220 is formed on the surfaces of the initial nanowire material layer 211 and the initial sacrificial material layer 210, and the dummy gate structure 220 exposes a portion of the surfaces of the initial nanowire material layer 211 and the initial sacrificial material layer 210; the initial nanowire material layer 211 and the initial sacrificial material layer 210 are etched using the dummy gate structure 220 as a mask until the surface of the substrate 200 is exposed to form initial nanowires 213 and initial sacrificial layers 212.
The initial nanowire 213 is used to form a first nanowire and a second nanowire.
The initial sacrificial layer 212 is used to form a sacrificial layer.
In this embodiment, with the dummy gate structure 220 as a mask, the process of etching the initial nanowire material layer 211 and the initial sacrificial material layer 210 includes one or both of a dry etching process and a wet etching process.
In this embodiment, the dummy gate structure 220 includes: a dummy gate 221 on a portion of the surface of the initial nanowire material layer 211 and a portion of the surface of the initial sacrificial material layer 210, a second sidewall 222 on a sidewall of the dummy gate 221, and a dummy gate barrier 223 on a top surface of the dummy gate 221.
The dummy gate structure 220 spans the initial nanowire material layers 211 and the initial sacrificial material layers 210.
In this embodiment, the method for forming the dummy gate structure 220 includes: forming a dummy gate dielectric material layer (not shown) on the surface of the initial nanowire material layer 211, the surface of the initial sacrificial material layer 210 and the surface of the first dielectric layer 202; forming a dummy gate electrode material layer (not shown) on the dummy gate dielectric material layer; forming a dummy gate barrier material layer (not shown) on the dummy gate electrode material layer; forming a patterned second mask layer (not shown) on the dummy gate barrier material layer (not shown); etching the dummy gate barrier material layer, the dummy gate electrode material layer and the dummy gate dielectric material layer by using the patterned second mask layer as a mask until the surface of the initial nanowire material layer 211, the surface of the initial sacrificial material layer 210 and the surface of the first dielectric layer 202 are exposed, thereby forming the dummy gate 221 and the dummy gate barrier layer 223; after the dummy gate 221 is formed, the second mask layer is removed; after the second mask layer is removed, a second sidewall material layer (not shown) is formed on the surface of the first dielectric layer 202, the surface of the initial nanowire material layer 211, the surface of the initial sacrificial material layer 210, the sidewall surface of the dummy gate 221, and the surface of the dummy gate barrier layer 223; and etching the second side wall material layer until the surface of the initial nanowire material layer 211, the surface of the initial sacrificial material layer 210, the surface of the first dielectric layer 202 and the top surface of the dummy gate barrier layer 223 are exposed, and forming a second side wall 222 on the side wall of the dummy gate 221.
In this embodiment, the material of the dummy gate barrier layer 223 is different from the material of the second sidewall 222.
In this embodiment, the material of the dummy gate barrier layer 223 includes silicon oxide or silicon nitride; the material of the pseudo gate dielectric material layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride; the material of the pseudo gate electrode material layer comprises polysilicon or metal; the material of the second side wall 222 includes at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride.
In this embodiment, the process of forming the dummy gate barrier material layer, the dummy gate dielectric material layer, and the second sidewall material layer includes an atomic layer deposition process or a chemical vapor deposition process; the process for forming the pseudo gate electrode material layer comprises an atomic layer deposition process or a physical vapor deposition process; and the process of etching the pseudo gate blocking material layer, the pseudo gate electrode material layer, the pseudo gate dielectric material layer and the second side wall material layer comprises a dry etching process or a wet etching process.
Referring to fig. 5, after forming the initial nanowire 213 and the initial sacrificial layer 212, a portion of the initial sacrificial layer 212 is etched to form a sacrificial layer 214 having sidewalls recessed with respect to sidewalls of the initial nanowire 213.
Specifically, after the sacrificial layer 214 is formed, a first sidewall opening (not shown) is provided between adjacent initial nanowires 213.
In this embodiment, the process of etching a portion of the initial sacrificial layer 212 includes a dry etching process or a wet etching process.
In this embodiment, after the sacrificial layer 214 is formed, a first sidewall 230 is formed on a sidewall surface of the sacrificial layer 214. Specifically, the first sidewall 230 is formed in the first sidewall opening.
The first side wall 230 is used for supporting and limiting the space after the sacrificial layer 214 is removed later, so that the space is used for forming a gate structure.
In this embodiment, the method for forming the first sidewall 230 includes: forming a first sidewall material layer (not shown) on the surface of the dummy gate structure 220, the surface of the first dielectric layer 202, the surface of the initial nanowire 213, the surface of the sacrificial layer 214, and in the first sidewall opening; the first sidewall material layer is etched back until the surface of the first dielectric layer 202 is exposed.
In this embodiment, the process of forming the first sidewall material layer is an atomic layer deposition process.
The process of etching the first side wall material layer comprises a dry etching process or a wet etching process.
In this embodiment, the process of etching the first sidewall material layer is a dry etching process.
The material of the first sidewall 230 includes at least one of silicon nitride, silicon oxynitride and silicon carbonitride boride.
In this embodiment, the material of the first sidewall 230 is silicon nitride.
The subsequent step of forming a third sidewall on the sidewall of the initial nanowire 213 in the second region II is shown in fig. 6 to 8.
Referring to fig. 6, after the first side wall 230 is formed, an initial third side wall 240 is formed on the side wall surfaces of the plurality of initial nanowires 213 and the side wall surface of the first side wall 230.
Specifically, in this embodiment, the initial third sidewall 240 is further formed on a sidewall surface of the dummy gate structure 220.
In this embodiment, the material of the initial third sidewall 240 includes silicon oxide.
In this embodiment, the method for forming the initial third sidewall 240 includes: forming an initial third sidewall material layer (not shown) on the surface of the dummy gate structure 220, the surface of the initial nanowire 213, the surface of the sacrificial layer 214, the surface of the first dielectric layer 202, and the surface of the first sidewall 230; forming a patterned third mask layer on the surface of part of the initial third side wall material layer; and etching the initial third sidewall material layer by taking the patterned third mask layer as a mask until the first dielectric layer 202 is exposed.
In this embodiment, after the initial third sidewall 240 is formed, the patterned third mask layer is removed.
In this embodiment, the process of forming the initial third sidewall material layer includes a deposition process or a spin-coating process.
In this embodiment, the process of etching the initial third sidewall material layer includes a dry etching process or a wet etching process.
In this embodiment, after the initial third sidewall 240 is formed, a third sidewall spacer 250 is formed on the surface of the substrate 200 and the sidewall surface of the initial third sidewall 240 of the first region I.
Therefore, by the third sidewall barrier 250, when the initial third sidewall 240 of the second region II is modified later, the initial third sidewall 240 of the first region I can be protected to reduce the influence of the modification on the initial third sidewall 240 of the first region I, so that when the initial third sidewall 240 is etched later to form a third sidewall, the initial third sidewall 240 of the first region I and the initial third sidewall 240 of the second region II have different etching rates by the modification, thereby forming a third sidewall.
In this embodiment, the method for forming the third sidewall spacer 250 includes: forming a third sidewall barrier material layer (not shown) on the surface of the dummy gate structure 220, the surface of the initial nanowire 213, the surface of the sacrificial layer 214, the surface of the substrate 200, and the surface of the initial third sidewall 240; and etching the third side wall blocking material layer until the side wall of the initial third side wall 240 of the second region II is exposed.
In this embodiment, the process of forming the third sidewall barrier material layer includes a deposition process or a spin-coating process.
In this embodiment, the process of etching the third sidewall spacer material layer includes a dry etching process or a wet etching process.
In this embodiment, the material of the third sidewall spacer 250 includes an organic material, for example, a carbon-containing organic material.
Referring to fig. 7, after the third sidewall barrier 250 is formed, the initial third sidewall of the second region II is modified.
In this embodiment, the process of modifying the initial third sidewall 240 of the second region II includes a second ion implantation process.
The process parameters of the second ion implantation process include: the implanted ions are silicon ions.
Thus, by having the initial third sidewall 240 of the first region I and the initial third sidewall 240 of the second region II have different silicon ion concentrations, it is achieved that the etching process has different etching rates for the initial third sidewall 240 of the first region I and the initial third sidewall 240 of the second region II when the initial third sidewall 240 is subsequently etched.
The process parameters of the second ion implantation process further include: the implantation angle of the ions ranges from 7 degrees to 25 degrees, and the implantation angle is the direction of the implantation direction and the normal line of the surface of the substrate; the dose range for ion implantation was 8.0e14atom/cm 2～2.0e16atom/cm2.
In this embodiment, after the modification treatment is performed on the initial third sidewall 240 of the second region II, the third sidewall barrier 250 is removed.
Referring to fig. 8, after removing the third sidewall spacer 250, the initial third sidewall 240 is etched to remove the initial third sidewall 240 of the first region I, thereby forming a third sidewall 241.
The process of removing the initial third sidewall 240 includes a wet etching process or a dry etching process.
Referring to fig. 9, after the third sidewall 241 is formed, the initial nanowire 213 of the first region I is etched with the third sidewall 241 as a mask, so as to form the composite nanowire structure 217.
The composite nanowire structure 216 includes the first region I, a second region II located on the first region I, and a plurality of first nanowires 215 and a plurality of second nanowires 216 arranged in a direction perpendicular to a surface of the substrate 200, the plurality of first nanowires 215 being located in the first region I, the plurality of second nanowires 216 being located in the second region II, gaps (not shown) being provided between the plurality of first nanowires 215, between the plurality of second nanowires 216, between adjacent first and second nanowires 215 and 216, and between the substrate 200 and the first nanowires 215, and a width a of the first nanowires 215 being smaller than a width B of the second nanowires 216 in an extending direction of a channel of the first nanowires 215.
In this embodiment, a source-drain doped layer with a higher ion concentration is formed in the first region I, and a source-drain doped layer with a lower ion concentration is formed in the second region II. Because the composite nanowire structure 217 includes a plurality of first nanowires 215 located in the first region I and a plurality of second nanowires 216 located in the second region II, and the width a of the first nanowires 215 is smaller than the width B of the second nanowires 216 in the extending direction of the channels of the first nanowires 215, on one hand, the second nanowires 216 with larger width B can increase the length of the channels, reduce schottky barrier and reduce interface resistance for the source-drain doped layer with high ion concentration, thereby reducing short channel effects and improving the performance of the semiconductor structure; on the other hand, the first nanowire 215 with smaller width a is used for the source-drain doped layer with lower ion concentration, and the length of the first nanowire 215 is reduced while short channel effect is not easy to generate, so that parasitic resistance on the first nanowire 215 is reduced, and the performance of the semiconductor structure is improved.
It should be noted that fig. 9 only schematically shows one first nanowire 215 in the first region I, and schematically shows one second nanowire 216 in the second region II. The number of first nanowires 215 in the first region I is any integer multiple of 1 or more, and the number of second nanowires 216 in the second region II is any integer multiple of 1 or more, the number of first nanowires 215 and the number of second nanowires 216 not affecting the effect of the present solution.
Specifically, in the present embodiment, the first nanowire 215 is formed by etching the initial nanowire 213 of the first region I, and the initial nanowire 213 located in the second region II is the second nanowire 216.
Specifically, in this embodiment, before the source-drain doped layer is formed later, the sacrificial layer 214 and the first sidewall 230 are located in the gap.
Specifically, in the present embodiment, after the composite nanowire structure 217 is formed, the dummy gate of the dummy gate structure 220 is located on the surface of the composite nanowire structure 217, and the dummy gate structure 220 spans the composite nanowire structure 217.
In this embodiment, the ratio of the width A of the first nanowire 215 to the width B of the second nanowire 216 is in the range of 1/3 to 2/3.
In this embodiment, the width a of the first nanowire 215 ranges from 1 nm to 10 nm.
If the width a is too wide, the parasitic resistance of the first nanowire 215 is higher, which is not beneficial to improving the performance of the semiconductor structure; if the width a is too short, the first nanowire 215 may have a short channel effect, which is also disadvantageous for improving the performance of the semiconductor structure. Accordingly, selecting an appropriate range of width a, i.e., within the above-described range of width a, enables the first nanowire 215 to reduce parasitic resistance of the first nanowire 215 while overcoming short channel effects, thereby improving performance of the semiconductor structure.
More preferably, the width a of the first nanowire 215 ranges from 2 nm to 5 nm.
In this embodiment, the width B of the second nanowire 216 ranges from 1 nm to 15 nm.
If the width B is too wide, the parasitic resistance is excessively increased while the second nanowire 216 is satisfied to overcome the short channel effect, which is not beneficial to improving the performance of the semiconductor structure; too short a width B is detrimental to overcoming the possible short channel effect of the second nanowire 216 for the source-drain doped layer with high ion concentration, and also to improving the performance of the semiconductor structure. Therefore, selecting a suitable range of the width B, that is, within the range of the width B, the parasitic resistance of the second nanowire 216 can be reduced while overcoming the short channel effect for the source-drain doped layer with high ion concentration, thereby improving the performance of the semiconductor structure.
More preferably, the width B of the second nanowire 216 ranges from 3 nm to 8 nm.
In this embodiment, after the composite nanowire structure 217 is formed, the third sidewall 241 is removed.
Referring to fig. 10, after the composite nanowire structure 217 is formed, source-drain doped layers 260 are formed on the surface of the substrate 200 at both sides of the composite nanowire structure 217.
Specifically, in this embodiment, after removing the third sidewall 241, the source-drain doped layer 260 is formed.
In this embodiment, the source-drain doped layer 260 includes a first source-drain doped layer 261 covering the first region I, and a second source-drain doped layer 262 covering the second region II, where the first source-drain doped layer 261 has a first ion therein, the second source-drain doped layer 262 has a second ion therein, the conductivity type of the first ion is the same as that of the second ion, and the concentration of the second ion is greater than that of the first ion.
The second source-drain doped layer 262 located in the second region II is in contact with a subsequently formed electrical interconnection structure, and since the first source-drain doped layer 261 has the first ions therein and the second source-drain doped layer 262 has the second ions therein, and the concentration of the second ions is greater than that of the first ions, the contact resistance generated between the second source-drain doped layer 262 and the electrical interconnection structure can be reduced by increasing the concentration of the ions in the second source-drain doped layer 262, thereby improving the performance of the semiconductor structure.
In this embodiment, the first ion type includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an antimony ion, and the P-type ion includes a boron ion or an indium ion; the source/drain doped layer 290 is made of phosphorus silicon, antimony silicon, boron silicon or indium silicon.
In this embodiment, the method for forming the source-drain doped layer 260 includes: forming an initial source-drain doped layer (not shown) on the surface of the substrate 200 and on the side of the composite nanowire structure 217, wherein the initial source-drain doped layer is provided with the first ions; and carrying out a first ion implantation process on the initial source-drain doped layer of the second region II.
Specifically, in this embodiment, the initial source-drain doped layer that is subjected to the first ion implantation process is the second source-drain doped layer 262, and the initial source-drain doped layer that is not subjected to the first ion implantation process is the first source-drain doped layer 261.
The process parameters of the first ion implantation process include: the implantation angle of the ions ranges from 7 degrees to 25 degrees, and the implantation angle is the direction of the implantation direction and the normal line of the surface of the substrate; the dose range for ion implantation was 8.0e14atom/cm 2～1.0e16atom/cm2.
Referring to fig. 11, after the source-drain doped layer 260 is formed, the sacrificial layer 214 and the dummy gate structure 220 are removed to form a gate structure 270 on the surface of the composite nanowire structure 217.
Specifically, the gate structure 270 surrounds the first nanowire 215 and the second nanowire 216, and the source-drain doped layer 260 is located at both sides of the gate structure 270.
In the present embodiment, the dummy gate barrier layer 223 is removed before the sacrificial layer 214 is removed; removing the dummy gate while removing the sacrificial layer 214; the gate structure 270 is positioned between the gap and the dummy gate sidewall 222 such that the gate structure 270 surrounds the composite nanowire structure 217.
The gate structure 270 includes a gate dielectric layer 271, a work function layer 272 on the gate dielectric layer 271, and a gate 273 on the work function layer 272.
In this embodiment, after the source-drain doped layer 260 is formed, an electrical interconnection structure (not shown) is formed on the surface of the second source-drain doped layer 262.
The electrical interconnect structure is electrically interconnected with the second source drain doped layer 262.
In this embodiment, the material of the electrical interconnect structure includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above forming method, referring to fig. 11, including: a substrate 200; a composite nanowire structure 217 located at a surface of the substrate 200, the composite nanowire structure 217 including a first region I, a second region II located on the first region I, and a plurality of first nanowires 215 and a plurality of second nanowires 216 arranged in a direction perpendicular to the surface of the substrate 200, the plurality of first nanowires 215 being located at the first region I, the plurality of second nanowires 216 being located at the second region II, gaps (not shown) being present between the plurality of first nanowires 215, between the plurality of second nanowires 216, between adjacent first and second nanowires 215 and 216, and between the substrate 200 and first nanowires 215, and a width a of the first nanowires 215 being smaller than a width B of the second nanowires 216 in an extending direction of the channels of the first nanowires 215; source-drain doped layers 260 located on the surface of the substrate 200 and on both sides of the composite nanowire structure 217.
In this embodiment, a source-drain doped layer with a higher ion concentration is formed in the first region I, and a source-drain doped layer with a lower ion concentration is formed in the second region II. Because the composite nanowire structure 217 includes a plurality of first nanowires 215 located in the first region I and a plurality of second nanowires 216 located in the second region II, and the width a of the first nanowires 215 is smaller than the width B of the second nanowires 216 in the extending direction of the channels of the first nanowires 215, on one hand, the second nanowires 216 with larger width B can increase the length of the channels, reduce schottky barrier and reduce interface resistance for the source-drain doped layer with high ion concentration, thereby reducing short channel effects and improving the performance of the semiconductor structure; on the other hand, the first nanowire 215 with smaller width a is used for the source-drain doped layer with lower ion concentration, and the length of the first nanowire 215 is reduced while short channel effect is not easy to generate, so that parasitic resistance on the first nanowire 215 is reduced, and the performance of the semiconductor structure is improved.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Wherein the multi-component semiconductor material formed by III-V elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the surface of the substrate 200 has a fin structure 201, and the composite nanowire structure 217 is located on the top surface of the fin structure 202.
In this embodiment, the source-drain doped layer 260 includes a first source-drain doped layer 261 covering the first region I, and a second source-drain doped layer 262 covering the second region II, where the first source-drain doped layer 261 has a first ion therein, the second source-drain doped layer 262 has a second ion therein, the conductivity type of the first ion is the same as that of the second ion, and the concentration of the second ion is greater than that of the first ion.
The second source-drain doped layer 262 located in the second region II is in contact with a subsequently formed electrical interconnection structure, and since the first source-drain doped layer 261 has the first ions therein and the second source-drain doped layer 262 has the second ions therein, and the concentration of the second ions is greater than that of the first ions, the contact resistance generated between the second source-drain doped layer 262 and the electrical interconnection structure can be reduced by increasing the concentration of the ions in the second source-drain doped layer 262, thereby improving the performance of the semiconductor structure.
In this embodiment, the concentration of the first ion is in the range of 5.0e20atom/cm 3～4.0e21atom/cm3; the concentration of the second ion is in the range of 2.0e21atom/cm 3～8.0e21atom/cm3.
In this embodiment, the first ion type includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an antimony ion, and the P-type ion includes a boron ion or an indium ion; the source/drain doped layer 290 is made of phosphorus silicon, antimony silicon, boron silicon or indium silicon.
In this embodiment, the ratio of the width A of the first nanowire 215 to the width B of the second nanowire 216 is in the range of 1/3 to 2/3.
In this embodiment, the width a of the first nanowire 215 ranges from 1 nm to 10 nm.
More preferably, the width a of the first nanowire 215 ranges from 2 nm to 5 nm.
In this embodiment, the width B of the second nanowire 216 ranges from 1 nm to 15 nm.
More preferably, the width B of the second nanowire 216 ranges from 3 nm to 8 nm.
In this embodiment, the semiconductor structure further includes: an electrical interconnect structure (not shown) is located on a surface of the second source drain doped layer 262.
The electrical interconnect structure is electrically interconnected with the second source drain doped layer 262.
In this embodiment, the material of the electrical interconnect structure includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the semiconductor structure further includes: a gate structure 270 located at a surface of the composite nanowire structure 217, and the gate structure 270 surrounds the composite nanowire structure 217.
The gate structure 270 includes a gate dielectric layer 271, a work function layer 272 on the gate dielectric layer 271, and a gate 273 on the work function layer 272.
In this embodiment, the semiconductor structure further includes: the first sidewall 230 is located between the gate structure 270 and the source/drain doped layer 260.
In this embodiment, the sidewalls of the first sidewall 230 are flush with respect to the sidewalls of the second nanowire 262.
In another embodiment, the sidewall of the first sidewall protrudes relative to the sidewall of the second nanowire.
The material of the first sidewall 230 includes at least one of silicon nitride, silicon oxynitride and silicon carbonitride boride.
In this embodiment, the material of the first sidewall 230 is silicon nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
a substrate;
A composite nanowire structure located on the surface of the substrate, the composite nanowire structure including a first region, a second region located on the first region, and a plurality of first nanowires and a plurality of second nanowires arranged in a direction perpendicular to the surface of the substrate, the plurality of first nanowires being located in the first region, the plurality of second nanowires being located in the second region, gaps being provided between the plurality of first nanowires, between the plurality of second nanowires, between adjacent first and second nanowires, and between the substrate and first nanowires, and a width of the first nanowires being smaller than a width of the second nanowires in an extension direction of the first nanowire channel;
the source-drain doping layers are positioned on the surface of the substrate and on two sides of the composite nanowire structure;
The source-drain doping layer comprises a first source-drain doping layer covering the first region and a second source-drain doping layer covering the second region, wherein first ions are arranged in the first source-drain doping layer, second ions are arranged in the second source-drain doping layer, and the conductivity type of the first ions is the same as that of the second ions;
the concentration of the second ion is greater than the concentration of the first ion.
2. The semiconductor structure of claim 1, wherein a concentration of the first ions ranges from 5.0e20 atoms/cm 3～4.0e21atom/cm3; the concentration of the second ion is in the range of 2.0e21atom/cm 3～8.0e21 atom/cm3.
3. The semiconductor structure of claim 1, further comprising: and the electric interconnection structure is positioned on the surface of the second source-drain doped layer.
4. The semiconductor structure of claim 1, wherein a ratio of a width of the first nanowire to a width of the second nanowire ranges from 1/3 to 2/3.
5. The semiconductor structure of claim 1, wherein the first nanowire has a width in a range of 1 nm to 10 nm.
6. The semiconductor structure of claim 1, wherein the second nanowire has a width in the range of 1 nm to 15 nm.
7. The semiconductor structure of claim 1, in which the substrate surface has a fin structure, the composite nanowire structure being located on a top surface of the fin structure.
8. A method of forming a semiconductor structure, comprising:
Providing a substrate;
Forming a composite nanowire structure on the surface of the substrate, wherein the composite nanowire structure comprises a first region, a second region located on the first region, a plurality of first nanowires and a plurality of second nanowires which are arranged in a direction vertical to the surface of the substrate, the plurality of first nanowires are located in the first region, the plurality of second nanowires are located in the second region, gaps are formed among the plurality of first nanowires, among the plurality of second nanowires, between adjacent first nanowires and second nanowires and between the substrate and the first nanowires, and in the extending direction of the first nanowire channel, the width of the first nanowires is smaller than the width of the second nanowires;
After the composite nanowire structure is formed, forming source-drain doped layers positioned on two sides of the composite nanowire structure on the surface of the substrate;
The source-drain doping layer comprises a first source-drain doping layer covering the first region and a second source-drain doping layer covering the second region, wherein first ions are arranged in the first source-drain doping layer, second ions are arranged in the second source-drain doping layer, and the conductivity type of the first ions is the same as that of the second ions;
the concentration of the second ion is greater than the concentration of the first ion.
9. The method of forming a semiconductor structure of claim 8, wherein the method of forming the source drain doped layer comprises: forming an initial source-drain doped layer on the surface of the substrate and the side wall surface of the composite nanowire structure, wherein the initial source-drain doped layer is internally provided with the first ions; and carrying out a first ion implantation process on the initial source-drain doped layer of the second region.
10. The method of forming a semiconductor structure of claim 9, wherein the process parameters of the first ion implantation process comprise: the implantation angle of the ions ranges from 7 degrees to 25 degrees, and the implantation angle is the direction of the implantation direction and the normal line of the surface of the substrate; the dose range for ion implantation was 8.0e14atom/cm 2～1.0e16 atom/cm2.
11. The method of forming a semiconductor structure of claim 8, further comprising: and after the source-drain doped layer is formed, forming an electric interconnection structure on the surface of the second source-drain doped layer.
12. The method of forming a semiconductor structure of claim 8, wherein the method of forming the composite nanowire structure comprises: forming a plurality of initial nanowires on the substrate, and sacrificial layers between adjacent initial nanowires and between the initial nanowires and the surface of the substrate; forming a third side wall on the side wall of the initial nanowire in the second region; and etching the initial nanowire of the first region by taking the third side wall as a mask.
13. The method of forming a semiconductor structure of claim 12, further comprising: and after the sacrificial layer is formed and before the third side wall is formed, forming a first side wall on the side wall surface of the sacrificial layer.
14. The method of forming a semiconductor structure of claim 13, wherein the method of forming the third sidewall comprises: forming an initial third side wall on the side wall surfaces of the initial nanowires and the side wall surfaces of the first side walls; modifying the initial third side wall of the second region; and after the initial third side wall of the second region is subjected to modification treatment, etching the initial third side wall to remove the initial third side wall of the first region and form the third side wall.
15. The method of forming a semiconductor structure of claim 14, wherein the process of modifying the initial third sidewall of the second region comprises a second ion implantation process, the process parameters of the second ion implantation process comprising: the implantation angle of the ions ranges from 7 degrees to 25 degrees, and the implantation angle is the direction of the implantation direction and the normal line of the surface of the substrate.
16. The method of forming a semiconductor structure of claim 12, further comprising: and forming a pseudo gate structure on the surface of the composite nanowire structure before forming the third side wall, wherein the pseudo gate structure spans the composite nanowire structure.
17. The method of forming a semiconductor structure of claim 16, wherein the dummy gate structure comprises: the device comprises a pseudo gate positioned on the surface of the composite nanowire structure, a second side wall positioned on the side wall of the pseudo gate and a pseudo gate barrier layer positioned on the top surface of the pseudo gate.
18. The method of forming a semiconductor structure of claim 16, further comprising: and removing the sacrificial layer and the dummy gate structure after the source-drain doped layer is formed, so as to form a gate structure on the surface of the composite nanowire structure.
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| CN107154433A (en) * | 2016-03-02 | 2017-09-12 | 三星电子株式会社 | Semiconductor devices |
| CN111180513A (en) * | 2018-11-12 | 2020-05-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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