CN113629073B - TFT backboard and display panel - Google Patents
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- CN113629073B CN113629073B CN202110848391.2A CN202110848391A CN113629073B CN 113629073 B CN113629073 B CN 113629073B CN 202110848391 A CN202110848391 A CN 202110848391A CN 113629073 B CN113629073 B CN 113629073B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the application provides a TFT backboard and a display panel. The TFT backboard comprises a driving TFT, wherein the driving TFT comprises a shading layer, an active layer, a grid electrode and a source drain metal layer which are sequentially laminated and arranged at intervals; the shading layer and the grid electrode are arranged corresponding to the active layer; the source-drain metal layer comprises a source electrode, a drain electrode and a switching layer; the switching layer is respectively connected with the grid electrode and the shading layer, so that the grid electrode is electrically connected with the shading layer. According to the TFT backboard provided by the embodiment of the application, the light shielding layer is used for covering the active layer so as to improve the illumination stability of the driving TFT, and meanwhile, the switching layer which is arranged on the same layer as the source electrode and the drain electrode is also used for connecting the grid electrode and the light shielding layer, so that the driving TFT forms a double-grid TFT structure, the output current of the driving TFT can be improved, the good stability of the TFT backboard is ensured, and the TFT backboard can be used for driving a display panel with large size and high refresh rate and high brightness.
Description
Technical Field
The application relates to the technical field of display, in particular to a TFT backboard and a display panel.
Background
AMOLED (Active-matrix organic light-emitting diode) display technology has higher contrast ratio than LCD (Liquid Crystal Display) display, is rich in color reduction capability, can realize flexible foldable display, is a high-performance display technology for replacing LCD, and has been widely used in many high-end display fields in recent years such as flexible foldable display, large-size transparent display, and the like. The large size, high resolution and high refresh rate of AMOLED technology are the preconditions for achieving 8k+5g, and are also the mainstream display technology in the future.
The LED (light-emitting diode) display technology is a novel active light-emitting display technology, has higher contrast ratio than LCD and AMOLED display, has a more abundant color reduction capability, is a high-performance display technology for replacing LCD and AMOLED, and is widely used in many high-end display fields in recent years. The LED display technology can be classified into Mini-LEDs and micro-LEDs according to the size of a light emitting unit, wherein the Mini-LEDs can realize direct display and backlight as high-end LCD display, and the micro LEDs can realize higher resolution display than the Mini-LEDs.
The traditional AMOLED display panel and the traditional LED display panel both adopt a 3T1C driving framework and are combined with an oxide semiconductor thin film field effect transistor (TFT), so that the problems of low driving current and poor backboard reliability are faced to a certain extent, and high-performance display integrating large-size high-resolution high refresh rate is difficult to realize.
Disclosure of Invention
The embodiment of the application provides a TFT backboard and a display panel, wherein the TFT backboard can be applied to the display panel and has stronger current driving capability and reliability.
In a first aspect, embodiments of the present application provide a TFT backplate, including a driving TFT, where the driving TFT includes a light shielding layer, an active layer, a gate electrode, and a source-drain metal layer that are sequentially stacked and arranged at intervals;
the shading layer and the grid electrode are arranged corresponding to the active layer;
the source-drain metal layer comprises a source electrode, a drain electrode and a switching layer;
the transfer layer is respectively connected with the grid electrode and the shading layer, so that the grid electrode is electrically connected with the shading layer.
In some embodiments, the TFT backplane further comprises a substrate base plate, a buffer layer, a gate insulating layer, and an interlayer dielectric layer;
the light shielding layer is arranged on the substrate, and the buffer layer covers the light shielding layer and the substrate;
the active layer, the gate insulating layer and the gate are sequentially stacked on the buffer layer, and the interlayer dielectric layer covers the active layer, the gate insulating layer and the gate;
the source-drain metal layer is arranged on the interlayer dielectric layer;
a first through hole is formed in the interlayer dielectric layer between the transfer layer and the grid electrode, and the transfer layer is connected with the grid electrode through the first through hole;
and a second through hole is arranged on the interlayer dielectric layer and the buffer layer between the transfer layer and the shading layer, and the transfer layer is connected with the shading layer through the second through hole.
In some embodiments, the TFT backplane further comprises a passivation layer, a planarization layer, a first electrode, and a pixel definition layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the flat layer covers the passivation layer;
the first electrode is arranged on the flat layer, and the pixel definition layer covers the first electrode and the flat layer;
a third through hole is formed in the passivation layer and the flat layer between the first electrode and the source electrode, and the first electrode and the source electrode are connected through the third through hole;
and a fourth through hole is formed in the pixel definition layer in a region corresponding to the first electrode, and the bottom of the fourth through hole is used for arranging an OLED device.
In some embodiments, the TFT back plate further comprises a passivation layer, a conductive layer, and an insulating protective layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the conductive layer comprises a second electrode and a third electrode which are arranged at intervals; the conducting layer is arranged on the passivation layer, and the insulating protection layer covers the conducting layer and the passivation layer;
a fifth through hole is formed in the passivation layer between the second electrode and the source electrode, and the second electrode and the source electrode are connected through the fifth through hole;
a sixth through hole is formed in the insulating protection layer in a region corresponding to the second electrode, a seventh through hole is formed in the insulating protection layer in a region corresponding to the third electrode, the portion, exposed in the sixth through hole, of the second electrode is used for being connected with the anode of the LED device, and the portion, exposed in the seventh through hole, of the third electrode is used for being connected with the cathode of the LED device.
In some embodiments, the material of the active layer is an oxide semiconductor material.
In some embodiments, the oxide semiconductor material includes an indium element, a zinc element, and an oxygen element, and a molar amount of the indium element in the oxide semiconductor material is greater than a molar amount of the zinc element.
In some embodiments, the material of the light shielding layer comprises molybdenum, aluminum, copper, titanium, tungstenOne or more of chromium, nickel and the above metal alloys, the thickness of the light shielding layer is
In some embodiments, the gate includes a first metal layer and a second metal layer that are stacked, the first metal layer being disposed toward the active layer, the second metal layer being disposed toward the source-drain metal layer;
the material of the first metal layer comprises at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloy thereof, and the thickness of the first metal layer is
The material of the second metal layer comprises at least one of aluminum and copper, and the thickness of the second metal layer is
In a second aspect, an embodiment of the present application further provides a display panel, including a TFT backplane and a light emitting device, where the TFT backplane is the TFT backplane described above, and a source of the driving TFT in the TFT backplane is electrically connected to the light emitting device.
In some embodiments, the light emitting device comprises at least one of an OLED device and an LED device.
According to the TFT backboard provided by the embodiment of the application, the light shielding layer is used for covering the active layer so as to improve the illumination stability of the driving TFT, and meanwhile, the switching layer which is arranged on the same layer as the source electrode and the drain electrode is also used for connecting the grid electrode and the light shielding layer, so that the driving TFT forms a double-grid TFT structure, the output current of the driving TFT can be improved, the good stability of the TFT backboard is ensured, and the TFT backboard can be used for driving a display panel with large size and high refresh rate and high brightness.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a first structure of a TFT backplane according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a first structure of a display panel according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a second structure of a TFT backplane according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a second structure of the display panel according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of a first structure of a TFT backplane according to an embodiment of the present application. The embodiment of the application provides a TFT backplane 100, which can be applied to an AMOLED display backplane to improve the current driving capability of the AMOLED display backplane, wherein the TFT backplane 100 can comprise a driving TFT, and the driving TFT comprises a light shielding layer 20, an active layer 40, a gate 50 and a source-drain metal layer which are sequentially laminated and are arranged at intervals; the light shielding layer 20 and the gate electrode 50 are disposed corresponding to the active layer 40; the source-drain metal layer includes a source electrode 61, a drain electrode 62 and a transfer layer 63; the transfer layer 63 is connected to the gate 50 and the light shielding layer 20, so that the gate 50 and the light shielding layer 20 are electrically connected. It is understood that the driving TFT refers to a TFT for driving the light emitting device to emit light, and an output current of the driving TFT directly affects performance parameters such as light emitting luminance of the light emitting device.
In the TFT backplane 100 of the embodiment of the present application, the light shielding layer 20 can significantly improve the light stability of the driving TFT, and after the gate 50 and the light shielding layer 20 are connected, the gate 50 substantially forms a top gate, and the light shielding layer 20 substantially forms a bottom gate, that is, the driving TFT is substantially a dual gate TFT structure. The conventional TFT structure generally connects the light shielding layer 20 to the source electrode 61 to improve the light stability and output saturation characteristics of the driving TFT, but the structure suppresses the output current of the TFT, significantly reduces the driving characteristics of the TFT, and the present application can significantly improve the output current of the driving TFT and enhance the driving characteristics of the driving TFT by connecting the gate electrode 50 and the light shielding layer 20 together to form a dual gate TFT structure. The TFT backplane 100 of the embodiment of the present application has a high stability while having a high output current, and can be used for driving a large-sized display panel with a high refresh rate and high brightness.
Referring to fig. 1, the tft back plate 100 may further include a substrate 10, a buffer layer 31, a gate insulating layer 32, and an interlayer dielectric layer 33;
the light shielding layer 20 is arranged on the substrate 10, and the buffer layer 31 covers the light shielding layer 20 and the substrate 10;
the active layer 40, the gate insulating layer 32, and the gate electrode 50 are sequentially stacked on the buffer layer 31, and the interlayer dielectric layer 33 covers the active layer 40, the gate insulating layer 32, and the gate electrode 50;
the source-drain metal layer is arranged on the interlayer dielectric layer 33;
a first through hole 91 is formed on the interlayer dielectric layer 33 between the transfer layer 63 and the gate 50, and the transfer layer 63 is connected with the gate 50 through the first through hole 91;
the interlayer dielectric layer 33 and the buffer layer 31 between the transfer layer 63 and the light shielding layer 20 are provided with a second through hole 92, and the transfer layer 63 is connected with the light shielding layer 20 through the second through hole 92.
Referring to fig. 1, the tft back plate 100 may further include a passivation layer 34, a planarization layer 35, a first electrode 71, and a pixel defining layer 80;
the passivation layer 34 covers the source/drain metal layer and the interlayer dielectric layer 33;
the planarization layer 35 covers the passivation layer 34;
the first electrode 71 is disposed on the planarization layer 35, and the pixel defining layer 80 covers the first electrode 71 and the planarization layer 35;
a third through hole 93 is formed in the passivation layer 34 and the planarization layer 35 between the first electrode 71 and the source electrode 61, and the first electrode 71 and the source electrode 61 are connected via the third through hole 93;
a fourth via hole 94 is provided in the pixel defining layer 80 in a region corresponding to the first electrode 71, and the bottom of the fourth via hole 94 is used to provide the OLED device 101.
The substrate 10 may be a glass substrate.
The material of the light shielding layer 20 may be one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni) and metal alloys thereof, and the thickness of the light shielding layer 20 may be
The buffer layer 31 may be a single layer of silicon nitride (SiN) x ) Single-layer silicon oxide (SiO) x ) Single layer silicon oxynitride (SiO) x N x ) Or a double-layer composite film of the above materials, the thickness of the buffer layer 31 may be
The material of the active layer 40 may be an oxide semiconductor material. Illustratively, the oxide semiconductor material includes an indium (In) element, a zinc (Zn) element, and an oxygen (O) element, and a molar amount of the indium element In the oxide semiconductor material is greater than a molar amount of the zinc element. The molar quantity of indium element and zinc element in the traditional oxide semiconductor material IGZO (indium gallium zinc oxide) is 1:1, and the mobility of the oxide semiconductor material can be improved by improving the content of the indium element, so that the output current of the driving TFT is improved. The above-described dual gate TFT structure formed by connecting the light shielding layer 20 and the gate electrode 50 is known to improve the mobility of the driving TFT, and the present application can improve the light emission brightness, the refresh rate, the resolution, the display size reduction and the like of the AMOLED display panel due to the reduction of the driving current by 2 times or more while ensuring high light stability by improving the TFT structure and improving the oxide semiconductor material.
The material of the gate insulating layer 32 may be silicon oxide (SiO 2 ) The gate insulating layer 32 may have a thickness of
The gate electrode 50 may include a first metal layer and a second metal layer stacked, the first metal layer being disposed toward the active layer 40, the second metal layer being disposed toward the source-drain metal layer; the first metal layer is made of at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloy thereof, and has a thickness ofThe second metal layer may be made of at least one of aluminum and copper, and has a thickness of +.>
The material of the interlayer dielectric layer 33 may be silicon oxide (SiO 2 ) The interlayer dielectric layer 33 may have a thickness of
The source/drain metal layer may be a double-layer metal structure, wherein the first layer (near the interlayer dielectric layer 33) may be a transition metal material such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni) or an alloy thereof, or a conductive oxide material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), aluminum doped zinc oxide (AZO), etc., and the thickness of the first layer may beThe second layer (near the passivation layer 34) may be made of aluminum (Al), copper (Cu), or other metal material, and the second layer may have a thickness of +>
The material of passivation layer 34 may beSilicon oxide (SiO) 2 ) The passivation layer 34 may have a thickness of
The material of the first electrode 71 may be a metal or a transparent conductive metal oxide (e.g., ITO).
The material of the planarization layer 35 may be an organic material such as a photoresist material.
The material of the pixel defining layer 80 may be an organic material, such as a photoresist material.
The TFT backplane 100 of the embodiment of the present application may be a TFT backplane with a 3T1C driving architecture, where the TFT backplane 100 may further include a switching TFT and a detecting TFT, the source of the switching TFT is connected to the gate 50 of the driving TFT, and the detecting TFT is electrically connected to the driving TFT and is used for detecting the performance of the driving TFT. Of course, the TFT backplane 100 of the embodiment of the present application may also be a TFT backplane having a 2T1C driving architecture.
The method for manufacturing the TFT backplane 100 provided in this embodiment specifically may include:
(1) Cleaning the substrate base plate 10;
(2) Depositing a shading layer 20 and performing patterning treatment;
(3) A buffer layer 31 is deposited to cover the light shielding layer 20;
(4) Depositing an oxide semiconductor layer, and performing patterning treatment to form an active region (an active layer 40) of a driving TFT, an active region of a switching TFT and an active region of a detecting TFT;
(5) Depositing a gate insulation layer 32;
(6) Depositing a gate metal layer;
(7) Defining a pattern of the gate 50 and a pattern of the gate insulating layer 32 by using a photomask, etching the gate metal layer by wet etching, and etching the gate insulating layer 32 by dry etching by using the metal protection layer pattern as self alignment;
(8) Processing the region of the oxide semiconductor layer not protected by the gate insulating layer 32 with Plasma (Plasma) to form an n+ conductor region serving as a source 61/drain 62 contact; the oxide semiconductor layer under the gate insulating layer 32 is not treated as a TFT channel;
(9) Depositing an interlayer dielectric layer 33, and etching a source contact hole and a drain contact hole of the interlayer dielectric layer 33 and a via hole for enabling the gate 50 to be in contact with the light shielding layer 20 respectively by using a patterning process;
(10) Depositing a source-drain metal layer, and defining a source electrode 61, a drain electrode 62, a switching layer 63 and other metal wiring areas by using the same photomask;
(11) Depositing a passivation layer 34 and etching out the via;
(12) Depositing a flat layer 35, and making a via hole through yellow light;
(13) Preparing a first electrode 71 for contacting the OLED light emitting device;
(14) The pixel defining layer 80 is deposited and the light emitting region is defined by the yellow light to complete the fabrication of the TFT backplane 100.
Referring to fig. 2, fig. 2 is a schematic diagram of a first structure of a display panel according to an embodiment of the disclosure. The embodiment of the present application further provides an AMOLED display panel 200, including the TFT backplane 100 and the OLED device 101 shown in fig. 1, where the OLED device 101 is disposed in the fourth through hole 94 and electrically connected to the first electrode 71, and the structure of the TFT backplane 100 is described above, which is not described herein.
Referring to fig. 3, fig. 3 is a schematic diagram of a second structure of a TFT backplane according to an embodiment of the present application. The embodiment of the application also provides a TFT backplane 100', which can be applied to an LED display backplane to improve the current driving capability of the LED display backplane, wherein the TFT backplane 100' can comprise a driving TFT, and the driving TFT comprises a light shielding layer 20', an active layer 40', a grid electrode 50' and a source-drain metal layer which are sequentially laminated and arranged at intervals; the light shielding layer 20' and the gate electrode 50' are disposed corresponding to the active layer 40 '; the source/drain metal layer includes a source electrode 61', a drain electrode 62' and a transfer layer 63'; the switching layer 63' is connected to the gate 50' and the light shielding layer 20', so that the gate 50' and the light shielding layer 20' are electrically connected.
It will be appreciated that the light shielding layer 20' may significantly improve the light stability of the driving TFT, and that the gate 50' may substantially form a top gate and the light shielding layer 20' may substantially form a bottom gate after the gate 50' and the light shielding layer 20' are connected, that is, the driving TFT may substantially be a dual gate TFT structure. The conventional TFT structure generally connects the light shielding layer 20 'to the source electrode 61' to improve the light stability and output saturation characteristics of the TFT, but the structure suppresses the output current of the TFT, significantly reduces the driving characteristics of the TFT, and the present application can significantly improve the output current of the driving TFT and the driving characteristics of the driving TFT by connecting the gate electrode 50 'and the light shielding layer 20' together to form a dual gate TFT structure. The TFT backplane 100' of the embodiment of the present application has a high stability while having a high output current, and can be used for driving a large-sized display panel with a high refresh rate and high brightness.
Referring to fig. 3, the tft back plate 100' may further include a substrate 10', a buffer layer 31', a gate insulating layer 32', and an interlayer dielectric layer 33';
the light shielding layer 20' is arranged on the substrate 10', and the buffer layer 31' covers the light shielding layer 20' and the substrate 10';
an active layer 40', a gate insulating layer 32', and a gate electrode 50 'are sequentially stacked on the buffer layer 31', and an interlayer dielectric layer 33 'covers the active layer 40', the gate insulating layer 32', and the gate electrode 50';
the source-drain metal layer is arranged on the interlayer dielectric layer 33';
the interlayer dielectric layer 33' between the transfer layer 63' and the gate 50' is provided with a first through hole 91', and the transfer layer 63' is connected with the gate 50' through the first through hole 91 ';
the interlayer dielectric layer 33 'and the buffer layer 31' between the transfer layer 63 'and the light shielding layer 20' are provided with a second via 92', and the transfer layer 63' is connected to the light shielding layer 20 'through the second via 92'.
Referring to fig. 3, the tft backplane 100' may further include a passivation layer 34', a conductive layer, and an insulating protection layer 36';
the passivation layer 34 'covers the source/drain metal layer and the interlayer dielectric layer 33';
the conductive layer comprises a second electrode 72 'and a third electrode 73' which are arranged at intervals; the conductive layer is disposed on the passivation layer 34', and the insulating protection layer 36' covers the conductive layer and the passivation layer 34';
a fifth through hole 95' is provided on the passivation layer 34' between the second electrode 72' and the source electrode 61', and the second electrode 72' and the source electrode 61' are connected via the fifth through hole 95 ';
a sixth through hole 96 'is formed in the insulating protection layer 36' in a region corresponding to the second electrode 72', a seventh through hole 97' is formed in the insulating protection layer 36 'in a region corresponding to the third electrode 73', a portion of the second electrode 72 'exposed in the sixth through hole 96' is used for connecting to the positive electrode of the LED device 102', and a portion of the third electrode 73' exposed in the seventh through hole 97 'is used for connecting to the negative electrode of the LED device 102'.
The substrate 10' may be a glass substrate.
The material of the light shielding layer 20 'may be one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni) and metal alloys thereof, and the thickness of the light shielding layer 20' may be
Buffer layer 31' may be a single layer of silicon nitride (SiN) x ) Single-layer silicon oxide (SiO) x ) Single layer silicon oxynitride (SiO) x N x ) Or a double-layer composite film of the above materials, the thickness of the buffer layer 31' may be
The material of the active layer 40' may be an oxide semiconductor material. Illustratively, the oxide semiconductor material includes an indium (In) element, a zinc (Zn) element, and an oxygen (O) element, and a molar amount of the indium element In the oxide semiconductor material is greater than a molar amount of the zinc element. The molar quantity of indium element and zinc element in the traditional oxide semiconductor material IGZO (indium gallium zinc oxide) is 1:1, and the mobility of the oxide semiconductor material can be improved by improving the content of the indium element, so that the output current of the driving TFT is improved. The above-described dual gate TFT structure formed by connecting the light shielding layer 20 'and the gate electrode 50' is known to improve the mobility of the driving TFT, and the present application can improve the high driving current requirement of the LED display panel by improving the TFT structure and improving the oxide semiconductor material, while ensuring high light stability, so that the output current of the driving TFT is increased by 2 times or more.
The material of the gate insulating layer 32' may be silicon oxide (SiO 2 ) The thickness of the gate insulating layer 32' may be
The gate electrode 50 'may include a first metal layer and a second metal layer stacked, the first metal layer being disposed toward the active layer 40', the second metal layer being disposed toward the source-drain metal layer; the first metal layer is made of at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloy thereof, and has a thickness ofThe second metal layer may be made of at least one of aluminum and copper, and has a thickness of +.>
The material of the interlayer dielectric layer 33' may be silicon oxide (SiO 2 ) The interlayer dielectric layer 33' may have a thickness of
The source/drain metal layer may be a double-layer metal structure, wherein the first layer (near the interlayer dielectric layer 33') may be a transition metal material such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), or alloys thereof, or a conductive oxide material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), aluminum doped zinc oxide (AZO), etc., and the thickness of the first layer may beThe material of the second layer (near the passivation layer 34') may be aluminum (Al), copper (Cu), or other metal material, and the thickness of the second layer may beTo be->
The material of the passivation layer 34' may be silicon oxide (SiO 2 ) The passivation layer 34' may have a thickness of
The material of the conductive layer may be a metal or a transparent conductive metal oxide (e.g., ITO).
The material of the insulating protection layer 36' may be an organic insulating material, such as a photoresist material. The insulating protective layer 36 may function to prevent the second electrode 72 'from being conducted with the third electrode 73', and to protect the underlying stacked structure.
The TFT backplane 100 'of the embodiment of the present application may be a TFT backplane with a 3T1C driving architecture, that is, the TFT backplane 100' may further include a switching TFT and a detecting TFT, where a source 61 'of the switching TFT is connected to a gate 50' of the driving TFT, and the detecting TFT is electrically connected to the driving TFT and is used for detecting performance of the driving TFT. Of course, the TFT backplane 100' of the embodiment of the present application may also be a TFT backplane with a 2T1C driving architecture.
The method for manufacturing the TFT backplane 100' provided in this embodiment specifically may include:
(1) Cleaning the substrate base plate 10';
(2) Depositing a shading layer 20' and performing patterning treatment;
(3) Depositing a buffer layer 31 'to cover the light shielding layer 20';
(4) Depositing an oxide semiconductor layer and performing patterning treatment to form an active region (an active layer 40') of the driving TFT, an active region of the switching TFT and an active region of the detecting TFT;
(5) Depositing a gate insulation layer 32';
(6) Depositing a gate metal layer;
(7) Defining a graph of a grid electrode 50' and a graph of a grid electrode insulating layer 32' by utilizing a photomask, etching a grid electrode metal layer by wet etching, and then etching the grid electrode insulating layer 32' by dry etching by utilizing the metal protection layer graph as self alignment;
(8) Processing the region of the oxide semiconductor layer not protected by the gate insulating layer 32' with Plasma (Plasma) to form an n+ conductor region for source 61 '/drain 62' contact; the oxide semiconductor layer under the gate insulating layer 32' is not treated as a TFT channel;
(9) Depositing an interlayer dielectric layer 33', and etching a source contact hole and a drain contact hole of the interlayer dielectric layer 33' and a transfer hole for enabling the grid 50 'to be contacted with the shading layer 20' respectively by using a patterning process;
(10) Depositing a source-drain metal layer, and defining a source electrode 61', a drain electrode 62', a switching layer 63' and other metal wiring areas by using the same photomask;
(11) Depositing a passivation layer 34' and etching out the via;
(12) Depositing a conductive layer, preparing a second electrode 72' and a third electrode 73' by patterning to contact the LED device 102';
(13) The insulating protection layer 36' is deposited, and the bonding area (the sixth through hole 96' and the seventh through hole 97 ') of the LED device 102' is defined by yellow light, so as to complete the fabrication of the TFT back plate 100 '.
Referring to fig. 4, fig. 4 is a schematic diagram of a second structure of the display panel according to the embodiment of the present application. The embodiment of the present application further provides an LED display panel 200', including the TFT backplate 100' and the LED device 102 'shown in fig. 3, where the positive electrode of the LED device 102' is electrically connected to the second electrode 72', and the negative electrode of the LED device 102' is electrically connected to the third electrode 73', and the structure of the TFT backplate 100' is described above and will not be repeated herein.
The TFT back plate and the display panel provided in the embodiments of the present application are described in detail above. Specific examples are set forth herein to illustrate the principles and embodiments of the present application, with the description of the examples given above only to assist in understanding the present application. Meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (3)
1. The display panel is characterized by comprising a TFT backboard and a light-emitting device, wherein the light-emitting device is an LED; the TFT backboard comprises a driving TFT, wherein the driving TFT comprises a shading layer, an active layer, a grid electrode and a source drain metal layer which are sequentially laminated and arranged at intervals;
the shading layer and the grid electrode are arranged corresponding to the active layer;
the source-drain metal layer comprises a source electrode, a drain electrode and a switching layer;
the transfer layer is respectively connected with the grid electrode and the shading layer, so that the grid electrode is electrically connected with the shading layer;
the TFT backboard further comprises a substrate base plate, a buffer layer, a grid insulating layer and an interlayer dielectric layer;
the light shielding layer is arranged on the substrate, and the buffer layer covers the light shielding layer and the substrate;
the active layer, the gate insulating layer and the gate are sequentially stacked on the buffer layer, and the interlayer dielectric layer covers the active layer, the gate insulating layer and the gate;
the source-drain metal layer is arranged on the interlayer dielectric layer;
a first through hole is formed in the interlayer dielectric layer between the transfer layer and the grid electrode, and the transfer layer is connected with the grid electrode through the first through hole;
the interlayer dielectric layer and the buffer layer between the transfer layer and the shading layer are provided with second through holes, and the transfer layer is connected with the shading layer through the second through holes;
the TFT backboard further comprises a passivation layer, a conductive layer and an insulating protective layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the conductive layer comprises a second electrode and a third electrode which are arranged at intervals; the conducting layer is arranged on the passivation layer, and the insulating protection layer covers the conducting layer and the passivation layer;
a fifth through hole is formed in the passivation layer between the second electrode and the source electrode, and the second electrode and the source electrode are connected through the fifth through hole;
a sixth through hole is formed in the insulating protection layer in a region corresponding to the second electrode, a seventh through hole is formed in the insulating protection layer in a region corresponding to the third electrode, the part, exposed in the sixth through hole, of the second electrode is used for being connected with the anode of the LED device, and the part, exposed in the seventh through hole, of the third electrode is used for being connected with the cathode of the LED device;
the material of the active layer is an oxide semiconductor material; the oxide semiconductor material contains an indium element, a zinc element, and an oxygen element, and a molar amount of the indium element in the oxide semiconductor material is larger than a molar amount of the zinc element;
the TFT backboard further comprises a switch TFT and a detection TFT, wherein a source electrode of the switch TFT is connected to a grid electrode of the driving TFT, the detection TFT is electrically connected with the driving TFT, and the detection TFT is used for detecting the performance of the driving TFT.
2. The display panel according to claim 1, wherein the material of the light shielding layer comprises one or more of molybdenum, aluminum, copper, titanium, tungsten, chromium, nickel, and metal alloys thereof, and the light shielding layer has a thickness of
3. The display panel according to claim 1 or 2, wherein the gate electrode includes a first metal layer and a second metal layer which are stacked, the first metal layer being disposed toward the active layer, the second metal layer being disposed toward the source-drain metal layer;
the material of the first metal layer comprises at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloy thereof, and the thickness of the first metal layer is
The material of the second metal layer comprises at least one of aluminum and copper, and the thickness of the second metal layer is
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