CN113612559B - A reconfigurable channel fading simulation device and its fading twinning method - Google Patents

Abstract

The invention discloses a reconfigurable channel fading simulation device and a fading twin method thereof, belonging to the field of wireless information transmission. The simulation device comprises a communication scene configuration unit, an analog-to-digital conversion unit, a reconfigurable fading generation unit, a reconfigurable time delay simulation unit, a reconfigurable channel superposition unit and a digital-to-analog conversion unit. Aiming at the diversity of wireless channel fading in an actual communication scene, the invention can realize the hardware real-time calculation of channel fading elementary functions in any convergence domain according to communication scene parameters input by a user, has a universal, flexible and reconfigurable hardware structure, and is suitable for channel simulation in the actual communication scene.

Description

A reconfigurable channel fading simulation device and its fading twinning method

technical field

The invention belongs to the field of wireless information transmission, and is particularly aimed at hardware simulation of channel fading in wireless communication scenarios, in particular to a reconfigurable channel fading simulation device and a fading twin method thereof.

Background technique

In the process of transmission, radio wave signals will be affected by the surrounding environment to produce a certain degree of fading of different types. For example, there is path loss due to the influence of terrain and transmission distance. Due to the superposition of scattering branches, multipath fading will be generated. Obstruction by obstacles also allows shadow fading to occur.

In order to effectively evaluate the performance of wireless communication systems, while reducing the cost of field test simulation and increasing the controllability of channel simulation, further research on wireless channel fading simulation is required in a laboratory environment. In real propagation scenarios, the types of wireless channel fading are diverse, which brings about the problems of high hardware simulation cost and low efficiency. Therefore, a general channel fading hardware twinning method is needed to achieve realistic reproduction of different kinds of wireless channel fading.

The key to wireless channel fading hardware twinning is how to efficiently generate Gaussian random sequences. For traditional fading simulation methods, Gaussian random variables are usually implemented by look-up table method, which is easy to implement in hardware and has good real-time performance, but consumes a lot of RAM resources. Coordinate Rotation Digital Computer (CORDIC) is another implementation method. Through a series of addition/subtraction and shift operations, the real-time calculation of trigonometric functions required for Gaussian variable generation can be realized. Fewer RAM resources. However, the traditional CORDIC algorithm has the problems of many iterations, large algorithm delay and small convergence area.

SUMMARY OF THE INVENTION

Aiming at the problems existing in the prior art, the present invention provides a reconfigurable channel fading simulation device and a fading twin method thereof. Based on the CORDIC principle, the invention can effectively reduce unnecessary iteration times, reduce hardware storage resource consumption, and improve the real-time performance of wireless channel fading hardware twins in view of the diversity of wireless channel fading in actual communication scenarios.

In order to achieve the above object, the present invention adopts the following technical scheme: a reconfigurable channel fading simulation device, comprising: a communication scene configuration unit (1-1), an analog-to-digital conversion unit (1-2), a reconfigurable fading generation unit (1-3), a reconfigurable delay simulation unit (1-4), a reconfigurable channel superposition unit (1-5), a digital-to-analog conversion unit (1-6); the communication scene configuration unit (1- The output interface of 1) is connected with the input interface of the reconfigurable fading generation unit (1-3) and the reconfigurable delay simulation unit (1-4) by a PCIE bus, and the analog-to-digital conversion unit (1-2) has a The output interface is connected to the input interface of the reconfigurable delay simulation unit (1-4), the output interface of the reconfigurable fading generation unit (1-3), the output interface of the reconfigurable delay simulation unit (1-4) The output interfaces are all connected with the input interface of the reconfigurable channel superposition unit (1-5), and the output interface of the reconfigurable channel superposition unit (1-5) is connected with the input interface of the digital-to-analog conversion unit (1-6) .

Further, the reconfigurable fading generation unit (1-3) is composed of a channel fading module and a fading selector; the channel fading module includes: a time-varying phase calculation module, a complex exponential calculation module, an e-index calculation module, a pair of A number calculation module and a square root calculation module, the time-varying phase calculation module is used to calculate and generate a time-varying phase; the complex exponential calculation module is used to generate a Gaussian random variable, and the Rayleigh fading value and Rice fading value; the logarithmic calculation module is used to calculate the logarithmic value of Rayleigh fading, and the Weibull fading value is generated by the e-index calculation module; the e-index calculation module is used to calculate the shadow fading value; the square root calculation module It can be used to calculate the path loss value and Nakagami fading value; the fading selector is used to select the shadow fading value, Weibull fading value, Rayleigh fading value, Rice fading value, path loss value, Nakagami fading value generated by the channel fading module input to In the reconfigurable channel superposition unit (1-5).

Further, the reconfigurable time delay analog unit (1-4) is composed of a DDR3 module, a RAM module and a polyphase filter structure, and the DDR3 module is used for receiving the digital signal output by the analog-to-digital conversion unit (1-2) , perform large delay simulation by reading and writing DDR3 addresses; the RAM module is used for receiving the output signal of the DDR3 module, and performing integer delay simulation by reading and writing the RAM address; the polyphase filtering structure is used for receiving the output signal of the RAM module , to achieve high-precision fractional delay simulation through multiple interpolation.

Further, the reconfigurable channel superposition unit (1-5) is composed of a channel convolution module and a gain control module, and the channel convolution module combines the reconfigurable fading generation unit (1-3) and the reconfigurable time The output signal of the extension analog unit (1-4) is convolved, and the result of the convolution is used as the input of the gain control structure, and the gain control structure inputs the gain-controlled signal to the digital-to-analog conversion unit (1-6).

The present invention also provides a fading twinning method for a reconfigurable channel fading simulation device, which specifically includes the following steps:

(1) The user inputs the communication scene parameters through the communication scene configuration unit (1-1), and transmits the communication scene through the PCIE bus to the reconfigurable fading generation unit (1-3) and the reconfigurable delay simulation unit (1- 4); the communication scene parameters include: Doppler frequency f _n,m and initial phase θ _n,m of the m th harmonic of the n th channel, cumulative cosine value P _n , standard deviation ξ _{n of shadow fading, β} , shadow fading mean α _n,β , direct diameter coefficient ρ _m , average power _pn ^Sha of each cluster signal channel fading, Weibull shape factor w _m and filter coefficients 1, 2,...S, channel delay parameters ;

(2) The reconfigurable delay simulation unit (1-4) divides the channel delay parameters provided by the communication scene configuration unit (1-1) into large delay, integer delay and fractional delay, and respectively Use DDR3 module, RAM module and polyphase filtering structure to perform delay operation on the input signal x(t), and the delayed signal is denoted as x(t-τ _n ) and sent to the reconfigurable channel superposition unit (1-5) , where τ _n represents the path delay;

(3) Reconfigurable fading generation unit (1-3) Doppler frequency f _n,m and initial phase θ _n,m and cumulative cosine value P _n of the m-th harmonic of the n-th channel configured according to the communication scenario , the standard deviation of shadow fading ξ _n,β , the mean value of shadow fading α _n,β , the direct diameter coefficient ρ _m , the average power p _n ^Sha of each cluster signal channel fading, Weibulλ shape factor w _m and filter coefficients 1, 2, ...S, generate different types of channel fading values r _n ⁱ (t), and output the different types of channel fading values r _n ⁱ (t) to the reconfigurable channel superposition unit (1-5) through the fading selector , the channel fading value r _n ⁱ (t) includes: shadow fading value, Weibull fading value, Rayleigh fading value, Rice fading value, path loss value, Nakagami fading value;

(4) The reconfigurable channel superposition unit (1-5) performs a convolution operation on the output signal of the reconfigurable delay simulation unit (1-4) and the output signal of the reconfigurable fading generation unit (1-3), Obtain the output signal y(t) after passing through the wireless channel, and perform automatic gain adjustment on the power of the output signal y(t); wherein, the output signal y(t) is

N represents the total number of channels;

(5) The result of automatic gain adjustment of the output signal is sent to the digital-to-analog conversion unit (1-6), and the analog signal superimposed with the channel fading delay is output.

Further, step (2) includes the following substeps:

(2.1) According to the delay parameter provided by the communication scene configuration unit (1-1), the delay parameter greater than the RAM depth is used as the address parameter of DDR3, and the digital signal output by the analog-to-digital conversion unit (1-2) is used as the DDR3 address parameter. Input data, use read and write address operations to achieve large delay simulation;

(2.2) Round the delay parameter less than the RAM depth in units of clock cycles, take the integer part as the address parameter of the RAM, take the output signal of DDR3 as the input data of the RAM, and use the read and write address operations to achieve integer delay simulation;

(2.3) The fractional part is used as the control parameter of the polyphase filter, the output signal of the RAM is used as the input data of the polyphase filter, and the coefficients 1, 2,...S of the control polyphase filter are used to realize the simulation of the fractional delay .

复指数运算得出。Further, the Rayleigh fading value and the Rice fading value are iteratively summed by the circular CORDIC rotation mode.

Complex exponential operation is obtained.

Further, the shadow fading value and the Weibull fading value are obtained by iterating the hyperbolic CORDIC rotation mode and expanding the convergence region of the input angle.

Further, the Nakagami fading value and the path loss value are obtained by iterating the hyperbolic CORDIC vector pattern and extending the convergence region of the input angle.

Compared with the prior art, the present invention has the following beneficial effects: the reconfigurable fading generation unit in the reconfigurable channel fading simulation device of the present invention can generate different channel fading values, and has the characteristics of strong versatility and high flexibility , which is suitable for the simulation of different channel fading in actual communication scenarios. The fading twin method of the reconfigurable channel fading simulation device of the present invention can realize real-time calculation of elementary functions required for channel fading generation, greatly optimize the utilization rate of hardware resources, and improve the real-time performance of the reconfigurable channel fading simulation device.

Description of drawings

1 is a schematic structural diagram of a reconfigurable channel fading simulation device according to the present invention;

Fig. 2 is the flow chart of the fading twinning method of the reconfigurable channel fading simulation device of the present invention;

FIG. 3 is a schematic diagram of three different CORDIC iteration models of the present invention; (a) in FIG. 3 is a schematic diagram of CR CORDIC iteration, (b) in FIG. 3 is a schematic diagram of HR CORDIC iteration, and (c) in FIG. 3 Iterative schematic for HV CORDIC.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention are described more clearly and completely below.

FIG. 1 is a schematic structural diagram of a reconfigurable channel fading simulation device according to the present invention. The reconfigurable channel fading simulation device includes: a communication scene configuration unit 1-1, an analog-to-digital conversion unit 1-2, and a reconfigurable fading generation unit 1 -3. The reconfigurable delay simulation unit 1-4, the reconfigurable channel superposition unit 1-5, the digital-to-analog conversion unit 1-6, the output interface of the communication scene configuration unit 1-1 and the reconfigurable fading generation unit 1 -3 and the input interface of the reconfigurable delay simulation unit 1-4 are connected by the PCIE bus, and the output interface of the analog-to-digital conversion unit 1-2 is connected with the input interface of the reconfigurable delay simulation unit 1-4, which can be reconfigured The output interface of the fading generation unit 1-3 and the output interface of the reconfigurable delay simulation unit 1-4 are connected to the input interface of the reconfigurable channel superposition unit 1-5, and the output of the reconfigurable channel superposition unit 1-5 The interface is connected with the input interface of the digital-to-analog conversion unit 1-6. The reconfigurable channel fading simulation device of the present invention has strong versatility and high flexibility, and is suitable for the simulation of different channel fading in actual communication scenarios.

The reconfigurable fading generating units 1-3 of the present invention are composed of a channel fading module and a fading selector; as shown in Figure 2, the channel fading module includes: a time-varying phase calculation module, a complex exponential calculation module, an e-exponential calculation module, and a logarithmic calculation module and the square root calculation module, the time-varying phase calculation module is used to calculate and generate the time-varying phase, and calculate the elementary function value required for channel fading in real time, so that the reconfigurable channel fading simulation device has the characteristics of real-time; the complex exponential calculation module is used to generate Gaussian random variable, through adder and multiplier operation, according to Rayleigh and Rice fading formula, obtain Rayleigh fading value and Rice fading value; logarithmic calculation module is used to calculate the Rayleigh fading value of different input angles after extended convergence. logarithmic value, and generate Weibull fading value through e-exponential calculation module; e-exponential calculation module is used to calculate the e-exponential function value of different input angles after extended convergence, and generate shadow fading value according to shadow fading formula; square root calculation module can be used to calculate Expand the square root function value of different input angles after convergence, generate path loss value and Nakagami fading value according to the path loss and Nakagami fading formula; the fading selector is used to select the shadow fading value, Weibull fading value and Rayleigh fading value generated by the channel fading module value, Rice fading value, path loss value, Nakagami fading value are input into the reconfigurable channel superposition unit 1-5.

In the present invention, the reconfigurable time delay analog unit 1-4 is composed of a DDR3 module, a RAM module and a polyphase filter structure. The DDR3 module is used to receive the digital signal output by the analog-to-digital conversion unit 1-2, and perform large-scale processing by reading and writing the DDR3 address. Delay simulation; the RAM module is used to receive the output signal of the DDR3 module, and the integer delay simulation is performed by reading and writing the RAM address; the polyphase filtering structure is used to receive the output signal of the RAM module, and realize high-precision fractional delay through multiple interpolation Simulation; the path delay τ _n can be simulated more accurately through the combination of large delay simulation, integer delay simulation and fractional delay simulation.

In the present invention, the reconfigurable channel superposition unit 1-5 is composed of a channel convolution module and a gain control module. The channel convolution module combines the outputs of the reconfigurable fading generation unit 1-3 and the reconfigurable delay simulation unit 1-4 The signal is convoluted, and the result of the convolution is used as the input of the gain control structure, and the gain control structure inputs the gain-controlled signal into the digital-to-analog conversion units 1-6.

The present invention also provides a fading twinning method for a reconfigurable channel fading simulation device, which specifically includes the following steps:

(1) The user inputs the communication scene parameters through the communication scene configuration unit 1-1, and transmits the communication scene to the reconfigurable fading generation unit 1-3 and the reconfigurable delay simulation unit 1-4 through the PCIE bus; in the present invention Communication scene parameters include: Doppler frequency f _n,m and initial phase θ _n,m of the mth harmonic of the nth path, cumulative cosine value P _n , standard deviation of shadow fading ξ _n,β , shadow fading mean value α _n,β , direct diameter coefficient ρ _m , average power _pn ^Sha of each cluster signal channel fading, Weibull shape factor w _m and filter coefficients 1, 2,...S, channel delay parameters;

(2) The reconfigurable delay simulation unit 1-4 divides the channel delay parameters provided by the communication scene configuration unit 1-4 into large delay, integer delay and fractional delay, for example, the delay value is 13.45 ms, it can be divided into three parts: 10ms, 3ms and 0.45ms; and respectively use DDR3 module, RAM module and polyphase filter structure to perform delay operation on the input signal x(t), the delayed signal is recorded as x( t-τ _n ) is sent to the reconfigurable channel superposition unit 1-5, where τ _n represents the path delay; specifically includes the following sub-steps:

(2.1) According to the delay parameter provided by the configuration unit 1-1 in the communication scenario, the delay parameter greater than the RAM depth is used as the address parameter of DDR3, and the digital signal output by the analog-to-digital conversion unit 1-2 is used as the input data of DDR3. Read and write address operations to achieve large delay simulation;

(2.2) Round the delay parameter less than the RAM depth in units of clock cycles, take the integer part as the address parameter of the RAM, take the output signal of DDR3 as the input data of the RAM, and use the read and write address operations to achieve integer delay simulation;

(2.3) The fractional part is used as the control parameter of the polyphase filter, the output signal of the RAM is used as the input data of the polyphase filter, and the coefficients 1, 2,...S of the control polyphase filter are used to realize the simulation of the fractional delay .

The simulation of large delay, integer delay, and fractional delay is realized through the above sub-steps, which can simulate the path delay τ _n more accurately and reduce unnecessary hardware resource consumption.

(3) The Doppler frequency f _n,m (maximum 1MHZ) of the mth harmonic of the nth channel configured by the reconfigurable fading generation unit 1-3 according to the communication scenario, the initial phase θ _n,m , the cumulative cosine value P _n , the standard deviation of shadow fading ξ _n,β , the mean value of shadow fading α _n,β , the direct diameter coefficient ρ _m , the average power _pn ^Sha of each cluster signal channel fading, the Weibull shape factor w _m and the filter coefficient 1, 2,...S, generate different types of channel fading values r _n ⁱ (t), and output the different types of channel fading values r _n ⁱ (t) to the reconfigurable channel superposition unit 1-5 through the fading selector In; the channel fading value r _n ⁱ (t) includes: shadow fading value, Weibull fading value, Rayleigh fading value, Rice fading value, path loss value, Nakagami fading value; specifically, Rayleigh fading value, Rice fading value The calculation process of the value is as follows:

(a) Let the initial values of the complex exponential calculation module be x ₀ =P _n , y ₀ =0, z ₀ =θ _n,m ,

(b) Iterative processing is performed through the circular CORDIC rotation pattern as shown in (a) in Figure 3:

Among them, b ⁱ ∈{-1,1} represents the iteration direction in the rotation mode; ω ⁱ represents the shift value during the iteration process, and the output value after iteration is:

计算复指数的值，通过累加器获得高斯随机变量σ_n(t)：(c) according to

Calculate the value of the complex exponent to obtain the Gaussian random variable σ _n (t) through the accumulator:

Among them, M represents the total number of harmonics;

(d) The complex addition is performed by the adder, and the Rayleigh fading value rn ^Ray ( _t ) can be obtained:

r _n ^Ray (t)=σ _n,1 (t)+jσ _n,2 (t)

where j represents the imaginary unit, σ _n,1 (t) represents the first Gaussian random variable, and σ _n,2 (t) represents the second Gaussian random variable.

(e) Let the initial value x ₀ =P _n , y ₀ =0,z ₀ =2πf _n,m t+θ _n,m , calculate the value of the complex index according to steps (b)-(c), and compare it with The Rice factor ρ _m is multiplied by the multiplier, and then added with the Rayleigh fading value r _n ^Ray (t) to obtain the Rice fading value r _n ^Ric (t)=ρ _m exp(j(2πf _n,m t+ θ _n,m ))+σ _n,1 (t)+jσ _n,2 (t), the initial phase θ _n,m obeys the uniform distribution of U～(0,2π].

The calculation process of shadow fading value and Weibull fading value in the present invention is as follows:

(A) Let the initial values of the e-index calculation module be x ₀ =1, y ₀ =0, z ₀ =θ, where θ is the input angle value,

(B) Iterative processing is performed through the hyperbolic CORDIC rotation pattern as shown in (b) in Figure 3:

x _i+1 = x _i +d _i ·y _i ·2 ^-i

y _i+1 =y _i +d _i ·x _i ·2 ^-i

z _i+1 = z _i -d _i ·tanh ^-1 2 ^-i

Among them, tanh ^-1 2 ^-i represents the value in the truth table of tanh ^-1 hyperbolic arctangent; d _i represents the symbol direction in the iterative process. In the rotation mode, the value of d _i is related to zi _i , that is

The output value obtained by iteration is:

x _n =A _n coshθ

y _n =A _n sinhθ

z _n = 0

当n→∞时，A_n≈0.82815936，旋转角度的总和为

输入角度θ的取值范围为[-1.1181,+1.1181]；in,

When _n →∞, An ≈ 0.82815936, the sum of the rotation angles is

The value range of the input angle θ is [-1.1181,+1.1181];

(C) Expand the convergence domain of the input angle, which can satisfy the calculation of the exponential function value of different input angles e, return to step (A), reset the input angle θ=Q·ln 2+R, where Q is the rounding of θ/ln 2 , R is the remainder of θ/ln 2, within the value range of the original input angle, we get:

x _n = cosh R/K _n

y _n =sinh R/K _n

z _n = 0

Multiply the output x _n , y _n by the modulus length compensation factor K _n to obtain the hyperbolic cosine value cosh R and the hyperbolic sine value sinh R respectively, and add the two to obtain e ^R according to e ^R =coshR+sinhR e ^θ = 2 ^Q · e ^R Multiply e ^R by 2 ^Q to obtain the value of the e exponential function of the reset input angle θ;

再将其通过平方根计算模块，得到阴影衰落值

其中，σ_n,0(t)表示均值为0，方差为1的高斯变量；(D) Set the input angle in step (C) to z ₀ =ξ _n,β σ _n,0 +α _n,β , then the final output

Then pass it through the square root calculation module to get the shadow fading value

Among them, σ _n,0 (t) represents a Gaussian variable with a mean of 0 and a variance of 1;

(E) Set the input angle in step (C) to w _m /2·ln(r _n ^Ray (t)), then finally output the Weibull fading value r _n ^Web (t)==exp(w _m /2· ln(r _n ^Ray (t))).

The calculation process of Nakagami fading value and path loss value in the present invention is as follows:

(I) Let the initial values of the logarithmic calculation module and the square root calculation module be x ₀ =α+1, y ₀ =α-1, z ₀ =0, where α is the required input angle value;

(II) Iterative processing is performed through the hyperbolic CORDIC vector mode as shown in (c) in Figure 3:

x _i+1 = x _i +d _i ·y _i ·2 ^-i

y _i+1 =y _i +d _i ·x _i ·2 ^-i

z _i+1 = z _i -d _i ·tanh ^-1 2 ^-i

Among them, tanh ^-1 2 ^-i represents the value in the truth table of tanh ^-1 hyperbolic arctangent; d _i represents the sign direction in the iterative process. In the vector mode, the value of d _i is related to y _i , that is,

The output value obtained by the last iteration is:

y _n = 0

当n→∞时，A_n≈0.82815936，α∈[0.1069,9.3573]；in,

When _n →∞, An ≈0.82815936, α∈[0.1069,9.3573];

(III) Expand the convergence domain of the input angle, which can satisfy the calculation of the logarithmic function value and the square root function value of different input angles, return to step (I), and reset the input angle to α=θ·4 ^Q , where θ∈[0.1069, 9.3573], Q is an integer, take Q∈[-10,7], the range of α can be extended from the original [0.1069,9.3573] to (0,512],

将x_n,z_n分别乘上K_n/2和2，可分别表示

和lnθ，则扩展收敛域后输入角度α的对数函数值和平方根函数值可表示为know

Multiply x _n , z _n by K _n /2 and 2 respectively, which can be expressed as

and lnθ, then the logarithmic function value and square root function value of the input angle α after expanding the convergence region can be expressed as

lnα=lnθ+Q·2ln 2

将其设置为步骤(Ⅲ)中的输入角度，再通过乘法器将此时步骤(Ⅲ)中x_n的输出

与

相乘，所得结果即为Nakagami衰落值

m表示独立高斯变量的个数；(IV) The Gaussian random variable generated by the complex exponential calculation module is squared and summed to obtain

Set it as the input angle in step (III), and then use the multiplier to convert the output of x _n in step (III) at this time

and

Multiply, the result is the Nakagami fading value

m represents the number of independent Gaussian variables;

(V) Set the input angle in step (III) as r _n ^α (t), then finally output the path loss value

(4) The reconfigurable channel superposition unit 1-5 performs a convolution operation on the output signal of the reconfigurable delay simulation unit 1-4 and the output signal of the reconfigurable fading generation unit 1-3, and obtains the output signal after the wireless channel. Output signal y(t), and perform automatic gain adjustment on the power of output signal y(t); wherein, output signal y(t) is

N represents the total number of channels,

(5) The result of automatic gain adjustment of the output signal is sent to the digital-to-analog conversion unit (1-6), and the analog signal superimposed with the channel fading delay is output to realize the reconfigurable channel fading simulation.

The fading twin method of the reconfigurable channel fading simulation device of the present invention can realize the real-time calculation of elementary functions required for the generation of channel fading, greatly optimize the utilization rate of hardware resources, improve the real-time performance of the reconfigurable channel fading simulation device, and has the advantages of It has the characteristics of strong versatility and high flexibility, and is suitable for the simulation of different channel fading in actual communication scenarios.

The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions that belong to the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (9)

1. A fading twin method for a reconfigurable channel fading simulation device is characterized by comprising the following steps:

(1) a user inputs communication scene parameters through the communication scene configuration unit (1-1), and transmits a communication scene to the reconfigurable fading generation unit (1-3) and the reconfigurable time delay simulation unit (1-4) through the PCIE bus; the communication scene parameters include: doppler frequency f of mth harmonic of nth channel_n,mAnd an initial phase theta_n,mAccumulated cosine value P_nStandard deviation xi of shadow fading_n,βShadow fading mean value alpha_n,βCoefficient of direct radiation rho_mAverage power p of fading of signal channels of each cluster_n ^ShaWeibull shape factor w_mAnd filter coefficients 1, 2.. S, channel delay parameters;

(2) the reconfigurable time delay analog unit (1-4) is based on the general communicationDividing channel time delay parameters provided by a signal scene configuration unit (1-1) into large time delay, integer time delay and decimal time delay, and respectively performing time delay operation on an input signal x (t) by using a DDR3 module, a RAM module and a polyphase filter structure, wherein the delayed signal is recorded as x (t-tau)_n) To a reconfigurable channel superposition unit (1-5), where τ_nRepresenting the path delay;

(3) the reconfigurable fading generation units (1-3) configure the Doppler frequency f of the mth harmonic wave of the nth channel according to the communication scene_n,mAnd an initial phase theta_n,mAccumulated cosine value P_nStandard deviation xi of shadow fading_n,βShadow fading mean value alpha_n,βCoefficient of direct radiation rho_mAverage power p of fading of signal channels of each cluster_n ^ShaWeibull shape factor w_mAnd filter coefficients 1, 2.. S, yielding different types of channel fading values r_n ⁱ(t) and different types of channel fading values r are selected by the fading selector_n ⁱ(t) outputting to a reconfigurable channel superposition unit (1-5); channel fading value r_n ⁱ(t) comprises: shadow fading value, Weibull fading value, Rayleigh fading value, Rice fading value, path loss value and Nakagami fading value;

(4) the reconfigurable channel superposition unit (1-5) performs convolution operation on the output signals of the reconfigurable time delay simulation unit (1-4) and the output signals of the reconfigurable fading generation unit (1-3) to obtain output signals y (t) after passing through a wireless channel, and performs automatic gain adjustment on the power of the output signals y (t); wherein the output signal y (t) is

N represents the total number of channels;

(5) and the result of the automatic gain adjustment of the output signal is transmitted to a digital-to-analog conversion unit (1-6) to output an analog signal superposed with the channel fading time delay.

2. The fading twin method for a reconfigurable channel fading simulation apparatus according to claim 1, wherein the step (2) comprises the sub-steps of:

(2.1) according to the time delay parameter provided by the communication scene configuration unit (1-1), taking the time delay parameter larger than the depth of the RAM as an address parameter of DDR3, taking the digital signal output by the analog-to-digital conversion unit (1-2) as input data of DDR3, and realizing large time delay simulation by using read-write address operation;

(2.2) rounding the time delay parameter smaller than the depth of the RAM by taking a clock cycle as a unit, taking the integer part as the address parameter of the RAM, taking the output signal of the DDR3 as the input data of the RAM, and realizing integer time delay simulation by utilizing read-write address operation;

and (2.3) using the fractional part as a control parameter of the polyphase filter, using an output signal of the RAM as input data of the polyphase filter, and realizing the simulation of fractional time delay by using coefficients 1, 2.

3. The fading twinning method for reconfigurable channel fading simulation apparatus of claim 1, wherein the rayleigh fading value and the rice fading value are iterated and summed through a circular CORDIC rotation mode

And (5) obtaining by complex exponential operation.

4. The fading twin method for reconfigurable channel fading simulation apparatus according to claim 1, wherein the shadow fading value and Weibull fading value are obtained by hyperbolic CORDIC rotation mode iteration and expanding the convergence domain of the input angle.

5. The fading twinning method for reconfigurable channel fading simulation apparatus as claimed in claim 1, wherein the Nakagami fading value and the path loss value are obtained by hyperbolic CORDIC vector mode iteration and expanding the convergence domain of the input angle.

6. A reconfigurable channel fading simulation apparatus that implements the fading twin method for the reconfigurable channel fading simulation apparatus according to claim 1, comprising: the system comprises a communication scene configuration unit (1-1), an analog-to-digital conversion unit (1-2), a reconfigurable fading generation unit (1-3), a reconfigurable time delay simulation unit (1-4), a reconfigurable channel superposition unit (1-5) and a digital-to-analog conversion unit (1-6); an output interface of the communication scene configuration unit (1-1) is connected with input interfaces of the reconfigurable fading generation unit (1-3) and the reconfigurable time delay simulation unit (1-4) through a PCIE bus, an output interface of the analog-to-digital conversion unit (1-2) is connected with an input interface of the reconfigurable time delay simulation unit (1-4), an output interface of the reconfigurable fading generation unit (1-3) and an output interface of the reconfigurable time delay simulation unit (1-4) are connected with an input interface of the reconfigurable channel superposition unit (1-5), and an output interface of the reconfigurable channel superposition unit (1-5) is connected with an input interface of the digital-to-analog conversion unit (1-6).

7. The reconfigurable channel fading simulation device according to claim 6, wherein the reconfigurable fading generation unit (1-3) is composed of a channel fading module and a fading selector; the channel fading module comprises: the system comprises a time-varying phase calculation module, a complex exponential calculation module, an e exponential calculation module, a logarithm calculation module and a square root calculation module, wherein the time-varying phase calculation module is used for calculating and generating a time-varying phase; the complex index calculation module is used for generating a Gaussian random variable and obtaining a Rayleigh fading value and a Rice fading value through the operation of an adder and a multiplier; the logarithm calculation module is used for calculating a logarithm value of Rayleigh fading and generating a Weibull fading value through the e-exponential calculation module; the e index calculation module is used for calculating a shadow fading value; the square root calculation module is used for calculating a path loss value and a Nakagami fading value; the fading selector is used for selecting a shadow fading value, a Weibull fading value, a Rayleigh fading value, a Rice fading value, a path loss value and a Nakagami fading value generated by the channel fading module to be input into the reconfigurable channel superposition unit (1-5).

8. The reconfigurable channel fading simulation device according to claim 6, wherein the reconfigurable delay simulation unit (1-4) is composed of a DDR3 module, a RAM module and a polyphase filter structure, the DDR3 module is used for receiving digital signals output by the analog-to-digital conversion unit (1-2) and performing large delay simulation by reading and writing DDR3 addresses; the RAM module is used for receiving an output signal of the DDR3 module and performing integer time delay simulation by reading and writing an RAM address; the multiphase filter structure is used for receiving the output signal of the RAM module and realizing high-precision decimal time delay simulation through multiple times of interpolation.

9. The reconfigurable channel fading simulation device according to claim 6, wherein the reconfigurable channel superposition unit (1-5) is composed of a channel convolution module and a gain control module, the channel convolution module convolves output signals of the reconfigurable fading generation unit (1-3) and the reconfigurable delay simulation unit (1-4), and takes a convolution result as an input of the gain control structure, and the gain control structure inputs the gain-controlled signal into the digital-to-analog conversion unit (1-6).

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