CN113611602A - Etching method - Google Patents
Etching method Download PDFInfo
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- CN113611602A CN113611602A CN202110862229.6A CN202110862229A CN113611602A CN 113611602 A CN113611602 A CN 113611602A CN 202110862229 A CN202110862229 A CN 202110862229A CN 113611602 A CN113611602 A CN 113611602A
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- etching
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- photoresist
- deep hole
- usg
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- 238000005530 etching Methods 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000011521 glass Substances 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000000945 filler Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an etching method for forming a smooth through hole profile, which comprises the following steps: step one, a doped silicon carbide film is arranged in a three-layer etching structure, the upper surface of the doped silicon carbide film is covered with a layer of undoped silicon glass USG, and an NFC layer is covered on the USG layer; the lower surface of the doped silicon carbide film is provided with a metal layer; deep holes are formed in the USG layer and are divided into two sections, and the diameter of the hole in the upper section is larger than that of the hole in the lower section; metal is filled in the holes; etching downwards to the lower section of the deep hole; step two, carrying out a first photoresist etching process, and etching and modifying the appearance of the doped silicon carbide film in the deep hole while etching the photoresist by using etching gas containing F; and step three, carrying out a second photoresist etching process to remove the residual photoresist. According to the invention, through the F-containing gas etching process of the photoresist, oxide residues are removed, the etching morphology of the deep hole is modified, and the reliability of deep hole filling is improved.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to an etching method capable of effectively removing oxide residues generated in tri-layer etching in an etching process.
Background
In the trench etching of Tri-layer process including photoresist (resist), Si-containing anti-reflective coating (SiARC) and spin-coated organic carbon, it is necessary to obtain a proper connection profile of the Via while ensuring the characteristic dimension CD of the trench and the profile of the trench, and the profile is very important for performance indexes such as reliability of the product. What is unavoidable in the etching process of the trench is that oxide fence-like residues exist at the junction of the NFC layer (a polymer similar to photoresist) and the oxide layer, and the oxide residues may cause poor appearance of the connection via in the subsequent etching, thereby affecting the reliability of the product, etc.
The existing Tri-layer process comprises the following steps:
depositing and etching a low-temperature silicon oxide layer;
etching the NFC layer;
depositing a Dielectric Anti-Reflective Coating (DARC) to suppress standing waves;
etching the silicon oxide layer;
removing the photoresist by using oxygen as etching gas;
and sixthly, etching the doped silicon carbide film on the bottom layer.
The above process causes the following problems: in the etching method, after the partial etching is completed, wall-shaped residues occur, so that the final side wall form of the trench or the hole has a double slope phenomenon, as shown in fig. 1 and fig. 2, after the trench in fig. 1 is continuously etched to form the structure shown in fig. 2, silicon oxide layer residues (indicated by dotted line circles in the figure) occur, and the defects can cause poor appearance of the next through hole, further influence the reliability of the product and the like.
Disclosure of Invention
The invention aims to provide an etching method for forming a smooth through hole side wall.
In order to solve the above problems, the etching method according to the present invention includes:
step one, a doped silicon carbide film is arranged in a three-layer etching structure, and the doped silicon carbide film is provided with two opposite surfaces; defining one surface of the doped silicon carbide film as an upper surface, and the other surface opposite to the upper surface as a lower surface; the upper surface is covered with a layer of undoped silicon glass USG, and an NFC layer is also covered on the USG layer; the lower surface of the doped silicon carbide film is provided with a metal layer;
deep holes are formed in the USG layer and are divided into two sections, and the diameter of the hole in the upper section is larger than that of the hole in the lower section; the deep hole is internally provided with filler; etching downwards to the lower section of the deep hole;
step two, carrying out a first photoresist etching process, and etching and modifying the appearance of the undoped silicon glass USG in the deep hole while etching the photoresist by adopting F-containing mixed etching gas;
and step three, carrying out a second photoresist etching process to remove the residual photoresist.
In a further improvement, the metal layer is copper.
In a further improvement, a step of etching the LTO layer of the low-temperature silicon oxide layer is included before the step one.
In a further improvement, in the second step, CF is adopted4And O2The mixed gas is used as etching gas to etch the photoresist and the USG; and (3) forming fence-shaped residues in the deep hole by the etching process in the step one, and etching and removing the fence-shaped undoped silicon glass USG residues by the first etching process containing F to modify the appearance in the deep hole.
In a further improvement, the etching bias power of the F-containing gas etching process is less than 80W.
In the third step, the second photoresist etching removal process adopts an etching gas atmosphere without F for etching, so that the residual photoresist in the deep hole is completely removed.
The atmosphere of the second etching gas is O2。
The etching method provided by the invention changes the traditional one-step photoresist removing process, firstly carries out synchronous etching on the photoresist and the undoped silicon glass USG by using the etching gas containing F in one step, modifies the etched appearance in the deep hole, removes fence-shaped residual etching of the undoped silicon glass USG, and then carries out the conventional photoresist etching process to obtain the deep hole appearance with a smooth inner wall, optimizes the subsequent deep hole filling effect and improves the reliability of the deep hole (connecting through hole).
Drawings
Fig. 1 is a schematic illustration of etching a silicon oxide layer in a three layer etch process.
FIG. 2 is a schematic diagram of fence-like residues formed after etching a silicon oxide layer in a three-layer etching process.
FIG. 3 is a schematic diagram of the first photoresist strip F gas etch removal performed in accordance with the present invention.
FIG. 4 is a schematic diagram of the second photoresist etch removal performed by the present invention.
FIG. 5 is a flow chart of the process steps of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
When an element or layer is referred to herein as being "on …", "adjacent …", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The etching method provided by the invention aims at the traditional three-layer (tri-layer) etching structure, solves the problem that Fence-shaped Oxide residue (Oxide Fence) occurs in etching, and because the problem can cause the subsequent reliability problem, a new process is required to be found to modify the etching appearance of the groove, so that the reliability of the process is improved.
As shown in fig. 1, which is a schematic diagram of an initial state structure of the three-layer etching process according to the present invention, for simplicity and pertinence of the illustration, other structures unrelated to the technical solution of the present invention, including a wafer substrate and other components, are omitted from the illustration 1, and only a basic structure of the three-layer etching process according to the technical solution of the present invention is shown. The structure concerned in fig. 1 has been substantially formed and has completed part of the conventional process, which is shown from bottom to top as a metal layer, a doped silicon carbide layer NDC, an undoped silicon glass layer USG and an NFC layer. The metal layer is copper in this embodiment, but may be another metal layer including aluminum. In the three-layer etching process, a deep hole structure is formed by etching, the deep hole structure is positioned in the USG layer of the undoped silicon glass and is divided into an upper section and a lower section, the diameter of the upper section of the deep hole is larger than that of the lower section, the section shape similar to an inverted convex shape is formed, the bottom of the deep hole is stopped on the surface of the doped silicon carbide layer, and photoresist is filled in the deep hole.
In the profile of the deep hole shown in fig. 1, the photoresist filled in the upper section with a larger diameter in the deep hole is basically etched, and only the photoresist in the lower section with a smaller diameter in the deep hole remains. After the photoresist on the upper part of the deep hole is etched, the opening of the lower section of the deep hole, namely the surface of the residual photoresist, has an inward concave shape, so that fence-shaped silicon oxide residues are formed on the periphery of the photoresist at the opening at the upper end of the lower section of the deep hole. This is the etch profile that the etch process inevitably results in, and requires measures to be taken to remove it.
As shown in fig. 3, the etching process of step two is performed, and the fence-like silicon oxide residue is removed simultaneously based on the removal of the photoresist. Specifically, in the etching process of this step, an etching gas containing F needs to be introduced, and CF is used in this embodiment4And O2The first photoresist removal etching process is performed on the mixed gas. During the etching process, fence-shaped undoped silicon glass USG residues are synchronously etched through the F-containing mixed gas, the etching bias power is less than 80W, the problem of fence-shaped silicon oxide residues generated during the etching process can be remarkably improved, and a better deep hole section appearance is formed.
After the first photoresist etching removal process, as shown in fig. 3, Oxide effect phenomenon formed in the conventional process has been completely removed, and only the lower half of the deep hole still retains the filler photoresist, so that the profile morphology achieves an ideal effect.
And then, carrying out a second photoresist removing process of the third step, wherein the etching process of the third step is the same as that of the traditional etching process, etching the photoresist by adopting a single oxygen etching atmosphere without F, etching and removing the photoresist inside the lower half part of the deep hole with a smaller diameter, and forming a profile with the shape as shown in figure 4 after removing, wherein the photoresist inside the deep hole is completely removed, the inner wall of the deep hole presents a smooth ideal shape, so that the deep hole has a better filling effect in the follow-up process, and the reliability of the device is improved.
Because the USG residue of the undoped silicon glass occurs in the photoresist etching removal process caused by the defects of the traditional process, the F-containing gas etching process of the photoresist is added in one step to modify the deep hole etching appearance, so that the deep hole etching process has smoother inner wall, and the subsequent deep hole filling effect is ensured.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. An etching method is characterized in that: the etching method is used for forming a smooth through hole profile, and comprises the following process steps:
step one, a doped silicon carbide film is arranged in a three-layer etching structure, and the doped silicon carbide film is provided with two opposite surfaces; defining one surface of the doped silicon carbide film as an upper surface, and the other surface opposite to the upper surface as a lower surface; the upper surface is covered with a layer of undoped silicon glass USG, and an NFC layer is also covered on the layer of undoped silicon glass USG; the lower surface of the doped silicon carbide film is provided with a metal layer;
deep holes are formed in the USG layer of the undoped silicon glass, the deep holes are divided into two sections, and the diameter of the holes in the upper section is larger than that of the holes in the lower section; the deep hole is internally provided with filler; etching downwards to the lower section of the deep hole;
step two, carrying out a first photoresist etching process, and etching and modifying the appearance of the undoped silicon glass USG in the deep hole while etching the photoresist by adopting F-containing mixed etching gas;
and step three, carrying out a second photoresist etching process to remove the residual photoresist.
2. The etching method according to claim 1, characterized in that: the metal layer is copper.
3. The etching method according to claim 1, characterized in that: before the first step, a low temperature silicon oxide layer LTO layer etching process step is further included.
4. The etching method according to claim 1, characterized in that: in the second step, CF is adopted4And O2The mixed gas is used as etching gas to etch the photoresistAnd etching the undoped silicon glass USG; and (3) forming fence-shaped residues of the USG in the deep hole by the etching process in the first step, and etching and removing the fence-shaped USG residues through the first etching process containing F to modify the appearance in the deep hole.
5. Etching method according to claim 1 or 4, characterized in that: the etching bias power of the F-containing gas etching process is less than 80W.
6. The etching method according to claim 1, characterized in that: in the third step, the second photoresist etching removal process adopts an etching gas atmosphere without F for etching, so that the residual photoresist in the deep hole is completely removed.
7. The etching method according to claim 6, wherein: the etching gas atmosphere is O2。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110862229.6A CN113611602B (en) | 2021-07-29 | 2021-07-29 | Etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110862229.6A CN113611602B (en) | 2021-07-29 | 2021-07-29 | Etching method |
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| Publication Number | Publication Date |
|---|---|
| CN113611602A true CN113611602A (en) | 2021-11-05 |
| CN113611602B CN113611602B (en) | 2024-01-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110862229.6A Active CN113611602B (en) | 2021-07-29 | 2021-07-29 | Etching method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115304291A (en) * | 2022-09-13 | 2022-11-08 | 江西沃格光电股份有限公司 | Method for processing through hole on glass substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399483B1 (en) * | 1999-08-12 | 2002-06-04 | Taiwan Semiconductor Manufacturing Company | Method for improving faceting effect in dual damascene process |
| US20050026085A1 (en) * | 2003-08-02 | 2005-02-03 | Myung Jung Hak | Methods for fabricating semiconductor devices |
| US20080146036A1 (en) * | 2006-12-18 | 2008-06-19 | Yu-Tsung Lai | Semiconductor manufacturing process |
| CN101320706A (en) * | 2007-06-07 | 2008-12-10 | 台湾积体电路制造股份有限公司 | Method for forming multi-layer semiconductor structure and its dual damascene |
| CN101937869A (en) * | 2009-06-30 | 2011-01-05 | 上海华虹Nec电子有限公司 | Damascus process integration method without dielectric film palisade residual risks |
-
2021
- 2021-07-29 CN CN202110862229.6A patent/CN113611602B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399483B1 (en) * | 1999-08-12 | 2002-06-04 | Taiwan Semiconductor Manufacturing Company | Method for improving faceting effect in dual damascene process |
| US20050026085A1 (en) * | 2003-08-02 | 2005-02-03 | Myung Jung Hak | Methods for fabricating semiconductor devices |
| US20080146036A1 (en) * | 2006-12-18 | 2008-06-19 | Yu-Tsung Lai | Semiconductor manufacturing process |
| CN101320706A (en) * | 2007-06-07 | 2008-12-10 | 台湾积体电路制造股份有限公司 | Method for forming multi-layer semiconductor structure and its dual damascene |
| CN101937869A (en) * | 2009-06-30 | 2011-01-05 | 上海华虹Nec电子有限公司 | Damascus process integration method without dielectric film palisade residual risks |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115304291A (en) * | 2022-09-13 | 2022-11-08 | 江西沃格光电股份有限公司 | Method for processing through hole on glass substrate |
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| CN113611602B (en) | 2024-01-19 |
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