CN113611245B

CN113611245B - Bidirectional transmission device and control method

Info

Publication number: CN113611245B
Application number: CN202110942857.5A
Authority: CN
Inventors: 李家栋; 黄建东; 张青松; 杨雪峰
Original assignee: SHENZHEN GREEN WELLSPRING SEMICONDUCTOR TECHNOLOGY Ltd
Current assignee: SHENZHEN GREEN WELLSPRING SEMICONDUCTOR TECHNOLOGY Ltd
Priority date: 2021-08-17
Filing date: 2021-08-17
Publication date: 2022-08-26
Anticipated expiration: 2041-08-17
Also published as: CN113611245A

Abstract

The embodiment of the application discloses a bidirectional transmission device and a control method, which are applied to the field of LED display and comprise a control module and a voltage conversion module. The first end of the control module is connected with the input end of the bidirectional transmission device, the second end of the control module is connected with the first end of the voltage conversion module, and the second end of the voltage conversion module is connected with the output end of the bidirectional transmission device. The control module comprises a delay unit and a control gate circuit, and is used for generating a pulse signal with a certain time sequence according to an input signal, and the pulse signal is used for controlling the input of the voltage conversion module. The voltage conversion module comprises a pull-up module and a pull-down module, and is used for obtaining a first output signal corresponding to the input signal according to the input of the voltage conversion module.

Description

Bidirectional transmission device and control method

Technical Field

The embodiment of the application relates to the field of LED display, in particular to a bidirectional transmission device and a control method.

Background

In an LED display device, a plurality of units generally transmit signals in a bidirectional manner. The bidirectional transmission is used as a more efficient transmission mode, the problem that single-line unidirectional transmission is easily affected by dead spots can be solved, and the display failure rate is greatly reduced. Meanwhile, the signal transmission efficiency of the bidirectional transmission is higher, and the circuit structure is simpler.

The bidirectional transmission system is generally composed of a controller and a bidirectional transmission unit (LED unit). Specifically, each bidirectional transmission unit can judge the transmission direction according to the input signal, and then select the corresponding controller according to the transmission direction, so as to realize free switching of the transmission direction and complete signal transmission. In a bidirectional transmission system, the commonly used input/output unit structure includes an upper pull line and a structure or a lower pull line or a structure, and the two structures will generate certain power consumption to affect the transmission efficiency of the bidirectional transmission system.

Therefore, how to improve the structure of the conventional bidirectional transmission unit to reduce the power consumption generated during signal transmission in the bidirectional transmission system becomes a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a bidirectional transmission device and a control method, which improve the structure of an input/output unit in a bidirectional transmission system to achieve the purpose of reducing power loss generated during signal transmission, thereby improving the transmission efficiency of the bidirectional transmission system.

A first aspect of an embodiment of the present application provides a bidirectional transmission apparatus, including:

the bidirectional transmission device comprises a control module and a voltage conversion module;

the first end of the control module is connected with the input end of the bidirectional transmission device, the second end of the control module is connected with the first end of the voltage conversion module, and the second end of the voltage conversion module is connected with the output end of the bidirectional transmission device;

the control module comprises a delay unit and a control gate circuit, and is used for generating a pulse signal with a certain time sequence according to an input signal, and the pulse signal is used for controlling the input of the voltage conversion module;

the voltage conversion module comprises a pull-up module and a pull-down module, and is used for obtaining a first output signal corresponding to the input signal according to the input of the voltage conversion module.

In an alternative embodiment, the bidirectional transmission device further includes an output driving module;

the input end of the output driving module is connected with the input end of the bidirectional transmission device; the output end of the output driving module is connected with the input end of the pull-up module or the pull-down module;

the output driving module is used for obtaining a second output signal opposite to the input signal according to the input signal.

In an alternative embodiment, the output driver module comprises an inverter.

In an alternative embodiment, the pull-up module includes a strong pull-up sub-module and a weak pull-up sub-module; the control gate circuit comprises an OR gate circuit;

the first input end of the OR gate circuit is connected with the output end of the delay unit, the second input end of the OR gate circuit is connected with the output end of the output driving module, and the output end of the OR gate circuit is connected with the input end of the strong pull-up sub-module; the output end of the output driving module is connected with the input end of the pull-down module.

In an optional embodiment, the strong pull-up sub-module comprises a first PMOS transistor, the weak pull-up sub-module comprises a first resistor, and the pull-down module comprises a first NMOS transistor;

the output end of the OR gate circuit is connected with the grid electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a power supply and is connected with the first end of the first resistor; the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and is connected with the second end of the first resistor; the second end of the first resistor is the output end of the bidirectional transmission device;

the grid electrode of the first NMOS tube is connected with the output end of the output driving module; the source electrode of the first NMOS tube is grounded.

In an alternative embodiment, the pull-down module includes a strong pull-down sub-module and a weak pull-down sub-module; the control gate circuit comprises an AND gate circuit;

the first input end of the AND gate circuit is connected with the output end of the delay unit, the second input end of the AND gate circuit is connected with the output end of the output driving module, and the output end of the AND gate circuit is connected with the input end of the strong pull-down submodule; the output end of the output driving module is connected with the input end of the pull-up module.

In an optional embodiment, the pull-up module comprises a second PMOS transistor, and the strong pull-down submodule comprises a second NMOS transistor; the weak pull-down submodule comprises a second resistor;

the output end of the AND gate circuit is connected with the grid electrode of the second NMOS tube; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube; and is connected with the first end of the second resistor; the source electrode of the second NMOS tube is grounded and is connected with the second end of the second resistor; the first end of the second resistor is the output end of the bidirectional transmission device;

the grid electrode of the second PMOS tube is connected with the output end of the output driving module; and the source electrode of the second PMOS tube is connected with a power supply.

A second aspect of the embodiments of the present application provides a method for controlling a bidirectional transmission apparatus, including:

sending an input signal to an input terminal of a bidirectional transmission device; the bidirectional transmission device comprises a control module and a voltage conversion module; the first end of the control module is connected with the input end, the second end of the control module is connected with the first end of the voltage conversion module, and the second end of the voltage conversion module is connected with the output end of the bidirectional transmission device;

according to the input signal, the control module determines the input of the voltage conversion module; the control module comprises a delay unit and a control gate circuit;

determining the output of the voltage conversion module according to the input of the voltage conversion module; the voltage conversion module comprises a pull-up module and a pull-down module, and the pull-up module and the pull-down module are used for obtaining a first output signal corresponding to the input signal;

and transmitting the first output signal to the output end of the bidirectional transmission device, and sending the first output signal outwards through the output end of the bidirectional transmission device.

In an alternative embodiment, the control module comprises a delay unit;

the control module is used for generating a pulse signal with a certain time sequence according to the input signal, and the pulse signal is used for controlling the input of the voltage conversion module.

A third aspect of the embodiments of the present application provides a bidirectional transmission system, including:

a plurality of any one of the bidirectional transmission devices, the selector and the data processing unit as provided in any one of the embodiments of the first aspect to the first aspect;

the bidirectional transmission device is used for receiving or sending transmission signals;

the selector is used for selecting a transmission path for the transmission signal according to the transmission signal;

the data processing unit is used for determining a target bidirectional transmission device according to the transmission path and sending a transmission signal to the target bidirectional transmission device.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, including the method for controlling a bidirectional transmission apparatus as provided in any one of the second to second aspects.

A fifth aspect of embodiments of the present application provides a computer product, including the method for controlling a bidirectional transmission apparatus as provided in any one of the second to the second aspects.

Through the above description, the bidirectional transmission apparatus provided in the embodiment of the present application includes a control module and a voltage conversion module, where the control module includes a delay unit, the delay unit is configured to receive an input signal, output a signal corresponding to the input signal after a delay time elapses, and control a pull-up module or a pull-down module included in the voltage conversion module according to the output signal. The pull-up module or the pull-down module can be controlled to be switched on and off through the time sequence pulse corresponding to the control module, so that the driving capability of the pull-up module or the pull-down module which is switched on all the time is reduced, and the effect of reducing power consumption is achieved. Therefore, the power consumption during signal transmission can be greatly reduced, and the efficiency of signal transmission is improved.

Drawings

Fig. 1 is a circuit architecture diagram of a bidirectional transmission system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a first bidirectional transmission apparatus according to an embodiment of the present disclosure;

fig. 3 is a circuit structure diagram of a first signal transmission system according to an embodiment of the present application;

fig. 4 is a circuit configuration diagram of a second signal transmission system according to an embodiment of the present application;

fig. 5 is a signal waveform diagram of a pin of the first bidirectional transmission apparatus during a high-level output process according to the embodiment of the present application;

fig. 6 is a circuit configuration diagram of a third signal transmission system according to an embodiment of the present application;

fig. 7 is a signal waveform diagram of a pin of the first bidirectional transmission apparatus during low-level output according to the embodiment of the present application;

fig. 8 is a schematic structural diagram of a first novel bidirectional transmission device according to an embodiment of the present application;

fig. 9 is a circuit configuration diagram of a first novel signal transmission system according to an embodiment of the present application;

figure 10 is a circuit block diagram of a second novel signal transmission system provided by an embodiment of the present application,

fig. 11 is a signal waveform diagram of a pin during high-level output of the first novel bidirectional transmission device provided in the embodiment of the present application;

fig. 12 is a circuit configuration diagram of a third novel signal transmission system according to an embodiment of the present application;

fig. 13 is a waveform diagram of signals at a pin of the first novel bidirectional transmission device during low-level output according to the embodiment of the present application;

fig. 14 is a schematic structural diagram of a second bidirectional transmission device according to an embodiment of the present application;

fig. 15 is a circuit configuration diagram of a fourth signal transmission system according to an embodiment of the present application;

fig. 16 is a circuit configuration diagram of a sixth signal transmission system according to an embodiment of the present application;

fig. 17 is a circuit configuration diagram of a sixth signal transmission system according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of a second novel bidirectional transmission device according to an embodiment of the present application;

fig. 19 is a circuit configuration diagram of a fourth novel signal transmission system according to an embodiment of the present application;

fig. 20 is a circuit configuration diagram of a fifth novel signal transmission system provided in the embodiment of the present application,

fig. 21 is a circuit configuration diagram of a sixth novel signal transmission system according to an embodiment of the present application;

fig. 22 is a flowchart illustrating a control method for a bidirectional transmission apparatus according to an embodiment of the present disclosure.

Detailed Description

The embodiment of the application provides a bidirectional transmission circuit and a control method, and the purpose of reducing power loss generated during signal transmission is achieved by improving the structure of an input/output unit in a bidirectional transmission system, so that the transmission efficiency of the bidirectional transmission system is improved.

In the LED display device, a plurality of units generally transmit signals in a bidirectional manner. The bidirectional transmission is used as a more efficient transmission mode, the problem that single-line unidirectional transmission is easily affected by dead spots can be solved, and the display failure rate is greatly reduced. Meanwhile, the signal transmission efficiency of the bidirectional transmission is higher, and the circuit structure is simpler.

Fig. 1 is a circuit architecture diagram of a bidirectional transmission system according to an embodiment of the present application; as shown in fig. 1, the bidirectional transmission system includes a plurality of bidirectional transmission devices, and the bidirectional transmission devices are connected to each other to transmit signals. Taking two bidirectional transmission devices as an example, the internal structures of the bidirectional transmission devices are similar, and a selection circuit is arranged in the middle of the bidirectional transmission devices. Wherein. Each bidirectional transmission device is used for receiving an input signal and transmitting the input signal outwards. The transmission direction can be judged according to the input (output) signal, and the automatic switching of the transmission direction is realized. The selection circuit selects a transmission path according to the signal output by the bidirectional transmission device, and determines the transmission direction so that the signal can be correctly transmitted.

The selection circuit comprises a watchdog, a data processing unit, a selector, a first AND gate circuit, a second AND gate circuit and a NOT gate circuit. The connection mode is shown in fig. 1, and is not described herein. The following describes the signal transmission process of the bidirectional transmission system in detail:

before the introduction, a brief introduction of the watchdog will be given. The watchdog is a chip for monitoring the program running state of the bidirectional transmission device in real time, so that the bidirectional transmission device can realize continuous work in an unmanned state. The working principle is that the watchdog chip is connected with one I/O pin of the bidirectional transmission device, the bidirectional transmission device regularly sends high level (or low level) to the I/O pin connected with the watchdog chip through program control, and the program statement is dispersedly put in the middle of other control statements of the bidirectional transmission device. Once the bidirectional transmission device falls into the endless loop state of a certain program section due to program runaway caused by interference, the watchdog chip can send a reset signal on a pin connected with a reset pin of the singlechip to reset the bidirectional transmission device due to the fact that the watchdog chip cannot obtain the signal sent by the bidirectional transmission device, namely, the program is executed from the initial position of the program memory, and therefore automatic reset of the bidirectional transmission device is achieved.

In the initial state of signal transmission, the watchdog defaults to "logic 0", i.e., outputs a low level. The "logic 0" controls the selector to select the data of the left bidirectional transfer device to be transferred to the data processing module without receiving the input data of the right bidirectional transfer device. At this time, the input data of one input end of the first and circuit is "logic 0", then the output end thereof is also "logic 0", and after passing through the not gate circuit of the bidirectional transmission device, a logic "1" is obtained, so that the PMOS transistor in the left bidirectional transmission device can be controlled to be turned off, that is, the I/O pin of the left bidirectional transmission device is the input pin. And the input data of one input end of the second and circuit is logic '1' obtained after the output of the watchdog passes through the not circuit, so that the data of the data processing module is transmitted to the I/O pin of the right bidirectional transmission device through the second and circuit, and then transmitted to other devices through the right bidirectional transmission device, namely the I/O pin of the right bidirectional transmission device is the output pin.

The watchdog needs to detect the data of the bidirectional transmission device in real time, and when the left bidirectional transmission device has no data input (no level change), the state of the watchdog changes to logic "1" after a while. At this time, the selector selects the data of the right bidirectional transmission device, the data of the left bidirectional transmission device is not received, the input data of one input end of the first and gate circuit is logic '1', at this time, the data of the data processing module can be transmitted to the I/O pin of the left bidirectional transmission device through the first and gate circuit and then transmitted to other devices through the left bidirectional transmission device, and at this time, the I/O pin of the left bidirectional transmission device is an output port. The input data of one input end of the second and-gate circuit is logic '0' obtained after the output of the watchdog chip passes through the not-gate circuit, then the output of the second and-gate circuit is also logic '0', and logic '1' is obtained after the output of the second and-gate circuit passes through the not-gate circuit of the right bidirectional transmission device, so that the PMOS of the right bidirectional transmission device is closed, namely, the I/O pin of the right bidirectional transmission device is an input port. The data processing module has the functions of local interception, regeneration and data conversion.

As can be seen from the above description, in the bidirectional transmission system, the watchdog chip switches the attribute of each bidirectional transmission device by detecting the state thereof in real time, and determines the signal transmission path to achieve the purpose of bidirectional transmission. Among them, power loss in signal transmission is a key factor affecting the efficiency of signal transmission. The power loss has a great relationship with the structure of the input-output system. The conventional bidirectional transmission device may be generally a pull-up line and structure or a pull-down line or structure, which will be described in detail below, and the power loss corresponding to each structure is analyzed.

Firstly, an upper stay wire and a structure:

fig. 2 is a schematic structural diagram of a first bidirectional transmission device according to an embodiment of the present disclosure, and as shown in fig. 2, the bidirectional transmission device includes a pull-up resistor, an inverter, a schmitt trigger, and an NMOS transistor. One pin OUT1 of the bidirectional transmission device is connected with the input end of the inverter, and the output end of the inverter is connected with the grid electrode of the NMOS tube. Meanwhile, one end of the pull-up resistor is connected with a power supply, the other end of the pull-up resistor is connected with the drain electrode of the NMOS tube, and the source electrode of the NMOS tube is grounded. Meanwhile, one end of the pull-up resistor connected with the drain electrode of the NMOS tube is connected with the first end of the Schmitt trigger and is also connected with the other pin PAD of the bidirectional transmission device, and the second end of the Schmitt trigger is connected with the third pin IN1 of the bidirectional transmission device.

Next, a signal transmission process between two bidirectional transmission devices is described, and fig. 3 is a circuit configuration diagram of a first signal transmission system according to an embodiment of the present application. As shown in fig. 3, the structures of the device a and the device B are the same, and the internal circuit thereof is the same as the structure of the bidirectional transmission device in the embodiment shown in fig. 2, which is not repeated herein. It will be appreciated that there is also a selection circuit between device a and device B, similar to the selection circuit between the two bidirectional transfer devices in the embodiment shown in fig. 1, and the selection circuits for device a and device B are simplified in fig. 3 for ease of description. With device a as the output port and device B as the input port, data will be transferred from device a to device B. It will be understood that the process of transferring data from device a to device B is similar and will not be repeated.

When device a is acting as an output, data will be transmitted from device a's OUT1 pin to the PAD pin, and device B is acting as an input, data will be received by device B's PAD pin, shaped by device B's schmitt trigger, and transmitted to device B's IN2 pin. Similarly, when device B is the output, data will be transmitted from the OUT2 pin of device B to the PAD pin, and device a is the input, data will be received by the PAD pin of device a, shaped by the schmitt trigger of device a, and transmitted to the IN1 pin of device a.

With the above structure, the following describes a specific process of data transmission:

1. transmitting a high level:

where "0" indicates a low level and "1" indicates a high level. The device B is used as an input port, the level of OUT2 is always high, so the level of the inverter INV2 is low, the output end of the inverter INV2 is connected to the gate of the NMOS transistor NM2, the gate voltage is low, and the NM2 is always in the off state.

When the level of the OUT1 port of the device a is switched from low level to high level when transmitting high level, the level of the output end of the inverter INV1 is switched from high level to low level, and the gate voltage of the NMOS transistor NM1 of the device a is low level, and NM1 is not turned on. At this time, the resistor R1 and the resistor R2 are connected between the VDD power supply and PAD, and since NM1 is turned off, the PAD of the device a is not pulled down by NM1, and the PAD is pulled up by the resistor R1 and the resistor R2. After a period of time T2, the voltage of PAD will be greater than the threshold voltage of Schmitt SMT2 and SMT2 will output a high level to IN 2. And after time T1, the voltage of PAD is pulled up to the power supply voltage, and the SMT2 output tends to be stable and always outputs high level to IN 2.

Fig. 4 is a circuit configuration diagram of a second signal transmission system according to an embodiment of the present application. Fig. 4 illustrates the flow direction of the high level transmission current, and fig. 5 illustrates the waveform of the signal of each pin during the high level output process. As shown in fig. 4, the dotted line indicates the flowing direction of the transmission current, and the cross indicates that the transmission current cannot flow. Since NM1 and NM2 are both turned off, the transmission current cannot flow to ground through NM1 and NM2, and only flows to PAD through resistor R1 and resistor R2, respectively.

Thus, when a high level is transmitted, the corresponding power consumption is the charge Q required to pull up the PAD voltage from the low level to the power supply voltage, and when the PAD voltage changes to the power supply voltage after T1 time, no transmission current is available any more. At this time, the total resistance value on the current path is a value obtained by connecting the resistor R1 and the resistor R2 in parallel, and if the resistances of the resistor R1 and the resistor R2 are both RL1, the total resistance value is RL 1/2.

According to the formula Q (charge) ═ U/[ (RL1/2) × t ] (voltage/resistance × time), t ═ RL ═ Q/2 × U can be obtained. When Q is fixed to U, t is in direct proportion to RL1, with the larger RL1 the larger t. In order to normally transmit data, t needs to have a smaller value to ensure the slope of the data rising edge, so the resistance values of the resistor R1 and the resistor R2 need to have a smaller value.

2. Transmitting low level:

similarly, "0" indicates a low level and "1" indicates a high level. The device B is used as an input port, the level of OUT2 is always high, so the level of the inverter INV2 is low, the output end of the inverter INV2 is connected to the gate of the NMOS transistor NM2, the gate voltage is low, and the NM2 is always in the off state.

When the level of the OUT1 port of the device a is switched from high level to low level when transmitting low level, the level of the inverter INV1 rises from low level to high level, and the output terminal of the inverter INV1 is connected to the gate of the NMOS transistor NM1 of the device a, so the gate voltage is high level, and NM1 is turned on. Since the pull-down driving capability of NM1 is much larger than the pull-up driving capability of resistor R1 connected in parallel with resistor R2, the PAD level of device a will be quickly pulled down from a high level to a low level, which is the voltage division of the parallel resistor obtained by connecting resistor R1 and resistor R2 in parallel with the internal resistor NM 1. If the resistances of the resistors R1 and R2 are both RL1 and the internal resistance of NM1 is RN, the PAD voltage is VDD × [ RN/(RN + RL1/2) ]. This voltage is lower than the threshold voltage of the Schmitt trigger of device B, so the Schmitt trigger of device B will output a low level to pin IN2 of device B.

If the voltage is V1 when it is pulled down to low level rapidly, according to the above formula, V1 is VDD × RN/(RN + RL/2) ], and V1 is smaller than the threshold voltage Vt of the schmitt trigger of device B, and if VDD is 5V and Vt is 0.5V, RN needs to be smaller than RL/9.

Fig. 6 is a circuit structure diagram of a third signal transmission system according to an embodiment of the present application, where fig. 6 illustrates a flow direction of a low level transmission current, and fig. 7 is a signal waveform diagram of each pin in a low level output process. In fig. 6, the dotted line indicates the direction in which the current flows, and the cross indicates that the current cannot flow. Since NM2 is turned off, the current cannot flow to ground through NM2, and the current can only flow to ground through NM1 through resistors R1 and R2. The resistance values of the resistor R1 and the resistor R2 are RL1, the internal resistance of the NMOS transistor NM1 is RN, and the total resistance value is RN + RL 1/2. And the power supply voltage is VDD, the current I is VDD/(RN + RL 1/2). At this time, according to the power consumption calculation formula W (power consumption) ═ U × I × t (voltage × current × time), the power consumption W1 at this time is VDD × VDD/(RN + RL1/2) × t, and the power consumption W1 is in a direct proportion to the time t, and thus it is understood that the power consumption W1 increases as the time t for transmitting the low level increases.

From the above description, it can be seen that the conventional pull-up line and structure will generate large power consumption when transmitting low level or high level. In order to reduce power consumption in the signal transmission process, the signal transmission efficiency is improved. The embodiment of the application improves the traditional upper stay wire and structure, obtains a new bidirectional transmission device with the upper stay wire and structure, and can greatly reduce the power consumption during signal transmission.

Fig. 8 is a schematic structural diagram of a first novel bidirectional transmission device according to an embodiment of the present disclosure, and as shown in fig. 8, the bidirectional transmission device includes a pull-up module, a control module, an output driving module, a schmitt trigger, and a pull-down module. One pin OUT of the bidirectional transmission device is connected with the input end of the output driving module, and the output end of the output driving module is connected with the pull-down module. Meanwhile, the pin OUT is also connected with the input end of the control module, and the output end of the control module is connected with the pull-up module. One end of the pull-down module is connected with one end of the pull-up module and is connected with one pin PAD of the bidirectional transmission device, and the other end of the pull-down module is grounded. The pull-up module comprises a controllable strong pull-up sub-module and an uncontrollable weak pull-up sub-module.

Specifically, the output driving module comprises an inverter INV, the control circuit comprises a delay module and an or gate circuit, the controllable strong pull-up sub-module comprises a first PMOS transistor, the uncontrollable weak pull-up sub-module comprises a first resistor, and the pull-down module comprises a first NMOS transistor. The specific connection relationship is as follows: the pin OUT of the bidirectional transmission device is connected with the input end of the inverter INV, and the output end of the inverter INV is connected with the grid electrode of the first NMOS tube. Meanwhile, a pin OUT of the bidirectional transmission apparatus is connected to one end of the delay block, the other end of the delay block is connected to a first input end of the or gate circuit, and an output end of the inverter INV is connected to a second input end of the or gate circuit. The output end of the OR gate circuit is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with a power supply VDD, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded. One end of the first resistor is connected with the drain electrode of the first PMOS tube, the other end of the first resistor is connected with the source electrode of the first PMOS tube, and one pin PAD of the bidirectional transmission device is connected with the drain electrode of the first PMOS tube. The first terminal of the Schmitt trigger is connected to a PAD of the bi-directional transmission device, and the second terminal is connected to a third pin IN of the bi-directional transmission device.

Next, a signal transmission process between two bidirectional transmission devices is described, and fig. 9 is a circuit configuration diagram of a first novel signal transmission system according to an embodiment of the present application. As shown in fig. 9, the structures of the device E and the device F are the same, and the internal circuit thereof is the same as the structure of the bidirectional transmission device in the embodiment shown in fig. 8, which is not repeated herein. It will be appreciated that there is also a selection circuit between device E and device F, similar to the selection circuit between the two bidirectional transfer devices in the embodiment shown in fig. 1, and the selection circuits of device E and device F are simplified in fig. 9 for ease of description. With device E as the output port and device F as the input port, data will be transferred from device E to device F. It will be appreciated that the process of transferring data from device E to device F is similar and will not be repeated.

When device E is the output, data will be transmitted from the OUT5 pin of device E to the PAD pin, and device F is the input, data will be received by the PAD pin of device F, shaped by the schmitt trigger of device F, and transmitted to the IN6 pin of device F. Similarly, when device F is used as the output port, data will be transmitted from the OUT6 pin of device F to the PAD pin, and device E is used as the input port, data received by the PAD pin of device E will be transmitted to the IN5 pin of device A after being shaped by the Schmitt trigger of device E.

1. transmitting high level:

where "0" indicates a low level and "1" indicates a high level. The device F is used as an input port, the level of OUT6 is always high, the level of the inverter INV6 is low, the level of the delay unit of the device F is high, OR the level of the gate OR6 is high, that is, the gate voltage of the gate of the first NMOS transistor NM6 of the device F is low, so the NM6 is always in the off state. The gate voltage of the gate of the first PMOS transistor PM6 of the device F is high, so the PM6 is also in the off state.

When the high level is transmitted, the level of OUT5 of the device E is switched from low to high, and the level of the inverter INV5 is lowered from high to low, so the gate level of the gate of the first NMOS transistor NM5 of the device E is low, and NM5 is turned off. The delay unit of the device E is delayed by T time, and then the level is raised from the low level to the high level. Since the inputs of the OR gate OR5 of the device E are the output of the delay unit and the output of the inverter INV5, the OR gate OR5 generates a low level pulse signal with a time width of T. The first PMOS transistor PM5 with strong pull-up capability will be open during this time. Since NM5 and NM6 are turned off and there is no path for current to flow to ground, PM5 quickly pulls the PAD voltage up to the supply voltage. After the time T, the PM5 is turned off, and the pull-up of the PAD voltage is maintained by the first resistor R5 with low pull-up capability, so that the PAD voltage is stabilized near the power supply. When the level of PAD is greater than the threshold voltage of the Schmitt trigger of device F, the Schmitt trigger outputs a high level to pin IN6 of device F.

Fig. 10 is a circuit structure diagram of another signal transmission system according to an embodiment of the present application, where fig. 10 illustrates a flow direction of a transmission current during high-level transmission, where a dotted line indicates a flowing direction of the transmission current, and a cross indicates that the transmission current cannot flow. Fig. 11 is a waveform diagram of signals during high-level output of each pin. Because the first NMOS transistors NM5 and NM6 are turned off, the current does not flow to the ground, and the current can only flow to the PAD through the first resistor R5 and the first PMOS transistor PM5 and resistor R6 which are turned on for T time, respectively, so that the power consumption in transmitting the high level is the charge Q required for pulling up the PAD from the low level to the power supply, and after the PAD is pulled up to the power supply, the current is not consumed any more.

If the resistance values of the first resistor R5 and the first resistor R6 are both RL2, the internal resistance of the first PMOS transistor PM5 is RP. From Q (charge) ═ U/RP × T (voltage/resistance × time), T ═ RP (Q/U) was obtained. According to the formula, when Q and U are fixed, T and RP are in a proportional relation. Since PM5 needs to be able to quickly pull up the PAD level from the low level to the supply voltage, RP needs to be a small value.

Since the PM5 has strong pull-up capability and can quickly pull up the PAD to the power supply within T time, the resistor R5 only needs weak pull-up capability to stabilize the PAD at the power supply voltage, so the resistance R5 of the resistor R5 can be set to a larger resistance according to specific requirements. In contrast to the old pull-up, both at the transmit high level are charges Q needed to pull up the PAD level from the low level to the power supply, so the new dual pull-up consumes the same power as the old pull-up at the transmit high level. But because of the PMOS tube with strong pull-up capability, the resistor R5 with weak pull-up capability can select a resistor with larger resistance value, thereby reducing the requirement on the driving capability of the weak pull-up module.

2. Transmitting low level:

similarly, "0" indicates a low level and "1" indicates a high level. The device F is used as an input port, the level of OUT6 is always high, the level of the inverter INV6 is low, the level of the delay unit of the device F is high, OR the level of the gate OR6 is high, that is, the gate voltage of the gate of the first NMOS transistor NM6 of the device F is low, so the NM6 is always in the off state. The gate voltage of the gate of the first PMOS transistor PM6 of the device F is high, so the PM6 is also in the off state.

When the low level is transmitted, the level of the pin OUT5 of the device E is switched from the high level to the low level, and the level of the inverter INV5 is raised from the low level to the high level. At this time, the gate voltage of the PM5 is high, and the PM5 is off, the gate voltage of the NM5 of the first NMOS transistor is high, the NM5 is on, the level of the delay unit of the device E needs to be decreased from high to low after T time, and the level of the OR gate OR5 is kept high during this time. At this time, since the PM5 is turned off, only the first resistor R5 and the first resistor R6 remain weakly pulled up. Since the pull-down capability of the first NMOS transistor NM5 of the device E is much larger than the pull-up capability of the resistor R5 connected in parallel with the resistor R6, the PAD level of the device E will be quickly pulled down from high level to low level V3, and V3 is the voltage division of the resistor R5, the resistor R6 connected in parallel and the internal resistor NM 5. If the resistances of the resistors R5 and R6 are both RL and the internal resistance of NM5 is RN, the voltage V3 is VDD (RN/(RN + RL/2)). At this time, V3 is lower than the threshold voltage of the Schmitt trigger of device F, so the Schmitt trigger will output a low level to pin IN6 of device F.

Fig. 12 is a circuit structure diagram of another signal transmission system according to an embodiment of the present application, where fig. 12 indicates a flow direction of a transmission current during low-level transmission, where a dotted line indicates a current flowing direction, and a cross indicates that a current cannot flow. Fig. 13 is a waveform diagram of signals during the low level output of each pin. Since NM6 is turned off, current cannot flow from PAD to ground through NM6, and current flows to the first NMOS transistor NM5 and to ground through only the first resistors R5 and R6. If the resistance values of the first resistors R5 and R6 are both RL2 and the internal resistance of NM5 is RN, the total resistance is RN + RL2/2, and if the power voltage is VDD, i.e., the transmission current I is VDD/(RN + RL/2). At this time, according to the power consumption calculation formula W (power consumption) ═ U × I × t (voltage × current × time), the new dual pull-up transfer low level power consumption W ═ VDD/(RN + RL2/2) × t.

Comparing the power consumption of the new bidirectional transmission device in transmitting the low level with the power consumption of the old bidirectional transmission device in transmitting the low level, it can be seen that the new bidirectional transmission device and the old bidirectional transmission device both need a module for strong pull-down driving in transmitting the low level, and therefore the on internal resistances of the NMOS transistors are consistent. However, in the old bidirectional transmission device, the pull-up resistor is used to pull up the PAD from a low level to a power supply voltage quickly, so that a strong pull-up driving capability is required, and the new bidirectional transmission device adopts a dual pull-up structure, in which the resistor is a weak pull-up module and only needs to provide a weak driving capability for stabilizing the power supply voltage. Therefore, the resistance of the resistor in the new bidirectional transmission device is far greater than that of the pull-up resistor in the old bidirectional transmission device, that is, RL1 is far less than RL2, the power consumption of the old bidirectional transmission device is VDD/(R N + RL1/2) t, and the power consumption of the new bidirectional transmission device is VDD/(RN + RL2/2) t, so that the power consumption of the old bidirectional transmission device is far greater than that of the new bidirectional transmission device.

Namely, when the new bidirectional transmission device transmits the low-level signal, the power consumption is far less than that of the old bidirectional transmission device, and the efficiency of signal transmission is greatly improved.

Second, pull-down lines or structures:

fig. 14 is a schematic structural diagram of a second bidirectional transmission device according to an embodiment of the present disclosure, and as shown in fig. 14, the bidirectional transmission device includes a pull-down resistor, an inverter, a schmitt trigger, and a PMOS transistor. One pin OUT3 of the bidirectional transmission device is connected with the input end of the inverter, and the output end of the inverter is connected with the grid electrode of the second PMOS tube. Meanwhile, the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with one end of the pull-down resistor, and the other end of the pull-down resistor is grounded. Meanwhile, one end of the pull-down resistor connected with the drain electrode of the PMOS tube is connected with the first end of the Schmitt trigger and is also connected with the other pin PAD of the bidirectional transmission device, and the second end of the Schmitt trigger is connected with the third pin IN3 of the bidirectional transmission device.

Next, a signal transmission process between two bidirectional transmission devices is described, and fig. 15 is a circuit configuration diagram of a signal transmission system according to an embodiment of the present application. As shown in fig. 15, the structures of the device C and the device D are the same, and the internal circuit thereof is the same as the structure of the bidirectional transmission device in the embodiment shown in fig. 14, which is not repeated herein. It will be appreciated that there is also a selection circuit between device C and device D, similar to the selection circuit between the two bidirectional transmission devices in the embodiment shown in fig. 1, and the selection circuits of device C and device D are simplified in fig. 15 for ease of description. With device C as the output port and device D as the input port, data will be transferred from device C to device D. It will be understood that the process of transferring data from device D to device C is similar and will not be repeated.

When device C is the output, data will be transmitted from the OUT3 pin of device C to the PAD pin, and device D is the input, data will be received by the PAD pin of device D, shaped by the schmitt trigger of device D, and transmitted to the IN4 pin of device D. Similarly, when device D is the output, data will be transmitted from the OUT4 pin of device D to the PAD pin, and device C is the input, data will be received by the PAD pin of device C, shaped by the Schmitt trigger of device C, and transmitted to the IN3 pin of device A.

1. transmitting a high level:

where "0" represents a low level and "1" represents a high level. When the device D is used as the input port, the level of OUT4 is always low, the level of the inverter INV4 is high, and the level of the delay unit of the device F is high, the gate voltage of the second PMOS transistor of the device D is high, so the PM4 is always in the off state.

When the high level is transmitted, the level of the pin OUT3 of the device C is switched from low level to high level, the level of the inverter INV3 is lowered from high level to low level, and the gate voltage of the second PMOS transistor PM3 of the device C is low level, so the PM3 is turned on. Since the pull-up driving capability of the PM3 is much stronger than that of the second resistor R3 connected in parallel with the second resistor R4, the voltage of the PAD of the device C will be quickly pulled up from the low level to the high level by the PM 3. The high level is the voltage division of the parallel resistance value of the second resistor R3 and the second resistor R4 and the internal resistance of the PM 3. If the resistances R3 and R4 are RL3 and the internal resistance of the PMOS transistor PM3 is RP1, the high level is VDD [ (RL3/2)/(RP1+ RL 3/2)). This voltage value is now greater than the threshold voltage of the Schmitt trigger of device D, so the Schmitt trigger will transmit an output high to pin IN4 of device D.

Fig. 16 is a circuit configuration diagram of another signal transmission system according to an embodiment of the present application, and a flow direction of a transmission current in high level transmission is indicated in fig. 16. The dotted line indicates the direction in which the current flows, and the cross indicates that the current cannot flow. Since PM4 is turned off, current cannot flow from VDD to PAD through PM4, and current can only flow to ground through PM3 through the second resistor R3 and the second resistor R4, respectively. If the resistances of the resistors R3 and R4 are RL3, and the internal resistance PR1 of the PMOS tube PM3 is PR 1+ RL3/2, the total resistance is RP1+ RL3/2, and if the voltage is VDD, the transmission current is VDD/(RP1+ RL 3/2). According to the power consumption calculation formula W (power consumption) ═ I × t (voltage × current × time), that is, the power consumption of the bidirectional transfer device when transmitting a high level is VDD × VDD/(RP1+ RL3/2) × t, and the power consumption is in a direct proportional relationship with time t, it is known that the power consumption of the old bidirectional transfer device increases as the time t for pulling down the high level increases.

2. Transmitting a low level:

similarly, "0" indicates a low level and "1" indicates a high level. When the device D is used as the input port, the level of OUT4 is always low, the level of the inverter INV4 is high, and the level of the delay unit of the device F is high, the gate voltage of the second PMOS transistor of the device D is high, so the PM4 is always in the off state.

When transmitting a low level, the level transmitted by the pin OUT3 of the device C is switched from a high level to a low level, the level of the inverter INV3 is raised from a low level to a high level, and the gate voltage of the second PMOS transistor PM3 of the device C is at a high level, so the PM3 changes from an on state to an off state, the pull-up driving of the PM3 is turned off, the level of the PAD of the device C is pulled down by the second resistor R3 and the second resistor R4 together, the voltage of the PAD of the device C is lower than the threshold voltage of the schmitt trigger of the device D after the time T2, and the SMT4 outputs a low level to the pin IN4 of the device D. After time T1, the charge on PAD of device C is fully discharged, and the PAD voltage will remain low, and the power consumption of the power supply is not consumed when PAD is discharged.

Fig. 17 is a circuit structure diagram of another signal transmission system according to an embodiment of the present application, where fig. 17 indicates a flow direction of a transmission current during low-level transmission, a dotted line indicates a current flowing direction, and a cross indicates that a current cannot flow. Since both PM3 and PM4 are in an off state, current cannot flow from the power supply to the PAD through PM3 and PM4, and only the PAD flows to ground through R3 and R3, so that the PAD only discharges charge, that is, power consumption of the power supply is not consumed.

At this time, the total resistance in the current path is R3 and R4 in parallel, and if the resistance values of the resistor R3 and the resistor R4 are both RL3, the total resistance is RL 3/2. From Q (charge) ═ U/(RL3/2) × t (voltage/resistance × time), t ═ RL3 ═ Q/2 × U was obtained. From the formula, when Q and U are fixed, t is in a direct proportional relation with RL3, and the larger RL3 is, the larger t is. In order to normally transmit data, the slope of the data falling edge is ensured, so t needs to be a small value, and the resistance RL3 needs to be a small value.

In order to reduce power consumption in the signal transmission process, the signal transmission efficiency is improved. The embodiment of the application improves the traditional pull-down line or structure, obtains a novel bidirectional transmission device with the pull-down line or structure, and can greatly reduce power consumption during signal transmission.

Fig. 18 is a schematic structural diagram of a second novel bidirectional transmission device according to an embodiment of the present application, and as shown in fig. 18, the bidirectional transmission device includes a pull-up module, a control module, an output driving module, a schmitt trigger, and a pull-down module. One pin OUT of the bidirectional transmission device is connected with the input end of the output driving module, and the output end of the output driving module is connected with the pull-up module. Meanwhile, the pin OUT is also connected with the input end of the control module, and the output end of the control module is connected with the pull-down module. One end of the pull-down module is connected with one end of the pull-up module and is connected with one pin PAD of the bidirectional transmission device, and the other end of the pull-down module is grounded. The pull-down module comprises a controllable strong pull-down submodule and an uncontrollable weak pull-down submodule.

Specifically, the output driving module comprises an inverter INV, the control circuit comprises a delay module and an and circuit, the controllable strong pull-down submodule comprises a second NMOS transistor, the uncontrollable weak pull-down submodule comprises a second resistor, and the pull-up module comprises a second PMOS transistor. The specific connection relationship is as follows: the pin OUT of the bidirectional transmission device is connected with the input end of the inverter INV, and the output end of the inverter INV is connected with the grid electrode of the second PMOS tube. Meanwhile, a pin OUT of the bidirectional transmission device is connected with one end of the delay module, the other end of the delay module is connected with a first input end of the AND circuit, and an output end of the inverter INV is connected with a second input end of the AND circuit. The output end of the AND gate circuit is connected with the grid electrode of the second NMOS tube, the source electrode of the second PMOS tube is connected with the power supply VDD, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded. One end of the first resistor is connected with the drain electrode of the second NMOS tube, the other end of the first resistor is connected with the source electrode of the second NMOS tube, and one pin PAD of the bidirectional transmission device is connected with the drain electrode of the first PMOS tube. The first terminal of the Schmitt trigger is connected to a PAD of the bidirectional transmission device, and the second terminal is connected to a third IN of the bidirectional transmission device.

Next, a signal transmission process between two bidirectional transmission devices is described, and fig. 19 is a circuit configuration diagram of a signal transmission system according to an embodiment of the present application. As shown in fig. 19, the structures of the device G and the device H are the same, and the internal circuit thereof is the same as the structure of the bidirectional transmission device in the embodiment shown in fig. 18, which is not repeated herein. It will be appreciated that there is also a selection circuit between the device G and the device H, similar to the selection circuit between the two bidirectional transfer devices in the embodiment shown in fig. 1, and the selection circuits of the device G and the device H are simplified in fig. 19 for the sake of convenience of description. With device G as the output port and device H as the input port, data will be transferred from device G to device H. It will be understood that the process of transferring data from device H to device G is similar and will not be repeated.

When the device G is used as an output port, data is transmitted from the OUT7 pin of the device G to the PAD pin, and when the device H is used as an input port, the data received by the PAD pin of the device H is transmitted to the IN8 pin of the device H after being shaped by the Schmitt trigger of the device H. Similarly, when device H is used as the output port, data will be transmitted from the OUT8 pin of device H to the PAD pin, and device G is used as the input port, data will be received by the PAD pin of device G, shaped by the Schmitt trigger of device G, and transmitted to the IN7 pin of device G.

1. transmitting a high level:

where "0" represents a low level and "1" represents a high level. The device H is used as an input port, the level of OUT8 is always low, the level of the inverter INV8 is high, the level of the delay unit of the device H is low, the level of the AND circuit AND8 is low, that is, the gate voltage of the gate of the second NMOS transistor NM8 of the device F is low, AND therefore, the NM8 is always in the off state. The gate voltage of the gate of the second PMOS transistor PM8 of the device F is high, so the PM8 is also in the off state.

When the high level is transmitted, the level of the pin OUT7 of the device G is switched from low level to high level, the level of the inverter INV7 is lowered from high level to low level, AND at this time, the gate level of the second PMOS transistor PM7 of the device G is low level, so that the PM7 is turned on, the delay unit of the device G is raised from low level to high level after delaying for T time, the level of the AND gate AND7 is always low level, AND at this time, the gate level of the NM7 of the second NMOS transistor is low level, so that the NM7 is turned off. Since NM7 is turned off and the driving capability of PM7 is much stronger than the parallel connection of resistor R7 and resistor R8, the PAD voltage will be quickly pulled up from a low level to a high level, which is the voltage division of the parallel connection of resistor R7 and resistor R8 and the internal resistance of PM 7. If the resistances of the resistors R7 and R8 are RL4, the internal resistances of the PMOS tubes PM7 and PM8 are RP. Then the high level is VDD ((RL4/2)/(RP + RL 4/2)). The value of this high level is greater than the threshold voltage of the schmitt trigger of device H, so the schmitt trigger transmits an output high level to pin IN8 of device H.

Fig. 20 is a circuit structure diagram of another signal transmission system according to an embodiment of the present application, where fig. 20 indicates a flow direction of a transmission current during high-level transmission, a dotted line indicates a current flowing direction, and a cross indicates that a current cannot flow. NM7, NM8, and PM8 are turned off, so that the transmission current cannot pass through NM7, NM7, and PM8, and therefore, the transmission current can only pass through PM7 and flow to the ground through the resistor R7 and the resistor R8, respectively. If the resistances of the resistors R7 and R8 are RL4, and the internal resistances of the PMOS transistors PM7 and PM8 are RP, the total resistance of the circuit is RP + RL4/2, and if the drain voltage is VDD, i.e. the transmission current is VDD/(RP + RL 4/2).

According to the power consumption calculation formula W (power consumption) ═ U × I × t (voltage × current × time), the new bidirectional transmission device with double pull-down lines or structure can transmit power consumption at high level, which is VDD × VDD/(RP + RL4/2) × t. Because the PMOS tube in the old bidirectional transmission device and the PMOS tube in the new bidirectional transmission device are both modules which need strong pull-up driving, the conduction internal resistances of the PMOS tubes are consistent. However, the pull-down resistor in the old input/output is used to pull down the PAD from high level to low level quickly, so that a strong pull-down driving capability is required, and the resistor in the new bidirectional transmission device is a weak pull-down module, and only a weak driving capability for stabilizing the power voltage needs to be provided. The resistance RL4 of the resistor in the new bidirectional transfer device will be much larger than the resistance RL3 of the pull-down resistor in the old bidirectional transfer device. When the old bidirectional transmission device transmits the high level, the corresponding power consumption is VDD/(RP + RL3/2) × t, and when the new bidirectional transmission device transmits the high level, the corresponding power consumption is VDD/(RP + RL4/2) × t, so that the power consumption of the new bidirectional transmission device when transmitting the high level is far less than that of the old bidirectional transmission device.

2. Transmitting low level:

similarly, "0" indicates a low level and "1" indicates a high level. The device H is used as an input port, the level of OUT8 is always low, the level of the inverter INV8 is high, the level of the delay unit of the device H is low, the level of the AND circuit AND8 is low, that is, the gate voltage of the gate of the second NMOS transistor NM8 of the device F is low, AND therefore, the NM8 is always in the off state. The gate voltage of the gate of the second PMOS transistor PM8 of the device F is high, so the PM8 is also in the off state.

When the pin OUT7 of the device G transmits a low level, the level transmitted by the pin OUT7 switches from high to low, the level of the inverter INV7 rises from low to high, and the gate voltage of the second PMOS transistor PM7 of the device G is at high, so the PM7 will be turned off. After the delay unit of the device G is delayed by T time, the level is lowered from high level to low level, AND since the two inputs of the AND gate AND7 are the output of the delay unit AND the output of the inverter INV7, the AND gate AND7 will generate a high level pulse signal with a width of T time, during which the second NMOS tube NM7 of the device G with strong pull-down capability will be turned on. Since PM7 and PM8 are closed, the current path from the power supply to PAD is closed, NM7 will pull the PAD level down to low level quickly, NM7 is closed after T time, and the second resistor R7 makes the PAD maintain the pull-down state, stabilizing the PAD level at low level. After T time, the charge on the PAD is completely released, the voltage of the PAD is always kept to be zero, and the PAD is in a discharge state in the whole process of transmitting low level and does not consume power consumption of the power supply.

Fig. 21 is a circuit structure diagram of another signal transmission system according to an embodiment of the present application, where fig. 21 illustrates a flow direction of a transmission current during low-level transmission, a dotted line indicates a current flowing direction, and a cross indicates that a current cannot flow. If the resistance values of the second resistor R7 and the second resistor R8 are both RL4, the internal resistance of the second NMOS transistor NM7 is RN. From Q (charge) ═ U/RN × (voltage/resistance) × T, T ═ RN ═ Q/U was obtained. From the equation, when Q and U are fixed, T and RN are in direct proportion. Since NM7 needs to be able to pull the PAD level down from high to low quickly, RN needs to be a small value. And NM7 has strong pull-up ability, can drop PAD to the low level fast in T time, so resistance R7 only need weak pull-down ability let PAD stabilize at zero level can, so resistance RL4 of resistance R7 will set up to great resistance value according to specific demand. In contrast to the old pull-down line or structured bidirectional transmission device, both pull down the level of PAD from high level to zero level when transmitting low level, and are in a discharge state, so that neither consumes power consumption of power source.

Namely, when the new bidirectional transmission device transmits the high-level signal, the power consumption is far less than that of the old bidirectional transmission device, and the efficiency of signal transmission is greatly improved.

Through the above description, the bidirectional transmission apparatus provided in the embodiment of the present application includes a control module and a voltage conversion module, where the control module includes a delay unit, the delay unit is configured to receive an input signal, output a signal corresponding to the input signal after a delay time elapses, and control a pull-up module or a pull-down module included in the voltage conversion module according to the output signal. The pull-up module or the pull-down module can be controlled to be switched on and off through the time sequence pulse corresponding to the control module, so that the driving capability of the pull-up module or the pull-down module which is always switched on is reduced, and the effect of reducing power consumption is achieved. Therefore, the power consumption during signal transmission can be greatly reduced, and the efficiency of signal transmission is improved.

Fig. 22 is a flowchart illustrating a control method for a bidirectional transmission apparatus according to an embodiment of the present application, including:

2201. an input signal is sent to an input of a bidirectional transmission device.

The bidirectional transmission device comprises a control module and a voltage conversion module; the first end of the control module is connected with the input end, the second end of the control module is connected with the first end of the voltage conversion module, and the second end of the voltage conversion module is connected with the output end of the bidirectional transmission device.

2202. The control module determines an input of the voltage conversion module based on the input signal.

The control module comprises a delay unit and a control gate circuit.

2203. The output of the voltage conversion module is determined according to the input of the voltage conversion module.

The voltage conversion module comprises a pull-up module and a pull-down module, and the pull-up module and the pull-down module are used for obtaining a first output signal corresponding to the input signal.

2204. And transmitting the first output signal to the output end of the bidirectional transmission device, and sending the first output signal outwards through the output end of the bidirectional transmission device.

The control module is used for obtaining a first output signal corresponding to the input signal according to the input of the voltage conversion module.

Through the above description, the bidirectional transmission apparatus provided in the embodiment of the present application includes a control module and a voltage conversion module, where the control module includes a delay unit, the delay unit is configured to receive an input signal, output a signal corresponding to the input signal after a delay time elapses, and control a pull-up module or a pull-down module included in the voltage conversion module according to the output signal. Meanwhile, the pull-up module or the pull-down module comprises controllable sub-modules, so that power consumption can be reduced, the output end is rapidly changed to a high level or a low level, and transmission is conducted to the outside. Therefore, the power consumption during signal transmission can be greatly reduced, and the efficiency of signal transmission is improved.

The embodiment of the present application further provides a bidirectional transmission system, which includes a plurality of bidirectional transmission devices, selectors, and data processing units as in any one of the embodiments shown in fig. 1 to 21.

The bidirectional transmission device is used for receiving or sending transmission signals.

The selector is used for selecting a transmission path for the transmission signal according to the transmission signal.

The data processing unit is used for processing the data. And a transmission path for determining a target bidirectional transmission device. And the target bidirectional transmission device sends the transmission signal.

The embodiment of the present application further provides a computer-readable storage medium, which includes a control method of a bidirectional transmission apparatus in the embodiment shown in any one of fig. 1 to 21.

The embodiment of the present application further provides a computer product, including a control method of a bidirectional transmission apparatus in the embodiment shown in any one of fig. 1 to 21.

Technical terms used in the embodiments of the present invention are only used for illustrating specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the use of "including" and/or "comprising" in the specification is intended to specify the presence of stated features, integers, steps, operations, elements, and/or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components.

With following

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed.

Claims

1. A bidirectional transmission apparatus, comprising: the device comprises a control module and a voltage conversion module;

the control module comprises a delay unit and a control gate circuit; the control module is used for generating a pulse signal with a certain time sequence according to an input signal, and the pulse signal is used for controlling the input of the voltage conversion module;

the voltage conversion module comprises a pull-up module and a pull-down module, and is used for obtaining a first output signal corresponding to the input signal according to the input of the voltage conversion module;

the bidirectional transmission device also comprises an output driving module;

the input end of the output driving module is connected with the input end of the bidirectional transmission device; the output end of the output driving module is connected with the input end of the pull-down module;

the output driving module is used for obtaining a second output signal opposite to the input signal according to the input signal;

the pull-up module comprises a strong pull-up sub-module and a weak pull-up sub-module; the control gate circuit comprises an OR gate circuit;

the first input end of the OR gate circuit is connected with the output end of the delay unit, the second input end of the OR gate circuit is connected with the output end of the output driving module, and the output end of the OR gate circuit is connected with the input end of the strong pull-up sub-module; and the output end of the output driving module is connected with the input end of the pull-down module.

2. The bi-directional transmission device of claim 1, wherein the output driver module comprises an inverter.

3. The bidirectional transmitting device of claim 1, wherein the strong pull-up sub-module comprises a first PMOS transistor, the weak pull-up sub-module comprises a first resistor, and the pull-down module comprises a first NMOS transistor;

the grid electrode of the first NMOS tube is connected with the output end of the output driving module; and the source electrode of the first NMOS tube is grounded.

4. A bidirectional transmission apparatus, comprising: the device comprises a control module and a voltage conversion module;

the bidirectional transmission device also comprises an output driving module;

the input end of the output driving module is connected with the input end of the bidirectional transmission device; the output end of the output driving module is connected with the input end of the pull-up module;

the pull-down module comprises a strong pull-down submodule and a weak pull-down submodule; the control gate circuit comprises an AND gate circuit;

the first input end of the AND-gate circuit is connected with the output end of the delay unit, the second input end of the AND-gate circuit is connected with the output end of the output driving module, and the output end of the AND-gate circuit is connected with the input end of the strong pull-down submodule; and the output end of the output driving module is connected with the input end of the pull-up module.

5. The bi-directional transmission device of claim 4, wherein the pull-up module comprises a second PMOS transistor and the strong pull-down sub-module comprises a second NMOS transistor; the weak pull-down submodule comprises a second resistor;

the grid electrode of the second PMOS tube is connected with the output end of the output driving module; and the drain electrode of the second PMOS tube is connected with a power supply.

6. A control method of a bidirectional transmission apparatus, the control method comprising:

sending an input signal to an input terminal of a bidirectional transmission device; the bidirectional transmission device comprises a control module, an output driving module and a voltage conversion module; the first end of the control module is connected with the input end, the second end of the control module is connected with the first end of the voltage conversion module, and the second end of the voltage conversion module is connected with the output end of the bidirectional transmission device; the input end of the output driving module is connected with the input end of the bidirectional transmission device;

determining the output of the voltage conversion module according to the input of the voltage conversion module; the voltage conversion module comprises a pull-up module and a pull-down module, the pull-up module and the pull-down module are used for obtaining a first output signal corresponding to the input signal, and the pull-up module comprises a strong pull-up sub-module and a weak pull-up sub-module; the control gate circuit comprises an OR gate circuit, a first input end of the OR gate circuit is connected with the output end of the delay unit, a second input end of the OR gate circuit is connected with the output end of the output driving module, and an output end of the OR gate circuit is connected with the input end of the strong pull-up sub-module; the output end of the output driving module is connected with the input end of the pull-down module;

according to the input signal, the output driving module obtains a second output signal opposite to the input signal;

and transmitting the first output signal to an output end of the bidirectional transmission device, and sending the first output signal outwards through the output end of the bidirectional transmission device.

7. The control method according to claim 6,

8. A control method of a bidirectional transmission apparatus, the control method comprising:

determining the output of the voltage conversion module according to the input of the voltage conversion module; the voltage conversion module comprises a pull-up module and a pull-down module, the pull-up module and the pull-down module are used for obtaining a first output signal corresponding to the input signal, and the pull-down module comprises a strong pull-down submodule and a weak pull-down submodule; the control gate circuit comprises an AND gate circuit, a first input end of the AND gate circuit is connected with an output end of the delay unit, a second input end of the AND gate circuit is connected with an output end of the output driving module, and an output end of the AND gate circuit is connected with an input end of the strong pull-down submodule; the output end of the output driving module is connected with the input end of the pull-up module;

9. A bidirectional transmission system, characterized in that it comprises a plurality of bidirectional transmission devices according to any one of claims 1 to 5, a selector and a data processing unit;

the bidirectional transmission device is used for receiving or sending a transmission signal;

and the data processing unit is used for determining a target bidirectional transmission device according to the transmission path and sending the transmission signal to the target bidirectional transmission device.