CN113615088B - Clock domain crossing synchronization circuit and method - Google Patents
Clock domain crossing synchronization circuit and method Download PDFInfo
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- CN113615088B CN113615088B CN201980094534.6A CN201980094534A CN113615088B CN 113615088 B CN113615088 B CN 113615088B CN 201980094534 A CN201980094534 A CN 201980094534A CN 113615088 B CN113615088 B CN 113615088B
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Abstract
The embodiment of the application discloses a clock domain crossing synchronization circuit, which comprises a clock domain channel circuit, a write address generating circuit, a read address generating circuit and a data buffer circuit, wherein the write address generating circuit is used for obtaining a write address according to a write enabling signal, the write address is used for controlling the data buffer circuit to receive input data, and the input data is in a write clock domain; the clock domain channel circuit is used for sampling the write enabling signal to obtain a plurality of sampling results, and selecting one sampling result from the plurality of sampling results as a read enabling signal according to a clock phase difference, wherein the clock phase difference is a phase difference between a write clock signal in a write clock domain and a read clock signal in a read clock domain; the read address generation circuit is used for obtaining a read address according to the read enabling signal, and the read address is used for controlling the data buffer circuit to generate output data which is in a read clock domain; the data buffer circuit is used for buffering input data and generating output data according to the write address and the read address.
Description
Technical Field
The present disclosure relates to the field of circuits, and more particularly, to a clock domain crossing synchronization circuit and a method thereof.
Background
System-on-chip (SOC) refers to a system-on-chip (SOC) integrated with a complete system on a single chip, and as the functions carried on the chip are increased, there are more and more clocks in the chip, and each clock has a different working frequency, so that there are multiple clock domains in the chip, when the multiple clock domains communicate with each other, synchronization of the clock domains is required to complete data interaction across the clock domains, and asynchronous circuit processing technology can complete the process.
One typical asynchronous circuit processing technique is the asynchronous first-in-first-out (FIFO) technique, referring to fig. 1, first the write address generation logic 101 in the write clock domain generates a binary write pointer to write data into the FIFO memory 104, and the read address generation logic 103 in the read clock domain generates a binary read pointer to read data from the FIFO memory 104, with each read or write operation the corresponding pointer being incremented to the next memory address. When the full/empty flag generation logic circuit 102 generates the read empty flag, the read operation is no longer performed, but the write operation may be performed, and when the full/empty flag generation logic circuit 102 generates the write full flag, the write operation is no longer performed, but the read operation may be performed. The generation of the read empty mark needs to synchronize the write pointer of the write clock domain to the read clock domain, firstly, in order to avoid the occurrence of burrs, the binary write pointer needs to be converted into Gray code, then the Gray code is processed by two stages of registers, or is processed by multiple stages of registers, then the write pointer obtained by processing is converted into binary, and compared with the binary read pointer, when the address bits of the two pointers are identical, the read empty signal is generated when the status bits are also identical, in the process, because the register registers need to ensure the setup time and the holding time of the data, the setup time refers to the time of inputting the data in advance before the rising edge of the clock signal, the holding time needs to be kept unchanged when the data is required to be kept unchanged after the rising edge arrives, the processing of one beat by the registers needs to be equal to one clock cycle, then the processing of two beats is executed by the registers, or the processing of two or the delay of two or more clock cycles is correspondingly generated when the processing of two beats by multiple registers is executed, the write pointer needs to be synchronized to the delay of at least two clock cycles by the write clock domain. Similarly, the generation of the full mark requires synchronizing the read pointer of the read clock domain to the write clock domain, and the synchronization process requires the register to perform a two-beat or multi-beat process, with a delay of at least two clock cycles.
It can be seen that synchronizing the write pointer of the write clock domain to the read clock domain to obtain a read empty signal will generate a delay of at least two clock cycles, and synchronizing the read pointer of the same read clock domain to the write clock domain to obtain a write full signal will also generate a delay of at least two clock cycles. The full mark controls the increase of the write pointer, the empty mark controls the increase of the read pointer, the read pointer controls the writing and reading of the data, thereby controlling the data of the write clock domain to be synchronized to the read clock domain, and therefore, the synchronization of the data between the two clock domains has at least two clock cycle delay. Because of the above factors, an asynchronous FIFO as shown in fig. 1 has a large delay in performing the cross-clock domain processing, and thus the efficiency of the data cross-clock domain processing is reduced.
Disclosure of Invention
A first aspect of the present application provides a clock domain crossing synchronization circuit that can synchronize input data from a write clock domain to a read clock domain, the clock domain crossing synchronization circuit including a clock domain channel circuit, a write address generation circuit, a read address generation circuit, and a data buffer circuit; the write address generating circuit can obtain a write address according to the write enable signal under the drive of the write clock signal, and the write address can control the data buffer circuit to receive input data, wherein the input data is the data of a write clock domain; the two input ends of the clock domain channel circuit respectively input a write-enabling signal and a clock phase difference, wherein the clock phase difference refers to the phase difference between a write clock signal in a write clock domain and a read clock signal in a read clock domain, the clock domain channel circuit can sample the write-enabling signal to obtain a sampling signal set, and the clock domain channel circuit selects a sampling signal from the sampling signal set to serve as a read-enabling signal according to the clock phase difference; the read address generating circuit can obtain a read address according to the read enabling signal under the drive of the read clock signal, the read address can control the data buffer circuit to generate output data, the output data is in the read clock domain, and then the clock domain crossing synchronizing circuit completes the process of synchronizing the input data from the write clock domain to the read clock domain. The data buffer circuit receives input data according to the write address and then buffers the input data, and then the data buffer circuit generates output data according to the read address.
The embodiment of the application has the following advantages: the write address generating circuit obtains a write address according to the write enabling signal, the write address is used for controlling the data caching circuit to receive data, and the data caching circuit caches the input data after receiving the input data, so that the process of writing the data into the data caching circuit is completed. The clock domain channel circuit may sample the write enable signal to obtain a plurality of sampling results, and delay of some or all sampling results in the plurality of sampling results relative to the write enable signal is within two clock cycles, and secondly, a clock phase difference exists between the write clock signal of the write clock domain and the read clock signal of the read clock domain, according to the clock phase difference, one read enable signal is selected from the plurality of sampling results, and the delay of the selected read enable signal and the selected write enable signal may be controlled within two clock cycles. The read address generation circuit can obtain a read address according to the read enabling signal, and the read address is used for controlling the data buffer circuit to generate output data so as to finish the data reading process, and then the delay of the read enabling signal and the write enabling signal is controlled in two clock cycles, so that the synchronization of the data between two clock domains is also in the two clock cycles, and compared with the scheme that the synchronization of the data between the two clock domains has the delay of at least two clock cycles, the data synchronization delay can be controlled in the two clock cycles, the data synchronization delay is reduced, and the data cross-clock domain processing efficiency is further improved.
In an optional embodiment of the present application, the clock domain channel circuit specifically includes a plurality of flip-flops, where the plurality of flip-flops sample the write enable signal at a rising edge and a falling edge of the read clock signal to obtain a sampling signal set, the sampling signal set includes at least one sampling signal, and the clock domain channel circuit further includes a multi-channel signal selector, where the multi-channel signal selector may select, according to a clock phase difference, a target mapping relationship from a preset mapping relationship between the clock phase difference and the write enable signal, and then determine, according to the target mapping relationship, the sampling signal from the sampling signal set, and use the determined sampling signal as the read enable signal. In this embodiment, the plurality of trigger groups may sample to obtain a sampling signal set, and meanwhile, a mapping relationship between a clock phase difference and a read enable signal is preset, so that the read enable signal determined by the change of the clock phase difference also changes, and therefore, a corresponding sampling signal may be selected from the sampling signal set as the read enable signal under the condition of different clock phase differences, so that clock delays of the obtained read enable signal and the obtained write enable signal may be controlled in two clock cycles, and clock delays of the obtained read enable signal and the obtained write enable signal may also ensure enough time to synchronize input data from a write clock domain to a read clock domain.
In an alternative embodiment of the present application, the cross-clock domain synchronization circuit further comprises a phase detector; the phase discriminator can determine the clock phase difference of the received write clock signal and the received read clock signal according to the two clock phase differences; the phase discriminator can also generate a write enable signal according to the write clock signal, and the write enable signal is only valid when the clock phase difference is in a stable state, otherwise, the write enable signal is invalid. The phase detector outputs a clock phase difference and a write enable signal to the clock domain channel circuit. In this embodiment, the phase detector may generate the clock phase difference and the write enable signal, which is more complete in structure and beneficial to implementation of the scheme.
In an alternative embodiment of the present application, the clock domain channel circuit includes a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; the first trigger is used for sampling the write enable signal to obtain a first sampling signal at the falling edge of the read clock signal after receiving the write enable signal generated by the phase discriminator, and the second trigger is used for sampling the first sampling signal at the rising edge of the read clock signal to obtain a second sampling signal; the third trigger is used for sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal after receiving the write enable signal generated by the phase discriminator; the fourth trigger can sample the third sampling signal at the rising edge of the read clock signal to obtain a fourth sampling signal, wherein the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal all belong to a sampling signal set. Compared with the prior art that a register is used for synchronizing a write pointer or a read pointer, the register needs to ensure the establishment time and the holding time of data, and then needs to wait for at least two clock cycles, in the embodiment, a trigger is used for sampling a write enable signal to obtain a sampling signal set, the sampling signal in the sampling signal set can be used as a read enable signal, and since the trigger can sample the signal at both rising edges and falling edges of the clock signal, the write enable signal can be controlled to obtain the read enable signal in two clock cycles, and the corresponding data can be controlled to be synchronized to a read clock domain from a write clock domain or in two clock cycles, so that the delay of data synchronization is reduced relative to the prior art.
In an optional embodiment of the present application, the clock domain channel circuit further includes a multiplexer, and two input terminals of the multiplexer respectively input the sampling signal set and the clock phase difference, and output the read enable signal. A multi-path signal selector, configured to select a second sampling signal from the sampling signal set as a read enable signal when the value range of the clock phase difference is [0T,1/4T ], where T is a clock cycle of the write clock domain or a clock cycle of the read clock domain, because the clock cycle of the write clock may be the same as the clock of the read clock domain; or, a multi-path signal selector for selecting the second sampling signal or the fourth sampling signal from the sampling signal set as the read enable signal when the clock phase difference is [1/4T,1/2T ], wherein the clock period of the second sampling signal and the clock period of the fourth sampling signal delayed relative to the write enable signal are the same, and the second sampling signal or the fourth sampling signal may be selected; or, a multi-path signal selector for selecting a fourth sampling signal from the sampling signal set as a read enable signal when the clock phase difference is [1/2T, 3/4T); or, the multi-path signal selector is configured to select the second sampling signal or the third sampling signal from the sampling signal set as the read enable signal when the value of the clock phase difference is greater than or equal to 3/4 of the clock period T, where the clock periods of the second sampling signal and the third sampling signal delayed with respect to the write enable signal are the same, and either the second sampling signal or the third sampling signal may be selected. In this embodiment, a specific manner of selecting a read enable signal under four clock phase difference conditions is described, which covers all possible clock phase difference conditions, and the method is flexibly implemented by using a scheme, so that clock delays of the selected read enable signal and the selected write enable signal can be controlled to be two clock cycles, and at the same time, the clock delays of the selected read enable signal and the selected write enable signal can also ensure enough time to synchronize input data from a write clock domain to a read clock domain.
In an optional embodiment of the present application, the clock domain crossing synchronization circuit further includes a write clock domain phase locked loop and a read clock domain phase locked loop, where the write clock domain phase locked loop and the read clock domain phase locked loop are connected to a same clock source; the write clock domain phase-locked loop can obtain a write clock signal according to a clock source signal, wherein the write clock signal is in a write clock domain; the read clock domain phase-locked loop can obtain a read clock signal according to the clock source signal, wherein the read clock signal is in the read clock domain. In this embodiment, the write clock domain phase-locked loop and the read clock domain phase-locked loop are connected to the same clock source, so as to ensure that the clocks in the write clock domain and the read clock domain are homologous clocks, and ensure that the two clocks have no frequency offset, so that the frequencies of the obtained write clock signal and the obtained read clock signal are equal or the frequency division ratio of the obtained write clock signal and the obtained read clock signal is an integer multiple, and meanwhile, the phase difference between the two clock signals is random.
In an alternative embodiment of the present application, the data buffer circuit includes a plurality of flip-flop groups, an input multi-way data selector, and an output multi-way data selector; the input data selector comprises a plurality of output ports which are connected with a plurality of input ends of a plurality of trigger groups in a one-to-one correspondence manner, and the output multipath data selector comprises a plurality of input ports which are connected with a plurality of output ends of a plurality of trigger groups in a one-to-one correspondence manner; the input multi-path data selector is used for outputting the cache data from a certain output port according to the write address after acquiring the input data, and the multi-path cache data can be obtained from a plurality of output ports of the input multi-path data selector by continuously changing the write address; the plurality of trigger groups are used for receiving the multi-path cache data under the drive of the write clock signal, and respectively caching the multi-path cache data output from the output ports of the plurality of input multi-path data selectors in different trigger groups; and the output multi-path data selector is used for receiving multi-path cache data output by the plurality of trigger groups, selecting one path of cache data from the multi-path cache data to be output as output data according to read addresses, wherein the read addresses are different, and the selected output data are different. In this embodiment, since the read enable signal changes along with the clock phase difference, the read enable signal can obtain the read address, so that under different clock phase differences, the read address is different, and the read address is used as the read address carrying address information, so that the read address has multiple possible situations. The clock phase difference is changed, the read address is changed, and the selected output data is also changed, so that the scheme can meet the requirement of data synchronization under different clock phase difference conditions.
In an alternative embodiment of the present application, the cross-clock domain synchronization circuit further includes a fifth D flip-flop; and the fifth D trigger is used for receiving and outputting the output data selected by the multi-path data selector under the drive of the read clock signal, and caching and outputting the output data. In this embodiment, the output data selected by the output multi-way data selector is buffered and output by using the fifth D flip-flop, which can prevent the influence of external interference on the accuracy of data transmission in the data transmission process.
A second aspect of the present application provides a method for synchronizing clock domains, the method comprising: obtaining a write address according to a write enabling signal, wherein the write address carries address information, receiving input data according to control of the write address, and caching the input data, so that a data writing process is completed, wherein the input data is in a write clock domain, simultaneously, the write enabling signal can be sampled to obtain a plurality of sampling results, and one sampling result is selected from the plurality of sampling results to serve as a read enabling signal according to a clock phase difference, wherein the clock phase difference is a phase difference between a write clock signal in the write clock domain and a read clock signal in the read clock domain; and obtaining a read address according to the read enable signal, and outputting the cached input data according to the control of the read address so as to generate output data, so that the data reading process is completed, and the output data is in a read clock domain.
This embodiment has the following advantages: the write address is obtained according to the write enable signal, and the input data can be received and cached according to the control of the write address, so that the writing process of the data is completed. And secondly, a clock phase difference exists between a write clock signal of the write clock domain and a read clock signal of the read clock domain, one read enable signal is selected from the plurality of sampling results according to the clock phase difference, and the delay of the read enable signal and the write enable signal obtained by selection can be controlled within two clock cycles. And then obtaining a read address according to the read enable signal, outputting the buffered input data according to the control of the read address to generate output data, and completing the data reading process, wherein the delay of the read enable signal and the write enable signal is controlled in two clock cycles, and the synchronization of the data between the two clock domains is also in the two clock cycles.
In an alternative embodiment of the present application, the sampling the write enable signal to obtain a plurality of sampling results includes: the write enable signal is sampled at the rising edge of the read clock signal, and at the same time, the write enable signal is sampled at the falling edge of the read clock signal, so that a plurality of sampling results can be obtained. In this embodiment, compared with the prior art that uses a register to synchronize a write pointer or a read pointer, the register needs to ensure the setup time and the hold time of data, and then needs to wait for at least two clock cycles.
In an alternative embodiment of the present application, sampling the write enable signal at a rising edge and a falling edge of the read clock signal respectively to obtain a plurality of sampling results specifically includes: sampling the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal; sampling the first sampling signal at the rising edge of the read clock signal to obtain a second sampling signal; sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal; the third sampling signal is sampled at the rising edge of the read clock signal, so as to obtain a fourth sampling signal, and the plurality of sampling results are specifically the obtained first sampling signal, second sampling signal, third sampling signal and fourth sampling signal. In this embodiment, compared with the prior art that uses a register to synchronize a write pointer or a read pointer, the register needs to ensure the setup time and the hold time of data, and then needs to wait for at least two clock cycles.
In an alternative embodiment of the present application, selecting one sampling result from a plurality of sampling results as the read enable signal according to the clock phase difference includes: under the condition that the value range of the clock phase difference is [0T, 1/4T), selecting a second sampling signal from a plurality of sampling results as a reading enabling signal, wherein the clock signal of the writing clock domain and the clock signal of the reading clock domain are generated by the same clock source, the clock period of the writing clock domain or the clock period of the reading clock domain are the same, and T can be the clock period of the writing clock domain or the clock period of the reading clock domain; or, under the condition that the value range of the clock phase difference is 1/4T, 1/2T), selecting a second sampling signal or a fourth sampling signal from a plurality of sampling results as a reading enabling signal; or, under the condition that the value range of the clock phase difference is 1/2T, 3/4T), selecting a fourth sampling signal from a plurality of sampling results as a reading enabling signal; or, in the case where the value of the clock phase difference is greater than or equal to 3/4 clock period T, selecting the second sampling signal or the third sampling signal from the plurality of sampling results as the read enable signal. In this embodiment, a specific manner of selecting a read enable signal under four clock phase difference conditions is described, which covers all possible clock phase difference conditions, and the method is flexibly implemented by using a scheme, so that clock delays of the selected read enable signal and the selected write enable signal can be controlled to be two clock cycles, and at the same time, the clock delays of the selected read enable signal and the selected write enable signal can also ensure enough time to synchronize input data from a write clock domain to a read clock domain.
In an alternative embodiment of the present application, the method further comprises: determining a clock phase difference between the write clock signal and the read clock signal of the read clock domain according to the write clock signal; and generating a write enable signal according to the write clock signal, wherein the write enable signal is valid when the clock phase difference between the write clock signal and the read clock signal is in a stable state, and the write enable signal is invalid when the clock phase difference between the write clock signal and the read clock signal is not in a stable state. In this embodiment, a clock phase difference and an acquisition manner of a write enable signal may be introduced, where the write enable signal may be used in the data synchronization process of the present application, and the write enable signal is valid only when the clock phase difference is stable, so that an error in data synchronization when the clock phase difference is unstable may be avoided.
A third aspect of the present application provides a chip comprising the clock domain crossing synchronization circuit of the first aspect of the present application and any implementation of the same.
The embodiment of the application has the following advantages: the write address generating circuit obtains a write address according to the write enabling signal, the write address is used for controlling the data caching circuit to receive data, and the data caching circuit caches the input data after receiving the input data, so that the process of writing the data into the data caching circuit is completed. The clock domain channel circuit may sample the write enable signal to obtain a plurality of sampling results, and delay of some or all sampling results in the plurality of sampling results relative to the write enable signal is within two clock cycles, and secondly, a clock phase difference exists between the write clock signal of the write clock domain and the read clock signal of the read clock domain, according to the clock phase difference, one read enable signal is selected from the plurality of sampling results, and the delay of the selected read enable signal and the selected write enable signal may be controlled within two clock cycles. The read address generation circuit can obtain a read address according to the read enabling signal, and the read address is used for controlling the data buffer circuit to generate output data so as to finish the data reading process, and then the delay of the read enabling signal and the write enabling signal is controlled in two clock cycles, so that the synchronization of the data between two clock domains is also in the two clock cycles, and compared with the scheme that the synchronization of the data between the two clock domains has the delay of at least two clock cycles, the data synchronization delay can be controlled in the two clock cycles, the data synchronization delay is reduced, and the data cross-clock domain processing efficiency is further improved.
Drawings
FIG. 1 is a block diagram of a prior art asynchronous FIFO;
FIG. 2 is a block diagram of a cross-clock domain synchronization circuit of the present application;
FIG. 3 is a block diagram of a clock domain channel circuit of the present application;
FIG. 4 (a) is a phase relationship of the read/write clock domain of the present application;
FIG. 4 (b) is another phase relationship of the read/write clock domain of the present application;
FIG. 4 (c) is another phase relationship of the read/write clock domain of the present application;
FIG. 4 (d) is another phase relationship of the read/write clock domain of the present application;
FIG. 5 (a) is a signal sampling result of the present application;
FIG. 5 (b) is another signal sampling result of the present application;
FIG. 5 (c) is another signal sampling result of the present application;
fig. 5 (d) shows another signal sampling result of the present application.
Detailed Description
The present application provides a clock domain crossing synchronization circuit, which may be applied to field-programmable gate arrays (field-programmable gate array, FPGA), application specific integrated circuit (application specific integrated circuits, ASIC) chips, and other devices, but is not limited thereto.
Referring to fig. 2, the clock domain crossing synchronization circuit of the present application includes a write address generation circuit 01, a read address generation circuit 02, and a data buffer circuit, wherein the data buffer circuit includes a plurality of flip-flop groups 05, an input multi-way data selector 06 (MUX), and an output multi-way data selector 07, and further includes a fifth D flip-flop 08, a phase detector 03, a clock domain channel circuit 04, a write clock domain phase-locked loop 09 (phase locked loop, PLL), and a read clock domain phase-locked loop 010.
Firstly, the write clock domain phase-locked loop 09 can generate a write clock signal of the write clock domain, the read clock domain phase-locked loop 010 can generate a read clock signal of the read clock domain, the input end of the write clock domain phase-locked loop 09 and the input end of the read clock domain phase-locked loop 010 are connected with the same clock source so as to ensure that the clocks of the write clock domain and the read clock domain are homologous clocks, and the purpose of the write clock domain phase-locked loop 09 is to ensure that the clocks of the write clock domain and the read clock domain are not offset, generate the write clock signal and the read clock signal with the same frequency, or generate the write clock signal and the read clock signal with the frequency division ratio of integer multiples, and meanwhile, the clock phase difference between the write clock signal and the read clock signal is random.
Write address generation circuit 01: the write pointer may be continuously generated when the write enable signal is asserted, which may be generated by the phase detector 03, as a write address, driven by a write clock signal of the write clock domain. One input port of the write address generating circuit 01 is connected to the output port of the write clock domain phase lock loop 09, and can receive a write clock signal, the other input port of the write address generating circuit 01 is connected to the first output port of the phase detector 03, and can receive a write enable signal, and the output port of the write address generating circuit 01 is connected to the input port of the input multiplexer 06, and can output a write address.
The data buffer circuit includes an input multi-way data selector 06, a plurality of trigger groups 05 and an output multi-way data selector 07, and the data buffer circuit can receive input data according to a write address, then buffer the input data, and the data buffer circuit can also generate output data according to a read address, and the specific process is as follows:
after the write address is input to the input multi-way data selector 06 and the input multi-way data selector 06 obtains the input data, the buffered data may be output from a certain output port of the input multi-way data selector 06 according to the address information indicated by the write address, so that the buffered data is written into a certain trigger group of the plurality of trigger groups 05, the address information indicated by the write address may indicate that the buffered data is written into a specific trigger group of the plurality of trigger groups 05, and the certain trigger group corresponds to a certain output port. The address information indicated by the write address is variable, and then the input multi-way data selector 06 may output the buffered data from the plurality of ports of the input multi-way data selector 06, respectively, according to the indication of the write address, and the buffered data output from the plurality of ports respectively enter the plurality of trigger groups 05. The two data terminals of the input multi-way data selector 06 respectively receive input data and write addresses generated by the write address generating circuit 01, a plurality of input ports of the plurality of trigger groups 05 are connected with a plurality of output ports of the input data multi-way selector 06 in a one-to-one correspondence manner, can receive cache data, and a plurality of output ports of the plurality of trigger groups 05 are connected with a plurality of input ports of the output multi-way data selector 07 in a one-to-one correspondence manner, and can output the cache data.
Further, regarding the plurality of flip-flop groups 05, for example, 4D flip-flop groups are taken as an example in fig. 2, the number of D flip-flops in each of the plurality of D flip-flop groups is determined by the bit width of the input data, the trigger input ports of the four D flip-flop groups are connected to the write clock signal, and the four cache data processed by the input multi-way data selector 06 are respectively input to the four D flip-flop groups under the driving of the write clock signal.
The plurality of trigger groups 05 buffer the multi-path buffer data, and then output the multi-path buffer data to the output multi-path data selector 07, the output multi-path data selector 07 can select one path of buffer data from the multi-path buffer data as output data to output according to the indication of the read pointer, the specific read pointer can be used as a read address, the read address carries address information, the address information indicated by the read address can indicate the output multi-path data selector 07 to output the buffer data obtained from the specific D trigger groups of the plurality of trigger groups 05, the read address is different, and the output multi-path data selector 07 selects the output buffer data is different. One input port of the output multiplexer 07 is connected to the output ports of the plurality of flip-flop groups 05, and can receive the buffered data, and the other input port of the output multiplexer 07 is connected to the output port of the read address generating circuit 02, and can receive the read address.
The output data generated by the output multi-way data selector 07 is input to the fifth D flip-flop 08, and the fifth D flip-flop 08 can buffer and output the output data generated by the data buffer circuit under the driving of the read clock signal, and the fifth D flip-flop 08 can prevent the influence of external interference on the correctness of data transmission in the data transmission process.
The phase detector 03 (PD) can calculate a clock phase difference between a write clock signal of the write clock domain and a read clock signal of the read clock domain, and when the write clock domain and the read clock domain are stable, the phase detector 03 enters a working state, and after a plurality of clock cycles, the phase detector 03 generates a stable clock phase difference and outputs the stable clock phase difference to the clock domain channel circuit 04. Meanwhile, the phase detector 03 can also process the write clock signal of the write clock domain to obtain a write enable signal, and output the write enable signal to the write address generating circuit 01 and the clock domain channel circuit 04, wherein the write enable signal is used as a state indication of the stable output clock phase difference of the phase detector 03, and when the clock phase difference is in a stable state, the write enable signal is valid, otherwise, the write enable signal is invalid. One input terminal of the phase detector 03 is connected to the write clock domain phase locked loop 09 to receive the write clock signal, the other input terminal of the phase detector 03 is connected to the read-while-write clock domain phase locked loop 010 to receive the read clock signal, the first output port of the phase detector 03 is connected to the other input port of the write address generating circuit 01 and the first input port of the clock domain channel circuit 04, and can output the write enable signal, and the second output port of the phase detector 03 is connected to the second input port of the clock domain channel circuit 04, and can output the clock phase difference.
Clock domain channel circuit 04 circuit: the clock domain channel circuit 04 may synchronize write enable from the write clock domain to the read clock domain according to four states of the clock phase difference, to obtain a read enable signal, and then the read enable signal is output to the read address generating circuit 02, and the read address generating circuit 02 may continuously generate a read pointer as a read address to be output to the multiplexer data selector 07 when the read enable signal is valid under the driving of the read clock signal of the read clock domain. An output port of the clock domain channel circuit 04 is connected to one input port of the read address generation circuit 02, and can output a read enable signal, and the other input port of the read address generation circuit 02 is connected to an output port of the read clock domain phase locked loop 010, and can receive a read clock signal, and the output port of the read address generation circuit 02 is connected to the other input port of the output multiplexer 07, and can output a read address.
Based on the above configuration, the write address generating circuit 01 generates a write address to write data into the data buffer circuit, the clock domain channel circuit 04 can obtain a read enable signal according to the write enable signal and the clock phase difference, thereby synchronizing the write enable signal from the write clock domain to the read clock domain, the read address generating circuit 02 obtains a read address according to the read enable signal, and reads data from the data buffer circuit, thereby realizing the synchronization of the input data from the write clock domain to the read clock domain.
Meanwhile, since the read enable signal changes along with the clock phase difference, the read enable signal can obtain the read pointer, so that under different clock phase difference conditions, the read pointer is also different, the read address changes, and the output data selected by the output multi-way data selector 07 also changes, therefore, the scheme of the application sets four-way cache data to meet the requirement of data synchronization under different clock phase difference conditions.
Based on the functions of the clock domain channel circuit 04 described above, the following specifically describes the generation process of the read address:
fig. 3 is a specific structure of the clock domain channel circuit 04 in the present application, where the clock domain channel circuit 04 includes a first flip-flop 041, a second flip-flop 042, a third flip-flop 043, a fourth flip-flop 044, and a multiplexer 045, a first output port of the phase detector 03 is specifically connected to an input port of the first flip-flop 041, an output port of the first flip-flop 041 is connected to an input port of the second flip-flop 042, a first output port of the phase detector 03 is specifically further connected to an input port of the third flip-flop 043, an output port of the third flip-flop 043 is connected to an input port of the fourth flip-flop 044, the output port of the first trigger 041, the output port of the second trigger 042, the output port of the third trigger 043, and the output port of the fourth trigger 044 are connected to another input port of the multiplexer, the output port of the multiplexer 045 is connected to the input port of the read address generating circuit 02, referring to fig. 3, taking the case that the write clock domain and the read clock domain are homologous synchronous clocks with the same frequency, the frequencies between the write clock signal and the read clock signal are the same, the clock phase difference is random, the specific process of synchronizing the write enable signal from the write clock domain to the read clock domain by the clock domain channel circuit 04 in this application is:
As described above, the phase detector 03 generates the write enable signal, which enters the write address generation circuit 01, and also enters the clock domain channel circuit 04, specifically:
the write enable signal enters a first trigger 041, a read clock signal is used as a sampling pulse, the first trigger 041 samples the write enable signal on the falling edge of the read clock signal to obtain a first sampling signal, then the first sampling signal enters a second trigger 042, the same read clock signal is used as a sampling pulse, the first sampling signal is sampled on the rising edge of the read clock signal to obtain a second sampling signal, the write enable signal of the write clock domain also enters a third trigger 043, the read clock signal is used as a sampling pulse, the third trigger 043 samples the write enable signal on the falling edge of the read clock signal to obtain a third sampling signal, then the third sampling signal enters a fourth trigger 044, the same read clock signal is used as a sampling pulse, and the third sampling signal is sampled on the rising edge of the read clock signal to obtain a fourth sampling signal. The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal belong to a sampling signal set, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are respectively output to a multi-channel signal selector 045, a clock phase difference obtained by phase discrimination of the phase discriminator 03 is also input to the multi-channel signal selector 045, and the multi-channel signal selector 045 selects one channel of sampling signals as a write enabling signal to be output to the read address generating circuit 02 according to the clock phase difference obtained by phase discrimination of the phase discriminator 03, so that a read address can be generated.
Compared with the prior art that the write pointer synchronization or the read pointer synchronization is performed by using the register, the register needs to ensure the setup time and the hold time of data, and then needs to wait for at least two clock cycles, in the embodiment, the trigger is used for sampling the write enable signal to obtain a sampling signal set, the sampling signal in the sampling signal set can be used as the read enable signal, and because the trigger can sample the signal at both the rising edge and the falling edge of the clock signal, all or part of the sampling signal in the sampling signal set obtained by the write enable signal can be controlled within two clock cycles, and the corresponding data can be controlled within two clock cycles from the synchronization of the write clock domain to the read clock domain, so that the delay of data synchronization is reduced compared with the prior art.
The clock phase difference of the phase detector 03 has four possible cases, and the read enable signal obtained by selection has four possible cases, and the general idea of selection is to ensure that the write enable signal does not have metastable states, and the four cases are described below:
first the clock phase difference refers to the phase difference between the write clock signal of the write clock domain and the read clock signal of the read clock domain. The application presets the mapping relation between clock phase differences and reading enabling signals, the clock phase differences are different, the reading enabling signals are different, and the application is specific:
1. The phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the clock phase difference is [0T, 1/4T), T is the clock period of the write clock domain, as shown in fig. 4 (a), taking the clock phase difference between the write clock signal and the read clock signal as an example, corresponding to the clock phase difference of fig. 4 (a), as shown in fig. 5 (a), the write enable signal is sampled by the read clock signal in the manner described above, the third sampling signal obtained by sampling may have a metastable state, the fourth sampling signal may also have a metastable state, but the first sampling signal and the second sampling signal may not have a metastable state, in order to ensure a certain data synchronization delay, thereby ensuring that there is enough time to read data, but the data synchronization delay is not too large, generally within 2 clock periods, the multiplexer 045 selects the second sampling signal as the read enable signal and generates the read address, and the data synchronization delay from the read clock domain to the write clock domain is about 1.25 clock periods later than the read address.
2. The phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the clock phase difference between the write clock domain and the read clock domain belongs to [1/4T, 1/2T), T is the clock cycle of the write clock domain, as shown in fig. 4 (b), taking the clock phase difference between the write clock signal and the read clock signal as 3/8T as an example, corresponding to the clock phase difference of fig. 4 (b), as shown in fig. 5 (b), the write enable signal is sampled by using the read clock signal in the manner described above, the metastable state of the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal obtained by sampling does not occur, in order to ensure a certain data synchronization delay, thereby ensuring that there is enough time to read data, but the data synchronization delay is not too large, generally, in 2 clock cycles, the second sampling signal and the fourth sampling signal are selected as the read enable signal, the clock cycle of the second sampling signal and the fourth sampling signal is delayed relative to the write enable signal is the same, the read address is about 1.5 clock cycles later than the write address, and then the data synchronization delay from the write clock domain to the read clock domain is about 1.5 clock cycles.
3. The phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the clock phase difference between the write clock domain and the read clock domain belongs to [1/2T, 3/4T), T is a clock cycle of the write clock domain, as shown in fig. 4 (c), taking the clock phase difference between the write clock signal and the read clock signal as an example, corresponding to the clock phase difference of fig. 4 (c), as shown in fig. 5 (c), the write enable signal is sampled by using the read clock signal in the manner described above, the metastable state of the first sampling signal and the second sampling signal obtained by sampling occurs, the metastable state of the third sampling signal and the fourth sampling signal does not occur, so that in order to ensure a certain data synchronization delay, and thus, enough time is ensured to read data, but the data synchronization delay is not too large, generally within 2 clock cycles, the fourth sampling signal is selected by the multiplexer 045 as the read enable signal and the read address is generated, and the read address is about 1.5 clock cycles later than the write address, and the data synchronization delay from the read clock domain to the write clock domain is about 1.5 clock cycles.
4. The phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the value of the phase difference between the write clock domain and the read clock domain is greater than or equal to 3/4 clock cycles T, where T is the clock cycle of the write clock domain, as shown in fig. 4 (d), and the phase difference between the write clock signal and the read clock signal is 7/8T, as shown in fig. 5 (d), where the write enable signal is sampled by the read clock signal in the manner described above, and the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal obtained by sampling do not have metastable states, in order to ensure a certain data synchronization delay, thereby ensuring that there is enough time to read data, but the data synchronization delay is not too large, generally in 2 clock cycles, the multiplexer 045 selects the second sampling signal or the third sampling signal as the read enable signal and generates the read address, where the clock cycles of the second sampling signal and the third sampling signal are delayed with respect to the write enable signal are the same, and the read address is about 1 clock cycle later than the write address, so that the data synchronization delay from the read clock domain to the write clock domain is about 1 clock cycle later.
Based on the above clock domain crossing synchronization circuit, the clock domain channel circuit 04 may sample the write enable signal to obtain a plurality of sampling results, where a delay of some or all sampling results in the plurality of sampling results with respect to the write enable signal is within two clock periods, and secondly, a clock phase difference is provided between the write clock signal in the write clock domain and the read clock signal in the read clock domain, and according to the clock phase difference, one read enable signal is selected from the plurality of sampling results, and the delay of the selected read enable signal and the delay of the write enable signal may be controlled within two clock periods. The synchronization of the data between the two clock domains is also in two clock cycles, so compared with the scheme that at least two clock cycles delay exists in the synchronization of the data between the two clock domains, the data synchronization delay is smaller.
The application also provides a clock domain crossing synchronization method which can be applied to the clock domain crossing synchronization circuit to realize the function of the clock domain crossing synchronization circuit.
From the above description of the embodiments, it will be apparent to those skilled in the art that the present application may be implemented by means of software plus necessary general purpose hardware, or of course may be implemented by dedicated hardware including application specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components and the like. Generally, functions performed by computer programs can be easily implemented by corresponding hardware, and specific hardware structures for implementing the same functions can be varied, such as analog circuits, digital circuits, or dedicated circuits. However, a software program implementation is a preferred embodiment in many cases for the present application. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a readable storage medium, such as a floppy disk, a U-disk, a removable hard disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), a magnetic disk or an optical disk of a computer, etc., including several instructions for causing a computer device (which may be a personal computer or a server, etc.) to execute the method described in the embodiments of the present application.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
Claims (13)
1. A clock domain crossing synchronization circuit comprising a clock domain channel circuit, a write address generation circuit, a read address generation circuit, and a data buffer circuit, wherein:
the write address generation circuit is used for obtaining a write address according to a write enabling signal, the write address is used for controlling the data buffer circuit to receive input data, and the input data is in a write clock domain;
the clock domain channel circuit is used for sampling the write enabling signal to obtain a plurality of sampling results, and selecting one sampling result from the plurality of sampling results as a read enabling signal according to a clock phase difference, wherein the clock phase difference is a phase difference between a write clock signal in the write clock domain and a read clock signal in the read clock domain;
the read address generation circuit is used for obtaining a read address according to the read enabling signal, the read address is used for controlling the data buffer circuit to generate output data, and the output data is in the read clock domain;
the data buffer circuit is used for buffering the input data and generating the output data according to the write address and the read address.
2. The cross-clock domain synchronization circuit of claim 1, wherein the clock domain channel circuit comprises: the plurality of triggers are used for respectively sampling the write enable signal at the rising edge and the falling edge of the read clock signal so as to obtain a plurality of sampling results;
and the multi-channel signal selector is used for selecting one sampling result from the sampling results according to the clock phase difference to serve as the reading enabling signal.
3. The cross-clock domain synchronization circuit of claim 2, wherein the plurality of flip-flops comprises a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop;
the first trigger is configured to sample the write enable signal at a falling edge of the read clock signal to obtain a first sampling signal;
the second trigger is configured to sample the first sampling signal at a rising edge of the read clock signal to obtain a second sampling signal;
the third flip-flop is configured to sample the write enable signal at a rising edge of the read clock signal to obtain a third sampling signal;
the fourth trigger is configured to sample the third sampling signal at a rising edge of the read clock signal to obtain a fourth sampling signal, where the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal are the plurality of sampling results.
4. A clock domain crossing synchronization circuit as claimed in claim 3, wherein the multiplexer is operable to:
selecting the second sampling signal from the plurality of sampling results as the read enable signal in the case that the clock phase difference is [0T, 1/4T), wherein T is a clock cycle of the write clock domain or a clock cycle of the read clock domain;
or alternatively, the first and second heat exchangers may be,
selecting the second sampling signal or the fourth sampling signal from the plurality of sampling results as the read enable signal in the case where the clock phase difference is [1/4T, 1/2T);
or alternatively, the first and second heat exchangers may be,
selecting the fourth sampling signal from the plurality of sampling results as the read enable signal in the case where the clock phase difference is [1/2T, 3/4T);
or alternatively, the first and second heat exchangers may be,
and selecting the second sampling signal or the third sampling signal from the sampling results as the reading enabling signal under the condition that the value of the clock phase difference is larger than or equal to 3/4 clock period T.
5. The clock domain crossing synchronization circuit of any one of claims 1 to 4, further comprising a phase detector;
The phase discriminator is used for determining the clock phase difference according to the write clock signal and the read clock signal;
the phase detector is further configured to generate the write enable signal according to the write clock signal, where the write enable signal is valid when the clock phase difference between the write clock signal and the read clock signal is in a steady state.
6. The clock domain crossing synchronization circuit as claimed in any one of claims 1 to 4, further comprising a fifth D flip-flop;
the fifth D trigger is used for buffering and outputting the output data generated by the data buffering circuit under the drive of the read clock signal.
7. The clock domain crossing synchronization circuit as claimed in any one of claims 1 to 4, further comprising a write clock domain phase locked loop and a read clock domain phase locked loop;
the write clock domain phase-locked loop is used for obtaining the write clock signal according to a clock source signal;
the read clock domain phase-locked loop is configured to obtain the read clock signal according to the clock source signal.
8. The clock domain crossing synchronization circuit as claimed in any one of claims 1 to 4, wherein the data buffer circuit comprises a plurality of flip-flop groups, an input multiplexer comprising a plurality of output ports connected in one-to-one correspondence with a plurality of input terminals of the plurality of flip-flop groups, and an output multiplexer comprising a plurality of input ports connected in one-to-one correspondence with a plurality of output terminals of the plurality of flip-flop groups;
The input multi-path data selector is used for receiving the input data, selecting one output port from the plurality of output ports of the input multi-path data selector to output cache data according to the write address, wherein the cache data is obtained by the input data;
the plurality of trigger groups are used for caching the cache data under the drive of the write clock signal;
the output multi-path data selector is used for receiving the plurality of cache data output by the plurality of trigger groups and selecting one path of cache data from the plurality of cache data to be output as the output data according to the read address.
9. A method of synchronizing across clock domains, the method comprising:
obtaining a write address according to a write enable signal, and receiving and caching input data according to control of the write address, wherein the input data is in a write clock domain;
sampling the write enabling signal to obtain a plurality of sampling results, and selecting one sampling result from the plurality of sampling results as a read enabling signal according to a clock phase difference, wherein the clock phase difference is a phase difference between a write clock signal in the write clock domain and a read clock signal in the read clock domain;
And obtaining a read address according to the read enabling signal, and outputting the cached input data according to the control of the read address to generate output data, wherein the output data is in the read clock domain.
10. The method of claim 9, wherein the sampling the write enable signal to obtain a plurality of sampling results comprises:
and respectively sampling the write enable signal on the rising edge and the falling edge of the read clock signal to obtain a plurality of sampling results.
11. The method of claim 10, wherein sampling the write enable signal at the rising and falling edges of the read clock signal, respectively, to obtain the plurality of sampling results comprises:
sampling the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal;
sampling the first sampling signal at the rising edge of the reading clock signal to obtain a second sampling signal;
sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal;
and sampling the third sampling signal at the rising edge of the reading clock signal to obtain a fourth sampling signal, wherein the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are the sampling results.
12. The method of any of claims 11, wherein the selecting one of the plurality of sampling results as the read enable signal according to the clock phase difference comprises:
selecting the second sampling signal from the plurality of sampling results as the read enable signal in the case that the clock phase difference is [0T, 1/4T), wherein T is a clock cycle of the write clock domain or a clock cycle of the read clock domain;
or alternatively, the first and second heat exchangers may be,
selecting the second sampling signal or the fourth sampling signal from the plurality of sampling results as the read enable signal in the case where the clock phase difference is [1/4T, 1/2T);
or alternatively, the first and second heat exchangers may be,
selecting the fourth sampling signal from the plurality of sampling results as the read enable signal in the case where the clock phase difference is [1/2T, 3/4T);
or alternatively, the first and second heat exchangers may be,
and selecting the second sampling signal or the third sampling signal from the sampling results as the reading enabling signal under the condition that the value of the clock phase difference is larger than or equal to 3/4 clock period T.
13. The method according to any one of claims 9 to 12, further comprising:
Determining the clock phase difference from the write clock signal and the read clock signal;
the write enable signal is generated according to the write clock signal, wherein the write enable signal is valid when the clock phase difference between the write clock signal and the read clock signal is in a steady state.
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| CN114326515A (en) * | 2021-12-30 | 2022-04-12 | 西人马(西安)测控科技有限公司 | Synchronous acquisition method, system and equipment based on FPGA and readable storage medium |
| CN114048470B (en) * | 2022-01-13 | 2022-06-24 | 浙江大学 | Method and device for defending hardware attack based on TDC module and electronic equipment |
| CN115589372A (en) * | 2022-01-25 | 2023-01-10 | 浙江理工大学 | Non-resident data clock domain crossing method based on same-frequency out-of-phase clock |
| CN114185397B (en) * | 2022-02-15 | 2022-05-17 | 深圳市爱普特微电子有限公司 | Cross-clock domain data transmission circuit and method |
| CN117636943A (en) * | 2022-08-16 | 2024-03-01 | 长鑫存储技术有限公司 | Write leveling circuit applied to memory, control method and control device thereof |
| CN116521604B (en) * | 2023-07-05 | 2024-03-19 | 芯耀辉科技有限公司 | Method for synchronizing data and related device |
| CN116795172B (en) * | 2023-08-29 | 2023-12-12 | 芯耀辉科技有限公司 | Cross-clock domain processing method, medium and device for high-speed digital transmission |
| CN117420342B (en) * | 2023-11-08 | 2024-04-09 | 苏州联讯仪器股份有限公司 | Multichannel acquisition method, device, system, FPGA and sampling oscilloscope |
| CN118708537A (en) * | 2024-08-26 | 2024-09-27 | 爱芯元智半导体股份有限公司 | On-chip data processing device, method and equipment crossing clock domain and voltage domain |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5731770A (en) * | 1995-04-12 | 1998-03-24 | Sharp Kabushiki Kaisha | Digital data buffering device |
| US5963075A (en) * | 1996-08-19 | 1999-10-05 | Nec Corporation | Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at different times |
| US6956776B1 (en) * | 2004-05-04 | 2005-10-18 | Xilinx, Inc. | Almost full, almost empty memory system |
| US7038952B1 (en) * | 2004-05-04 | 2006-05-02 | Xilinx, Inc. | Block RAM with embedded FIFO buffer |
| CN101009487A (en) * | 2007-01-24 | 2007-08-01 | 华为技术有限公司 | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device |
| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
| CN106354652A (en) * | 2015-07-15 | 2017-01-25 | 上海华虹集成电路有限责任公司 | Nonvolatile memory read-write control circuit and method |
| CN107911102A (en) * | 2017-11-29 | 2018-04-13 | 长园深瑞继保自动化有限公司 | The symchronizing filter and method of cross-clock domain asynchronous data |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2993463B2 (en) * | 1997-05-08 | 1999-12-20 | 日本電気株式会社 | Synchronous circuit controller |
-
2019
- 2019-03-26 CN CN201980094534.6A patent/CN113615088B/en active Active
- 2019-03-26 WO PCT/CN2019/079663 patent/WO2020191611A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5731770A (en) * | 1995-04-12 | 1998-03-24 | Sharp Kabushiki Kaisha | Digital data buffering device |
| US5963075A (en) * | 1996-08-19 | 1999-10-05 | Nec Corporation | Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at different times |
| US6956776B1 (en) * | 2004-05-04 | 2005-10-18 | Xilinx, Inc. | Almost full, almost empty memory system |
| US7038952B1 (en) * | 2004-05-04 | 2006-05-02 | Xilinx, Inc. | Block RAM with embedded FIFO buffer |
| CN101009487A (en) * | 2007-01-24 | 2007-08-01 | 华为技术有限公司 | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device |
| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
| CN106354652A (en) * | 2015-07-15 | 2017-01-25 | 上海华虹集成电路有限责任公司 | Nonvolatile memory read-write control circuit and method |
| CN107911102A (en) * | 2017-11-29 | 2018-04-13 | 长园深瑞继保自动化有限公司 | The symchronizing filter and method of cross-clock domain asynchronous data |
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