CN113593463B

CN113593463B - Display mode switching system and method and display device

Info

Publication number: CN113593463B
Application number: CN202110874462.6A
Authority: CN
Inventors: 林准; 苏国火; 陈航宇; 张银龙; 刘冬; 陈芪飞; 刘建涛; 廖燕平
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2024-05-31
Anticipated expiration: 2041-07-30
Also published as: CN113593463A

Abstract

The invention provides a display mode switching system, a display mode switching method and a display device, and relates to the technical field of display. Wherein the system comprises a display processor and a timing controller; when a first instruction for switching the display mode is obtained, the display processor sends a switching trigger signal to the time sequence controller; the switching of the display mode comprises switching of the refresh frequency and switching of the resolution; the timing controller adjusts the timing of the clock signal in response to the switching trigger signal to achieve display mode switching. In the embodiment of the invention, when the display processor obtains the first instruction, the switching trigger signal is sent to the time sequence controller, the time sequence controller responds to the switching trigger signal, and the switching of the refresh frequency and the resolution can be realized by adjusting the time sequence of the clock signal, so that the switching of the display mode is realized, the display mode is matched with the current signal source, and the display abnormality of a picture is avoided.

Description

Display mode switching system and method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display mode switching system, a display mode switching method, and a display device.

Background

A timing controller (Timer Control Register, TCON) in the display device may control a gate driving circuit of the display panel by a clock signal to provide a switching control signal to the pixels and control a source driving circuit of the display panel by the pixel driving signal to provide a display data signal to the pixels.

Currently, the timing controller is designed according to only one specific display mode, and the display mode has a specific refresh frequency and a specific resolution, however, in practical application, when the signal source is switched to a signal source with other refresh frequency and/or other resolution, the timing controller is very easy to cause abnormal display of the picture if performing display control based on the current display mode.

Disclosure of Invention

The invention provides a display mode switching system, a display mode switching method and a display device, which are used for solving the problem that the conventional time sequence controller cannot support multiple display modes, so that abnormal picture display is easy to occur after a signal source is switched.

In order to solve the above problems, the present invention discloses a display mode switching system applied to a display device, the system comprising a display processor and a timing controller connected;

The display processor is configured to send a switching trigger signal to the timing controller when a first instruction for switching a display mode is obtained; the switching of the display mode comprises switching of refresh frequency and switching of resolution;

The timing controller is configured to adjust the timing of the clock signal in response to the switching trigger signal to achieve switching of the display mode.

Optionally, a target line is arranged between the display processor and the time schedule controller;

The display processor is configured to send a switching trigger signal to the time schedule controller through the target line; the signal form of the switching trigger signal is related to the target line.

Optionally, the display processor includes a first display data signal interface, the timing controller includes a second display data signal interface, the first display data signal interface is connected with the second display data signal interface, a signal line between the first display data signal interface and the second display data signal interface includes an integrated circuit bus signal line, and the target line is the integrated circuit bus signal line;

The display processor is specifically configured to send a switching trigger signal to the timing controller through the integrated circuit bus signal line; the signal form of the switching trigger signal is an integrated circuit bus command signal.

Optionally, the display processor includes a first input/output port, the timing controller includes a second input/output port, and the target line is a connection line between the first input/output port and the second input/output port;

The display processor is specifically configured to send a switching trigger signal to the time schedule controller through the first input/output port; the signal form of the switching trigger signal is a level signal.

Optionally, the display processor includes a first display data signal interface, the timing controller includes a second display data signal interface, the first display data signal interface is connected with the second display data signal interface, a signal line between the first display data signal interface and the second display data signal interface includes a display data signal line, and the target line is the display data signal line;

The display processor is specifically configured to send a switching trigger signal to the timing controller through the display data signal line; the signal form of the switching trigger signal is a display data signal.

Optionally, the switching trigger signal is a target display data signal corresponding to a preset picture, where the preset picture includes at least one pattern area;

the time schedule controller is specifically configured to determine the size and the pixel arrangement mode of each pattern area according to the target display data signals; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to the second display mode; when the size and the pixel arrangement mode of each pattern area are determined to meet a second switching condition, switching from the current second display mode to the first display mode;

The first switching condition includes: the size of each pattern area is larger than the corresponding first preset size, and the pixel arrangement mode of each pattern area is the corresponding first preset arrangement mode;

The second switching condition includes: when the size of each pattern area is larger than the second preset size corresponding to each pattern area, and the pixel arrangement mode of each pattern area is the second preset arrangement mode corresponding to each pattern area;

For the same pattern area, the first preset size and the second preset size corresponding to the pattern area are different; and/or the first preset arrangement mode and the second preset arrangement mode corresponding to the pattern area are different.

Optionally, the display device further includes a display panel, and the display panel is connected with the timing controller;

the time schedule controller is further configured to output a display data signal corresponding to a preset aging mode picture to the display panel so as to enter an aging mode, and switch the display mode in the aging mode.

Optionally, the display processor is specifically configured to send, when a first instruction for switching a display mode is obtained, a second instruction for entering the burn-in mode to the timing controller through the integrated circuit bus signal line;

The time schedule controller is specifically configured to respond to the second instruction, output a display data signal corresponding to the aging mode picture to the display panel so as to enter the aging mode, and switch the display mode in the aging mode.

Optionally, the display processor further includes a third input/output port, and the timing controller further includes a fourth input/output port, where the third input/output port is connected to the fourth input/output port;

The display processor is specifically configured to send a second instruction for entering the aging mode to the time schedule controller through the third input/output port when a first instruction for switching the display mode is obtained;

Optionally, the timing controller is specifically configured to output, when it is determined that the size and the pixel arrangement manner of each pattern area meet the first switching condition, a display data signal corresponding to the aging mode picture to the display panel so as to enter the aging mode, and switch from the current first display mode to the second display mode in the aging mode;

When the size and the pixel arrangement mode of each pattern area meet the second switching condition, outputting display data signals corresponding to the aging mode picture to the display panel so as to enter the aging mode, and switching from the current second display mode to the first display mode in the aging mode.

Optionally, the display device further comprises a backlight module, and the backlight module is connected with the display processor;

The display processor is further configured to control the backlight module to be turned off after a first instruction for switching the display mode is obtained;

the time schedule controller is further configured to switch the display mode under the condition that the backlight module is closed.

Optionally, the display processor is further configured to control the backlight module to be turned on when the on condition of the backlight module is satisfied;

Wherein, the starting condition of the backlight module comprises: the display processor receives a third instruction which is sent by the time sequence controller after the display mode is switched and is used for starting the backlight module; or the display processor achieves a preset time length after closing the backlight module, wherein the preset time length is longer than the time length required by the time sequence controller for switching the display modes.

Optionally, the first instruction is specifically configured to switch from a first display mode to a second display mode, where a refresh frequency of the second display mode is higher than a refresh frequency of the first display mode, and a resolution of the second display mode is lower than a resolution of the first display mode; in the first display mode, each of the clock signals is sequentially driven;

at least two adjacent clock signals are divided into a clock signal group, the number of the clock signals included in each clock signal group is the same, and the clock signals included in each clock signal group are not repeated;

The display processor is further configured to send display data of a pixel row corresponding to a target clock signal to the timing controller after sending the switching trigger signal to the timing controller; the time sequence controller is specifically configured to respond to the switching trigger signal, adjust each clock signal in the clock signal group to be synchronously driven with a target clock signal, and output display data of a pixel row corresponding to the target clock signal; or alternatively

The display processor is further configured to send display data of each pixel row to the timing controller after sending the switching trigger signal to the timing controller; the time sequence controller is specifically configured to respond to the switching trigger signal, adjust each clock signal in the clock signal group to be synchronously driven with a target clock signal, and output display data of a pixel row corresponding to the target clock signal;

Wherein in the same clock signal group, the target clock signal is any one clock signal in the clock signal group.

Optionally, the first instruction is specifically configured to switch from a second display mode to a first display mode, where a refresh frequency of the second display mode is higher than a refresh frequency of the first display mode, and a resolution of the second display mode is lower than a resolution of the first display mode;

in the second display mode, each of the clock signals in the clock signal group is synchronously driven with a target clock signal; the target clock signal is any one clock signal in the clock signal group;

The display processor is further configured to send display data of each pixel row to the timing controller after sending the switching trigger signal to the timing controller;

the timing controller is specifically configured to adjust the respective clock signals to be sequentially driven in response to the switching trigger signal, and to output the display data of each pixel row.

Optionally, the display processor comprises a system on chip.

In order to solve the above problems, the present invention also discloses a display mode switching method, which is applied to the above display mode switching system, and the method comprises:

When the display processor obtains a first instruction for switching the display mode, a switching trigger signal is sent to the time sequence controller; the switching of the display mode comprises switching of refresh frequency and switching of resolution;

the time sequence controller responds to the switching trigger signal and adjusts the time sequence of the clock signal so as to realize the switching of the display mode.

In order to solve the problems, the invention also discloses a display device which comprises the display mode switching system.

Optionally, the display device further includes a display panel and a backlight module, the display panel is connected with the timing controller in the display mode switching system, and the backlight module is connected with the display processor in the display mode switching system.

Compared with the prior art, the invention has the following advantages:

in the embodiment of the invention, when the display processor obtains the first instruction for switching the display mode, the switching trigger signal can be sent to the time sequence controller, and the time sequence controller responds to the switching trigger signal and can realize the switching of the refresh frequency and the resolution by adjusting the time sequence of the clock signal, so that the switching of the display mode can be realized, the refresh frequency and the resolution corresponding to the display mode and the current signal source are matched, and the display abnormality of a picture is avoided.

Drawings

FIG. 1 is a block diagram showing a display mode switching system according to a first embodiment of the present invention;

FIG. 2 is a timing diagram of clock signals in a first display mode according to a first embodiment of the invention;

FIG. 3 is a timing diagram of clock signals in a second display mode according to a first embodiment of the invention;

FIG. 4 is a schematic diagram of a display data signal interface of a display processor and a timing controller according to a first embodiment of the present invention;

FIG. 5 is a schematic diagram of an interface pin according to a first embodiment of the present invention;

FIG. 6 is a schematic diagram of an input/output port of a display processor and a timing controller according to a first embodiment of the present invention;

fig. 7 is a schematic view of a preset screen including a pattern area according to a first embodiment of the present invention;

FIG. 8 is a flowchart showing steps of a display mode switching method according to a second embodiment of the present invention;

Fig. 9 is a block diagram showing a structure of a display device according to a third embodiment of the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Example 1

Referring to fig. 1, there is shown a block diagram of a display mode switching system according to a first embodiment of the present invention, the system 100 is applied to a display device, and the system 100 includes a display processor 110 and a timing controller 120 connected.

A display processor 110 configured to transmit a switching trigger signal to the timing controller 120 when a first instruction for switching the display mode is obtained; the switching of the display mode comprises switching of the refresh frequency and switching of the resolution;

the timing controller 120 is configured to adjust the timing of the clock signal in response to the switching trigger signal to realize switching of the display mode.

In a normal display process, the display data signal may be output to the display processor 110, and after the display processor 110 performs processing such as format conversion, the display data signal is output to the timing controller 120, and the timing controller 120 may further output the clock signal and the display data signal to the connected display panel.

In an embodiment of the present invention, the display processor 110 optionally includes a System On Chip (SOC).

In the embodiment of the invention, in the process of normal display of the display device, the switching function of the display mode can be triggered by the first instruction for switching the display mode.

In an alternative implementation, the user may trigger the display mode switching function through a key on the remote control of the display device, a virtual touch key displayed by the display device, an entity key external to the display device, and the like, and when the related key is triggered, the display processor 110 may obtain a first instruction for switching the display mode.

In practical applications, the user may manually trigger the first instruction to match the switched display mode with the current signal source when the current display mode does not match the current signal source (e.g., display insufficiency occurs, the screen size is far smaller than the display area size, etc.). Or, the user may manually trigger the first instruction when the current display mode is matched with the current signal source, and accordingly, the display processor 110 may switch the signal source when the timing controller 120 switches the display mode, so that the switched display mode is matched with the switched signal source.

In another alternative implementation, where the signal source may be automatically switched, the first instruction to switch the display mode may be generated when the display processor 110 detects a change in the refresh frequency and/or resolution of the signal source.

After the display processor 110 obtains the first instruction, a switching trigger signal may be sent to the timing controller 120, where the timing controller 120 responds to the switching trigger signal, and may implement switching of the refresh frequency by adjusting the timing of the clock signal, and may implement switching of the resolution by adjusting the output of the display data signal, so that switching of the display mode may be implemented, so that the refresh frequency and the resolution corresponding to the display mode and the current signal source are matched, and display abnormality of the picture is avoided.

Optionally, referring to fig. 1, a target line X is disposed between the display processor 110 and the timing controller 120;

A display processor 110 configured to transmit a switching trigger signal to the timing controller 120 through the target line X; the signal form of the switching trigger signal is related to the target line. That is, the target line determines the form in which the switch trigger signal is sent to the timing controller 120, and the processing of the timing controller 120 will be different according to the signal form.

The manner in which the display processor 110 sends the switching trigger signal to the timing controller 120, and the specific form of the switching trigger signal, will be described below.

1 St alternative implementation:

Referring to fig. 4, optionally, the display processor 110 includes a first display data signal interface 1101, the timing controller 120 includes a second display data signal interface 1201, the first display data signal interface 1101 is connected to the second display data signal interface 1201, a signal line between the first display data signal interface 1101 and the second display data signal interface 1201 includes an integrated circuit bus (Inter-INTEGRATED CIRCUIT, I2C) signal line 10A, and accordingly, the target line X is the integrated circuit bus signal line 10A;

a display processor 110 specifically configured to send a switch trigger signal to the timing controller 120 through the integrated circuit bus signal line 10A; the signal form of the switching trigger signal is an integrated circuit bus command signal.

In practical applications, the first display data signal interface 1101 and the second display data signal interface 1201 may be, for example, V-By-One (VBO) interfaces. Referring to fig. 5, an interface connector of a V-By-One interface is shown, where the V-By-One interface is provided with an I2C pin 02 in addition to a V-By-One pin 01, and an I2C channel may be established between the first display data signal interface 1101 and the second display data signal interface 1201 through the I2C pin 02.

In implementation 1, the switching trigger signal may be an I2C signal, and the display processor 110 may send the switching trigger signal to the timing controller 120 through the I2C signal line. In this way, the display processor 110 can transmit the switching trigger signal to the timing controller 120 by using the I2C channel of the display data signal interface itself, without adding an additional signal line or interface.

Specifically, referring to fig. 5, the I2C pin 02 includes an SDA pin and an SCL pin, and the I2C signal line 10A includes an SDA signal line and an SCL signal line, respectively, wherein the SDA signal line is an I2C data signal line and the SCL signal line is an I2C clock signal line.

2 Nd alternative implementation:

referring to fig. 6, optionally, the display processor 110 includes a first input/output (IO) port 1102, the timing controller 120 includes a second input/output port 1202, and the target line X is a connection line between the first input/output port 1102 and the second input/output port 1202.

The display processor 110 is specifically configured to send a switching trigger signal to the timing controller 120 through the first input-output port 1102; the signal form of the switching trigger signal is a level signal.

In practical applications, some spare IO ports are usually provided between the display processor 110 and the timing controller 120. Accordingly, in implementation 2, the switching trigger signal may specifically be a level signal, where the first display mode may be switched to the second display mode by a high level indication, and the second display mode may be switched to the first display mode by a low level indication, or vice versa. In this way, the display processor 110 can transmit the switching trigger signal to the timing controller 120 using the spare IO port without adding an additional signal line or interface.

3 Rd alternative implementation:

Referring to fig. 4, optionally, the display processor 110 includes a first display data signal interface 1101, the timing controller 120 includes a second display data signal interface 1201, the first display data signal interface 1101 is connected to the second display data signal interface 1201, a signal line between the first display data signal interface 1101 and the second display data signal interface 1201 includes a display data signal line 10B, and accordingly, the target line X is the display data signal line 10B.

The display processor 110 is specifically configured to send a switching trigger signal to the timing controller 120 through the display data signal line 10B; the signal form of the switching trigger signal is a display data signal.

For example, the first display data signal interface 1101 and the second display data signal interface 1201 are both VBO (V-By-One) interfaces, and the display data signal line 10B is the signal line between the above-mentioned VBO pins 01, and a VBO channel may be established between the first display data signal interface 1101 and the second display data signal interface 1201 through the VBO pins 01.

In implementation 3, the switch trigger signal may specifically be a VBO signal, and the display processor 110 may send the switch trigger signal to the timing controller 120 through a VBO signal line. In this way, the display processor 110 can transmit the switching trigger signal to the timing controller 120 by using the display data signal channel of the display data signal interface itself, without adding an additional signal line or interface.

Of course, in the embodiment of the present invention, the first display data signal interface 1101 and the second display data signal interface 1201 may be other types of signal interfaces, which is not limited in the embodiment of the present invention.

Further, in the 3 rd implementation manner, since the timing controller 120 has a function of detecting the display data signal, a special pattern in the screen can be identified (PATTERN DETECT functions, refer to related art for details), and therefore, the triggering timing of the display mode switching can be determined by using the function of the timing controller 120. In the 3 rd implementation manner, the switching trigger signal is in the form of a display data signal, that is, a specific frame may be displayed based on the switching trigger signal, when the timing controller 120 receives the switching trigger signal, the function PATTERN DETECT is triggered, some patterns in the corresponding frame may be determined by detecting the switching trigger signal, and if some features in the patterns meet the preset condition, the display mode may be switched.

Correspondingly, the switching trigger signal may be a target display data signal corresponding to a preset picture, where the preset picture includes at least one pattern area;

The timing controller 120 is specifically configured to determine the size and the pixel arrangement mode of each pattern area according to the target display data signal; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to the second display mode; when the size and the pixel arrangement mode of each pattern area are determined to meet the second switching condition, switching from the current second display mode to the first display mode.

The first switching condition includes: the size of each pattern area is larger than the corresponding first preset size, and the pixel arrangement mode of each pattern area is the corresponding first preset arrangement mode.

The second switching condition includes: when the size of each pattern area is larger than the second preset size corresponding to each pattern area, and the pixel arrangement mode of each pattern area is the second preset arrangement mode corresponding to each pattern area.

In an alternative embodiment, the first preset size corresponding to each pattern area may be the same (hereinafter, this will be taken as an example), and may be different. The second preset size corresponding to each pattern area may be the same (hereinafter, this will be taken as an example), and may be different.

Taking the preset screen shown in fig. 7 as an example, the preset screen presets a screen 1, a pattern area 2, a pattern area 3 and a pattern area 4.

When the dimensions (X1, Y1) of the pattern area 1, the dimensions (X2, Y2) of the pattern area 2, the dimensions (X3, Y3) of the pattern area 3, and the dimensions (X4, Y4) of the pattern area 4 are all larger than the first preset dimensions (A1, B1), and the pixel arrangement of the pattern area 1 is the first preset arrangement (for example, one horizontal line and one horizontal line are sequentially arranged), the pixel arrangement of the pattern area 2 is the first preset arrangement (for example, one vertical line and one vertical line are sequentially arranged) of the pattern area 2, the pixel arrangement of the pattern area 3 is the first preset arrangement (for example, two horizontal lines and two horizontal lines are sequentially arranged) of the pattern area 3, and the pixel arrangement of the pattern area 4 is the first preset arrangement (for example, two vertical lines and one horizontal line are sequentially arranged) of the pattern area 4, the dimensions and the pixel arrangement of the pattern area 1-4 are determined to satisfy the first switching condition, and the timing controller 120 can switch from the current first display mode to the second display mode.

When the dimensions (X1, Y1) of the pattern area 1, the dimensions (X2, Y2) of the pattern area 2, the dimensions (X3, Y3) of the pattern area 3, and the dimensions (X4, Y4) of the pattern area 4 are all larger than the second preset dimensions (A2, B2), and the pixel arrangement of the pattern area 1 is the second preset arrangement (for example, a vertical black-to-vertical white arrangement) corresponding to the pattern area 1, the pixel arrangement of the pattern area 2 is the second preset arrangement (for example, a horizontal black-to-horizontal white arrangement) corresponding to the pattern area 2, the pixel arrangement of the pattern area 3 is the second preset arrangement (for example, a two vertical black-to-two vertical white arrangement) corresponding to the pattern area 3, and the pixel arrangement of the pattern area 4 is the second preset arrangement (for example, a two horizontal white-to-horizontal black arrangement) corresponding to the pattern area 4, it is determined that the dimensions and the pixel arrangement of the pattern area 1-4 satisfy the second switching condition, and the timing controller 120 can switch from the current second display mode to the first display mode.

In specific application, the number of pattern areas is not suitable to be set too small or too large, the misjudgment is increased due to too small pattern areas, the detection amount is increased due to too large pattern areas, and the operation efficiency is low.

In addition, in practical applications, in the process of switching display modes, image quality problems such as flicker and abnormal images may occur, so that in order to avoid users seeing these image quality problems during the switching process, the user experience may be improved, and the switching process of the display modes may be performed in an abnormal display mode (for example, an aging mode) with a specific image, or the switching of the display modes may be performed when the backlight module is turned off.

In an alternative embodiment:

Optionally, the timing controller 120 is further configured to output a display data signal corresponding to a preset aging mode screen, so as to enter an aging mode, and switch the display mode in the aging mode.

In practical application, the display device further includes a display panel, the display panel is connected to the output end of the timing controller 120, and the timing controller 120 can enter the aging mode by outputting a display data signal corresponding to the aging mode picture to the display panel, and switch the display mode in the aging mode.

Corresponding to the 1 st alternative implementation (sending a switching trigger signal via the I2C channel) described above, the display processor 110 is specifically configured to send a second instruction for entering the burn-in mode to the timing controller 120 via the integrated circuit bus signal line 10A when a first instruction for switching the display mode is obtained.

The timing controller 120 is specifically configured to output, in response to the second instruction, a display data signal corresponding to the aging mode screen to the display panel, so as to enter the aging mode, and switch the display mode in the aging mode.

In this embodiment, the display processor 110 may transmit a second instruction for displaying an aging mode picture (a picture may be custom, full black or a specific picture) to the timing controller 120 through the I2C channel.

In correspondence to the above-mentioned 2 nd alternative implementation manner (the switching trigger signal is sent through the IO port), specifically optionally, referring to fig. 6, the display processor 110 further includes a third input/output port 1103, and the timing controller 120 further includes a fourth input/output port 1203, where the third input/output port 1103 is connected to the fourth input/output port 1203;

The display processor 110 is specifically configured to, when obtaining a first instruction for switching the display mode, send a second instruction for entering the burn-in mode to the timing controller 120 through the third input output port 1103;

In this embodiment, the display processor 110 may transmit a second instruction for displaying the aging mode screen to the timing controller 120 through the IO port.

In the above two embodiments, the display processor 110 may send the second instruction to the timing controller 120 first to make the timing controller 120 enter the aging mode, and then send the switching trigger signal to the timing controller 120 to make the timing controller 120 switch the display mode, so as to ensure that the timing controller enters the aging mode before the display mode is switched, and avoid the problem of image quality occurring in the switching process from being seen by the user.

Corresponding to the 3 rd alternative implementation manner (the switching trigger signal is sent through the display data signal line), specifically and optionally, the timing controller 120 is specifically configured to output, when determining that the size and the pixel arrangement manner of each pattern area meet the first switching condition, a display data signal corresponding to the aging mode screen to the display panel so as to enter the aging mode, and in the aging mode, switch from the current first display mode to the second display mode;

when the size and the pixel arrangement mode of each pattern area meet the second switching condition, outputting a display data signal corresponding to the aging mode picture to the display panel so as to enter an aging mode, and switching from the current second display mode to the first display mode in the aging mode.

In the third embodiment, the display processor 110 may send the switching trigger signal to the timing controller 120, then the timing controller 120 detects the pattern area, and when determining that the feature of the pattern area meets the switching condition, the timing controller 120 enters the aging mode, and then switches the display mode, so as to ensure that the aging mode is entered before the display mode is switched, and avoid the problem of image quality occurring in the switching process from being seen by the user.

In the third embodiment, the switching trigger signal is transmitted in the form of a display data signal, and if the second command is also transmitted in the form of a display data signal through the same channel, the detection of the pattern area is affected, so the timing controller 120 may enter the aging mode after the detection of the pattern area is completed, and then switch the display mode in the aging mode.

In an embodiment of the present invention, the timing controller 120 may exit the burn-in mode after the display mode switching is completed.

In another alternative embodiment:

Optionally, the display device further includes a backlight module, and the backlight module is connected to the display processor 110.

The display processor 110 is further configured to control the backlight module to be turned off after obtaining the first instruction for switching the display mode.

The timing controller 120 is further configured to switch the display mode when the backlight module is turned off.

Corresponding to the 1 st and 2 nd alternative implementations, the display processor 110 may control the backlight module to be turned off first, and then send a switching trigger signal to the timing controller 120, so that the timing controller 120 performs switching of the display mode, thereby ensuring that the backlight module is turned off before the display mode is switched, and avoiding the problem of image quality occurring in the switching process from being seen by the user.

Corresponding to the 3 rd alternative implementation manner, the display processor 110 may send a switching trigger signal to the timing controller 120, and control the backlight module to be turned off at the same time, then the timing controller 120 performs detection of the pattern area (the detection function may be implemented when the backlight module is turned off), and then performs switching of the display mode when determining that the feature of the pattern area meets the switching condition, so as to ensure that the backlight module is turned off before switching of the display mode, and avoid the problem of image quality occurring in the switching process from being seen by the user.

Further optionally, the display processor 110 is further configured to control the backlight module to be turned on when an on condition of the backlight module is satisfied.

Wherein, the starting condition of backlight unit includes: the display processor 110 receives a third instruction for starting the backlight module, which is sent by the timing controller 120 after the switching of the display mode is completed; or the display processor 110 may switch off the backlight module for a preset period of time, which is longer than the period of time required for the timing controller 120 to switch the display modes.

Corresponding to the 1 st and 2 nd alternative implementations, the third instruction may be transmitted through a channel (I2C channel or IO port) for transmitting a switching trigger signal between the display processor 110 and the timing controller 120, and after the timing controller 120 completes switching the display mode, the third instruction for starting the backlight module may be sent to the display processor 110, so that the display processor 110 may control the backlight module to be started.

Corresponding to the 3 rd alternative implementation manner, since the switching trigger signal does not occupy the I2C channel or the IO port, the timing controller 120 cannot control the display processor 110 to turn on the backlight module through the instruction. In one embodiment, the display processor 110 may wait a period of time after turning off the backlight module, and reserve a certain time for the timing controller 120 to complete the switching, and the display processor 110 controls the backlight module to turn on after the backlight module is turned off for a period of time.

The manner of switching from the first display mode (high resolution, low refresh frequency) to the second display mode (low resolution, high refresh frequency) and vice versa will be described in detail below.

1. The switching mode from the first display mode to the second display mode is as follows:

Optionally, the first instruction is specifically configured to switch from the first display mode to the second display mode, where a refresh frequency (for example, 120 Hz) of the second display mode is higher than a refresh frequency (for example, 60 Hz) of the first display mode, and a resolution (for example, a lateral resolution of 8k×a longitudinal resolution of 2K, hereinafter referred to as 8k×2K) of the second display mode is lower than a resolution (for example, a lateral resolution of 8k×a longitudinal resolution of 4K, hereinafter referred to as 8k×4K) of the first display mode; in the first display mode, the respective clock signals are sequentially driven, as shown in fig. 2.

Referring to fig. 2, adjacent at least two clock signals are divided into one clock signal group, the number of clock signals included in each clock signal group is the same, and the clock signals included in each clock signal group are not repeated.

In one manner, the display processor 110 is further configured to send the display data of the pixel row corresponding to the target clock signal to the timing controller 120 after sending the switching trigger signal to the timing controller 120; the timing controller 120 is specifically configured to adjust each clock signal in the clock signal group to be driven in synchronization with the target clock signal (as shown in fig. 3) in response to the switching trigger signal, and output display data of the pixel row corresponding to the target clock signal. Or alternatively

In another manner, the display processor 110 is further configured to send the display data signal of each pixel row to the timing controller 120 after sending the switching trigger signal to the timing controller 120; the timing controller is specifically configured to respond to the switching trigger signal, adjust each clock signal in the clock signal group to be driven in synchronization with the target clock signal (as shown in fig. 3), and output display data of a pixel row corresponding to the target clock signal.

In the same clock signal group, the target clock signal is any one clock signal in the clock signal group.

In a specific embodiment, referring to fig. 3, STV0 is a reset signal of the GOA unit of the last stage, and STV1 is a start input signal of the GOA unit of the first stage. In this embodiment, two adjacent clock signals may be divided into one clock signal group, CLK1 and CLK2 into one group, CLK3 and CLK4 into one group, CLK5 and CLK6 into one group, CLK7 and CLK8 into one group, CLK9 and CLK10 into one group, and CLK11 and CLK12 into one group.

When the display mode needs to be switched, the display data of the even pixel rows may be discarded first, the display data of the odd pixel rows may be retained (or vice versa), then the timing controller 120 adjusts the second clock signal in the clock signal group to be driven synchronously with the first clock signal in the clock signal group, that is, CLK2 is adjusted to be driven synchronously with CLK1, CLK4 is adjusted to be driven synchronously with CLK3, CLK6 is adjusted to be driven synchronously with CLK5, CLK8 is adjusted to be driven synchronously with CLK7, CLK10 is adjusted to be driven synchronously with CLK9, and CLK12 is adjusted to be driven synchronously with CLK11 (or vice versa). Therefore, two rows of grid lines can be simultaneously started to realize simultaneous charging of two rows of pixel lines, the refreshing frequency of a picture can be adjusted from 60Hz to 120Hz, the resolution of the picture can be adjusted from 8K multiplied by 4K to 8K multiplied by 2K, and the switching from the first display mode to the second display mode is realized.

It should be noted that, the step of discarding the display data of a portion of the pixel rows (for example, the step of discarding the display data of the even pixel rows in the above example) may be performed by the display processor 110 or may be performed by the timing controller 120, which is not limited in particular in the embodiment of the present invention.

2. Switching mode from the second display mode to the first display mode:

optionally, the first instruction is specifically configured to switch from the second display mode to the first display mode, where a refresh frequency (e.g. 120 Hz) of the second display mode is higher than a refresh frequency (e.g. 60 Hz) of the first display mode, and a resolution (e.g. 8k×2K) of the second display mode is lower than a resolution (e.g. 8k×4K) of the first display mode.

Referring to fig. 3, adjacent at least two clock signals are divided into one clock signal group, the number of clock signals included in each clock signal group is the same, and the clock signals included in each clock signal group are not repeated.

In the second display mode, each clock signal in the clock signal group is driven in synchronization with the target clock signal (as shown in fig. 3); the target clock signal is any one of the clock signal groups.

The display processor 110 is further configured to transmit the display data of each pixel row to the timing controller 120 after transmitting the switching trigger signal to the timing controller 120;

The timing controller 120 is specifically configured to adjust the respective clock signals to be sequentially driven in response to the switching trigger signal, as shown in fig. 2, and to output (output to the display panel) the display data of each pixel row.

Wherein the second switching mode and the first switching mode are opposite processes. Referring to FIG. 2, in one particular embodiment, timing controller 120 may adjust CLK1-CLK12 to be driven sequentially in response to a toggle trigger signal and display data is not partially discarded. In this way, the refresh frequency of the picture can be adjusted from 120Hz to 60Hz, and the resolution of the picture can be adjusted from 8Kx2K to 8Kx4K, thereby realizing the switching from the first display mode to the first display mode.

The following will provide 3 specific examples:

First embodiment: the TCON (timing controller 120) receives an instruction (switching trigger signal) through an I2C channel of a VBO interface of the SOC (display processor 110), thereby controlling switching of the display mode.

Starting up an initial state: the power-up defaults to normal display mode (8K 4K 60 Hz).

Display mode switching process: when the display mode needs to be switched, the SOC sends a Force imaging instruction (second instruction) to the TCON, and enters an imaging (aging) mode;

normal display mode→high brush display mode (8 k×2k120hz): in the imaging mode, the SOC sends a high-brush GIP mode instruction (switching trigger signal) to the TCON through the I2C channel, and discards display data corresponding to even pixel rows, the VBO signal is switched from 8K multiplied by 4K 60Hz to 8K multiplied by 2K120Hz, and when the TCON receives the high-brush GIP mode instruction, the display mode is switched from the normal display mode to the high-brush display mode (fig. 2 to fig. 3);

High brush display mode→normal display mode: in the imaging mode, the SOC sends a normal GIP mode instruction (switching trigger signal) through the I2C channel, display data corresponding to even pixel rows are reserved, the VBO signal is switched from 8K×2K120Hz to 8K×4K60 Hz, and when the TCON receives the normal GIP mode instruction, the display mode is switched from the high-speed display mode to the normal display mode (fig. 3 to fig. 2).

The SOC sends an Exit imaging instruction to the TCON through the I2C channel, and the TCON exits the imaging mode.

Shutdown state: the display mode can be normally powered off no matter what display mode, and the display mode is still normal after the display mode is powered on.

The I2C communication commands for SOC are shown in Table 1 below (with HX8898ATCON IC as an example).

TABLE 1

Second embodiment: the TCON sets the corresponding IO1 and IO2 ports for receiving a Level signal (H/L Level) provided by the SOC, thereby controlling switching of the display mode.

The high level voltage range is set to 2.7-3.3V, and the low level voltage range is set to 0-0.6V.

IO1 is used to control normal display mode/imaging mode, high: flag mode, low level: normal display mode.

IO2 is used to control display mode switching, H: normal display mode→high brush display mode, L: high-brush display mode→normal display mode.

A start-up initial mode: IO1 is low, IO2 does not make level judgment, and defaults to normal display mode.

Display mode switching process: IO1 is set from low level to high level, SOC controls TCON to enter an imaging mode, and TCON starts to detect the state of IO 2;

normal display mode→high brush display mode: in the imaging mode, the SOC inputs a high level to the TCON IO2, discards display data corresponding to even pixel rows, switches a VBO signal from 8K multiplied by 4K60Hz to 8K multiplied by 2K120Hz, and switches a display mode from a normal display mode to a high-brush display mode;

high brush display mode→normal display mode: in the imaging mode, the SOC inputs a low level to the TCON IO2, and retains display data corresponding to even pixel rows, the VBO signal is switched from 8Kx2K120Hz to 8Kx4K60Hz, and the TCON switches the display mode from a high-brush display mode to a normal display mode.

The display mode switching is completed: the SOC completes the VBO signal switching, IO1 is changed from high level to low level, and TCON exits from the shooting mode.

The IO port level signals are as follows in table 2.

TABLE 2

It should be noted that, in the power-on initial mode, IO2 may be set to a high level in advance, but TCON does not determine the IO2 state in the power-on mode.

In addition, after entering the imaging mode, the TCON may start detecting the status of IO2 again after delaying the display time of at least 1 frame of picture.

Third embodiment: by utilizing PATTERN DETECT functions of the TCON, the TCON switches display modes after detecting the special pattern sent by the SOC.

A start-up initial mode: the power-up defaults to normal display mode.

Display mode switching process: when the display mode needs to be switched, the SOC sends a specific pattern, the TCON triggers PATTERN DETECT functions, meanwhile, the SOC controls the backlight module to be turned off, and after the SOC sends the specific pattern and delays 500ms, the backlight module is controlled to be turned on again. Wherein 500ms is a theoretical value, and different display devices can be set according to the actual display mode switching time of the SOC and the TCON.

Normal display mode→high brush display mode: if the TCON detects PatternA, the system enters an imaging mode, the SOC discards the display data corresponding to even pixel rows, the VBO signal is switched from 8K multiplied by 4K 60Hz to 8K multiplied by 2K 120Hz, and the TCON switches the display mode from the normal display mode to the high-brush display mode.

High brush display mode→normal display mode: if the TCON detects PatternB, the processing mode is entered, the SOC keeps the display data corresponding to even pixel rows, the VBO signal is switched from 8K multiplied by 2K 120Hz to 8K multiplied by 4K 60Hz, and the TCON switches the display mode from the high-speed display mode to the normal display mode.

In the embodiment of the invention, when the display processor obtains the first instruction for switching the display mode, the switching trigger signal can be sent to the time sequence controller, the time sequence controller responds to the switching trigger signal, the switching of the refresh frequency can be realized by adjusting the time sequence of the clock signal, and the switching of the resolution can be realized by adjusting the output of the display data signal, so that the switching of the display mode can be realized, the refresh frequency and the resolution corresponding to the display mode and the current signal source are matched, and the display abnormality of a picture is avoided.

Example two

Fig. 8 is a flowchart showing a display mode switching method according to a second embodiment of the present invention, where the method is applied to the display mode switching system, and the method includes the following steps:

step 801: when the display processor obtains a first instruction for switching the display mode, a switching trigger signal is sent to the time sequence controller; the switching of the display mode includes switching of a refresh frequency and switching of a resolution.

Step 802: the time sequence controller responds to the switching trigger signal and adjusts the time sequence of the clock signal so as to realize the switching of the display mode.

The sending a switching trigger signal to the timing controller includes:

the display processor sends a switching trigger signal to the time sequence controller through the target line; the signal form of the switching trigger signal is related to the target line.

The sending a switching trigger signal to the timing controller includes: the display processor sends a switching trigger signal to the time sequence controller through the integrated circuit bus signal line; the signal form of the switching trigger signal is an integrated circuit bus command signal.

the sending a switching trigger signal to the timing controller includes: the display processor sends a switching trigger signal to the time sequence controller through the first input/output port; the signal form of the switching trigger signal is a level signal.

the sending a switching trigger signal to the timing controller includes: the display processor sends a switching trigger signal to the time sequence controller through the display data signal line; the signal form of the switching trigger signal is a display data signal.

The step 802 includes: the time schedule controller determines the size and the pixel arrangement mode of each pattern area according to the target display data signals; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to the second display mode; when the size and the pixel arrangement mode of each pattern area are determined to meet a second switching condition, switching from the current second display mode to the first display mode;

Optionally, the method further comprises: and the time schedule controller outputs a display data signal corresponding to a preset aging mode picture so as to enter an aging mode, and the display mode is switched in the aging mode.

Optionally, the timing controller outputs a display data signal corresponding to a preset aging mode picture to the display panel, so as to enter an aging mode, and before the aging mode is switched to the display mode, the method further includes: when the display processor obtains a first instruction for switching the display mode, sending a second instruction for entering the aging mode to the time schedule controller through the integrated circuit bus signal line;

The time schedule controller outputs display data signals corresponding to a preset aging mode picture to the display panel so as to enter an aging mode, and switches the display mode in the aging mode, and the time schedule controller comprises the following steps: and the time schedule controller responds to the second instruction, outputs a display data signal corresponding to the aging mode picture to the display panel so as to enter the aging mode, and switches the display mode in the aging mode.

the time schedule controller outputs display data signals corresponding to a preset aging mode picture to the display panel so as to enter an aging mode, and before switching the display mode in the aging mode, the method further comprises the following steps: when the display processor obtains a first instruction for switching the display mode, sending a second instruction for entering the aging mode to the time sequence controller through the third input/output port;

Optionally, the timing controller outputs a display data signal corresponding to a preset aging mode picture to the display panel, so as to enter an aging mode, and performs switching of the display mode in the aging mode, including: when the time schedule controller determines that the size and the pixel arrangement mode of each pattern area meet the first switching condition, outputting display data signals corresponding to the aging mode picture to the display panel so as to enter the aging mode, and switching from the current first display mode to the second display mode in the aging mode;

the method further comprises the steps of: after the display processor obtains a first instruction for switching the display mode, the backlight module is controlled to be closed;

And the time schedule controller switches the display modes under the condition that the backlight module is closed.

Optionally, the method further comprises: when the display processor meets the starting condition of the backlight module, controlling the backlight module to be started;

The method further comprises the steps of: the display processor sends display data of a pixel row corresponding to a target clock signal to the time sequence controller after sending the switching trigger signal to the time sequence controller; the time schedule controller responds to the switching trigger signal, adjusts each clock signal in the clock signal group to be synchronously driven with a target clock signal, and outputs display data of a pixel row corresponding to the target clock signal; or alternatively

The method further comprises the steps of: the display processor sends the display data of each pixel row to the time sequence controller after sending the switching trigger signal to the time sequence controller; the time schedule controller responds to the switching trigger signal, adjusts each clock signal in the clock signal group to be synchronously driven with a target clock signal, and outputs display data of a pixel row corresponding to the target clock signal;

the method further comprises the steps of: the display processor sends the display data of each pixel row to the time sequence controller after sending the switching trigger signal to the time sequence controller;

The timing controller adjusts the respective clock signals to be sequentially driven in response to the switching trigger signal, and outputs the display data of each pixel row.

It should be noted that, the specific implementation manner of each step in the present embodiment may refer to the related content in the first embodiment, and this embodiment is not described herein again.

Example III

The embodiment of the invention also discloses a display device comprising the display mode switching system.

Fig. 9 shows a block diagram of a display device according to a third embodiment of the present invention, where the display device 1000 further includes a display panel 130 and a backlight module 140, the display panel 130 is connected to the timing controller 120 in the display mode switching system 100, and the backlight module 140 is connected to the display processor 110 in the display mode switching system 100.

For the foregoing method embodiments, for simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will appreciate that the present invention is not limited by the order of acts, as some steps may, in accordance with the present invention, occur in other orders or concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The system, the method and the display device for switching the display mode provided by the invention are described in detail, and specific examples are applied to the explanation of the principle and the implementation of the invention, and the explanation of the above examples is only used for helping to understand the method and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. A display mode switching system, characterized by being applied to a display device, the system comprising a display processor and a timing controller connected;

the time sequence controller is configured to respond to the switching trigger signal and adjust the time sequence of a clock signal so as to realize the switching of a display mode;

the first instruction is specifically configured to switch from a first display mode to a second display mode, where a refresh frequency of the second display mode is higher than a refresh frequency of the first display mode, and a resolution of the second display mode is lower than a resolution of the first display mode; in the first display mode, each of the clock signals is sequentially driven;

the display processor is further configured to send display data of a pixel row corresponding to a target clock signal to the timing controller after sending the switching trigger signal to the timing controller;

The time sequence controller is specifically configured to respond to the switching trigger signal, adjust each clock signal in the clock signal group to be synchronously driven with a target clock signal, and output display data of a pixel row corresponding to the target clock signal; or alternatively

2. The system of claim 1, wherein a target line is provided between the display processor and the timing controller;

3. The system of claim 2, wherein the display processor includes a first display data signal interface, the timing controller includes a second display data signal interface, the first display data signal interface is connected to the second display data signal interface, a signal line between the first display data signal interface and the second display data signal interface includes an integrated circuit bus signal line, and the target line is the integrated circuit bus signal line;

4. The system of claim 2, wherein the display processor includes a first input-output port, the timing controller includes a second input-output port, and the target line is a connection line between the first input-output port and the second input-output port;

5. The system of claim 2, wherein the display processor comprises a first display data signal interface, the timing controller comprises a second display data signal interface, the first display data signal interface is connected to the second display data signal interface, a signal line between the first display data signal interface and the second display data signal interface comprises a display data signal line, and the target line is the display data signal line;

6. The system of claim 5, wherein the switching trigger signal is a target display data signal corresponding to a preset frame, the preset frame including at least one pattern area;

The time schedule controller is specifically configured to determine the size and the pixel arrangement mode of each pattern area according to the target display data signals; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to the second display mode;

when the size and the pixel arrangement mode of each pattern area are determined to meet a second switching condition, switching from the current second display mode to the first display mode;

7. The system of any one of claims 1-6, wherein the timing controller is further configured to output a display data signal corresponding to a preset aging mode picture to the display panel to enter an aging mode, and switch the display mode in the aging mode.

8. The system of claim 7, wherein the display processor is specifically configured to send a second instruction to the timing controller to enter the burn-in mode via an integrated circuit bus signal line when a first instruction to switch display modes is obtained;

9. The system of claim 7, wherein the display processor further comprises a third input-output port, the timing controller further comprising a fourth input-output port, the third input-output port being connected to the fourth input-output port;

10. The system of claim 7, wherein the timing controller is specifically configured to output a display data signal corresponding to the aging mode picture to the display panel to enter the aging mode when it is determined that the size and the pixel arrangement of each pattern area satisfy a first switching condition, and switch from a current first display mode to a second display mode in the aging mode;

11. The system of claim 1, wherein the display device further comprises a backlight module, the backlight module being coupled to the display processor;

12. The system of claim 11, wherein the display processor is further configured to control the backlight module to be turned on when an on condition of the backlight module is satisfied;

wherein, the starting condition of the backlight module comprises: the display processor receives a third instruction which is sent by the time sequence controller after the display mode is switched and is used for starting the backlight module;

Or the display processor achieves a preset time length after closing the backlight module, wherein the preset time length is longer than the time length required by the time sequence controller for switching the display modes.

13. The system of claim 1, wherein the display processor comprises a system-on-chip.

14. A display mode switching system, characterized by being applied to a display device, the system comprising a display processor and a timing controller connected;

The first instruction is specifically configured to switch from a second display mode to a first display mode, where a refresh frequency of the second display mode is higher than a refresh frequency of the first display mode, and a resolution of the second display mode is lower than a resolution of the first display mode;

15. A display mode switching method applied to the display mode switching system according to any one of claims 1 to 13 or to the display mode switching system according to claim 14, the method comprising:

16. A display device comprising the display mode switching system according to any one of claims 1 to 13 or comprising the display mode switching system according to claim 14.

17. The display device of claim 16, further comprising a display panel and a backlight module, wherein the display panel is coupled to the timing controller in the display mode switching system, and wherein the backlight module is coupled to the display processor in the display mode switching system.