CN113594255A - Groove type MOSFET device and preparation method thereof - Google Patents
Groove type MOSFET device and preparation method thereof Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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Abstract
本发明公开了一种沟槽型MOSFET器件及其制备方法，该器件在外延层设置有沟槽，在沟槽内填充多晶硅，在多晶硅和沟槽之间设置有厚氧化层和薄氧化层，在对应薄氧化层的沟槽上端周围的外延层上设置有Pbody基区；在厚氧化层对应的外延层处设置有N+区层；在Pbody基区上方靠近沟槽的地方设置有N+源区，在沟槽的上方设置有绝缘介质层，在绝缘介质层和外延层上方设置有源金属层，在绝缘介质层上设置有接触孔，所述接触孔将接源金属层分别与N+源区和Pbody基区相连接，所述接触孔内设置有金属。本发明通过采用深沟槽和沟槽下部分的厚氧化层，提高了相同外延参数下器件的耐压，可以用更低电阻率的外延，从而优化了导通电阻Ron。
The invention discloses a trench type MOSFET device and a preparation method thereof. The device is provided with a trench in an epitaxial layer, filled with polysilicon in the trench, and is provided with a thick oxide layer and a thin oxide layer between the polysilicon and the trench, A Pbody base region is arranged on the epitaxial layer around the upper end of the trench corresponding to the thin oxide layer; an N+ region layer is arranged at the epitaxial layer corresponding to the thick oxide layer; an N+ source region is arranged above the Pbody base region near the trench , an insulating medium layer is arranged above the trench, an active metal layer is arranged above the insulating medium layer and the epitaxial layer, and a contact hole is arranged on the insulating medium layer, and the contact hole connects the source metal layer to the N+ source region respectively. It is connected with the base area of the Pbody, and metal is arranged in the contact hole. The invention improves the withstand voltage of the device under the same epitaxy parameters by using the deep trench and the thick oxide layer at the lower part of the trench, and can use epitaxy with lower resistivity, thereby optimizing the on-resistance Ron.
Description
Technical Field
The invention relates to a groove type MOSFET device and a preparation method thereof, belonging to the technical field of semiconductor power devices.
Background
Due to the existence of the JEFET region and process limitation, the cell size of the traditional planar VDMOS cannot be made very small, the power density of a planar VDMOS device is limited, the cell size of a groove type MOSFET can be made smaller due to the vertical conduction characteristic of the groove type MOSFET, the JEFET region is eliminated, the groove type MOSFET has the advantages of high power density, small on-resistance and the like, and a groove type MOSFET structure is generally purchased for power MOSFET devices with the withstand voltage of less than 100V.
A groove of the groove MOSFET is vertical to the surface of the wafer and is positioned in the epitaxial layer, the polycrystal is positioned in the groove, the polycrystal and the epitaxy are isolated through silicon dioxide, and the groove structure penetrates through the N + source electrode area, the Pbody body area and the N-drift area. When the positive voltage applied to the grid electrode is larger than the threshold voltage, an inversion layer can be formed on the surface of the grid oxide layer to form a channel, and when the positive voltage is applied to the D level and the S pole is connected with zero voltage, current flows through the MOSFET from the channel to be conducted. When the drain is connected with positive voltage and the source and the grid are connected with zero voltage, the P-type region and the N-drift region of the device bear withstand voltage, and the MOSFET is cut off. The medium and low voltage MOSFET is not high in requirement on withstand voltage, but high in requirement on conduction loss, and the medium and low voltage MOSFET device is required to have low internal resistance and can pass large current. Therefore, the on-resistance of the MOSFET in the middle and low voltage fields is an important measure for the MOSFET.
For trench MOSFETs, the channel resistance Rch is reduced, primarily by optimizing the cell size to increase the channel density. Although the overall on-resistance of the conventional trench MOSFET is reduced, the increase of the channel density can only reduce the channel resistance, and the resistance of the drift region cannot be continuously optimized, so that the space for further optimizing the on-resistance of the conventional trench MOSFET becomes more and more limited along with the process limitation of the continuous reduction of the cell size.
Disclosure of Invention
In order to solve the problems, the invention provides a trench MOSFET device and a preparation method thereof, which can reduce the resistance of a drift region by using lower resistivity epitaxy, so that the on-resistance of the trench MOSFET is reduced.
The technical scheme adopted for solving the technical problems is as follows:
in a first aspect, a trench MOSFET device provided in an embodiment of the present invention includes a drain region, a semiconductor substrate, and an epitaxial layer, where the epitaxial layer is provided with a trench, the trench is filled with polysilicon, an oxide layer is disposed between the polysilicon and the trench, a Pbody base region is disposed on the epitaxial layer around an upper end of the trench, and a thickness of a portion of the oxide layer corresponding to the Pbody base region is smaller than a thickness of a portion of the oxide layer corresponding to a lower portion of the Pbody base region; an N + region layer is arranged at the epitaxial layer corresponding to the oxide layer at the lower part of the Pbody base region; an N + source region is arranged above the Pbody base region and close to the groove, an insulating medium layer is arranged above the groove, an active metal layer is arranged above the insulating medium layer and the epitaxial layer, a contact hole is formed in the insulating medium layer, the contact hole is used for connecting the source metal layer with the N + source region and the Pbody base region respectively, and metal is arranged in the contact hole.
As a possible implementation manner of this embodiment, the area of the lower surface of the insulating dielectric layer is at least larger than the cross-sectional area of the trench.
As a possible implementation manner of this embodiment, the cross-sectional area of the portion of the polysilicon corresponding to the Pbody base region is larger than the cross-sectional area of the polysilicon corresponding to the portion below the Pbody base region.
As a possible implementation manner of this embodiment, the side surfaces of the trench are vertical, and the bottom is rounded.
As a possible implementation manner of this embodiment, the thickness of the N + region layer is not greater than 0.1 um.
As a possible implementation manner of the embodiment, a thin oxide layer with the thickness of 400-800A is adopted as a gate oxide layer in an oxide layer arranged in a trench in the depth of the Pbody base region; the oxide layer in the trench below the depth of Pbody uses a thick oxide layer with a thickness greater than the thin oxide layer. In a second aspect, a method for manufacturing a trench MOSFET device according to an embodiment of the present invention includes the following steps:
etching a groove with an upward opening on the epitaxial layer;
injecting As ions into the side wall of the groove according to an angle of 3-7 degrees to form an N + region layer of the side wall of the groove;
forming a thick oxide layer on the inner wall of the trench by a thermal oxidation method;
depositing grid polysilicon in the groove after the thick oxide layer is formed;
etching the polysilicon to remove the upper polysilicon in the trench;
etching the thick oxide layer outwards at the position where the polycrystalline silicon is etched to form a gate oxide layer;
depositing polysilicon again;
injecting boron atoms into the top of the epitaxial layer to form a Pbody base region;
injecting As ions into the Pbody base region close to the top of the trench to form an N + source region;
forming an insulating medium layer above the polycrystalline silicon layer and the N + source region;
opening a contact hole at the position of the N + source region, which is far away from the groove, and depositing contact metal;
and depositing metal on the uppermost layer to form a source metal layer.
As a possible implementation manner of this embodiment, before etching a trench with an upward opening on the epitaxial layer, the method further includes:
depositing silicon nitride on the upper surface of the epitaxial layer to form a masking oxide layer;
after etching a trench with an upward opening in the epitaxial layer, the method further comprises:
and (5) dry etching the silicon nitride until the silicon nitride is completely etched, namely stripping the masking oxide layer.
As a possible implementation manner of this embodiment, the horizontal cross-sectional area of the insulating medium layer is the same as the horizontal cross-sectional area of the source metal layer.
As a possible implementation manner of this embodiment, during the process of etching a trench with an upward opening on the epitaxial layer, the bottom of the trench is rounded.
The technical scheme of the embodiment of the invention has the following beneficial effects:
according to the invention, the deep groove and the thick oxide layer at the lower part of the groove are adopted, so that the withstand voltage of the device under the same epitaxial parameters is improved; compared with the MOSFET device with the same voltage resistance, the structure can use epitaxy with lower resistivity, thereby optimizing the on-resistance Ron.
According to the invention, the N + region layers are doped on the two sides of the thick oxide layer of the deep trench, so that the electron mobility on the surface of the thick oxide layer is improved, and the on-resistance of the device is further optimized. The on-resistance is used as an important parameter for evaluating the middle-low voltage power MOSFET device, and the optimization of the on-resistance improves the power density of the MOSFET, thereby reducing the cost of the device and generating economic benefit.
Description of the drawings:
fig. 1 is a schematic cross-sectional view of a trench MOSFET device according to an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating a method of forming a thick oxide layer on the inner walls of a trench and etching a trench with an upward opening by thermal oxidation in accordance with an exemplary embodiment;
FIG. 3 is a schematic illustration showing after forming an N + region layer of trench sidewalls and stripping the hard mask, in accordance with an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating the deposition of gate polysilicon within a trench after the formation of a thick oxide layer in accordance with one illustrative embodiment;
figure 5 is a schematic diagram illustrating a process after forming a gate oxide layer in accordance with one illustrative embodiment;
FIG. 6 is a schematic diagram illustrating an N + source region in accordance with an exemplary embodiment;
fig. 7 is a schematic diagram illustrating a source metal layer after formation, according to an example embodiment.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
in order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
Example 1
Fig. 1 is a schematic cross-sectional view of a trench MOSFET device according to an exemplary embodiment. As shown in fig. 1, a trench MOSFET device according to an embodiment of the present invention includes a drain region 1, a semiconductor substrate 2, and an epitaxial layer 3, where the epitaxial layer is provided with a trench 4, the trench is filled with polysilicon 5, oxide layers 61 and 62 are disposed between the polysilicon 5 and the trench 4, a Pbody base region 7 is disposed on the epitaxial layer 3 around an upper end of the trench 4, and a thickness of a portion of the oxide layer corresponding to the Pbody base region (i.e., a thin oxide layer 62) is smaller than a thickness of a portion of the oxide layer corresponding to a lower portion of the Pbody base region (i.e., a thick oxide layer 61); an N + region layer 11 is arranged at the epitaxial layer corresponding to the oxide layer at the lower part of the Pbody base region; an N + source region 8 is arranged above the Pbody base region 7 and close to the groove, an insulating medium layer 9 is arranged above the groove, an active metal layer 10 is arranged above the insulating medium layer and the epitaxial layer, a contact hole (not shown in figure 1) is arranged on the insulating medium layer, the contact hole connects the active metal layer 10 with the N + source region 8 and the Pbody base region 7 respectively, and metal is arranged in the contact hole.
As a possible implementation manner of this embodiment, the area of the lower surface of the insulating medium layer 9 is at least larger than the cross-sectional area of the trench 4.
As a possible implementation manner of this embodiment, the lower surface of the insulating dielectric layer 9 covers the entire device and is located below the source metal layer 10. Namely: the horizontal cross-sectional area of the insulating medium layer is the same as that of the source metal layer. The insulating medium layer 9 is arranged on the device in a full-coverage mode, so that the process is simpler.
As a possible implementation manner of this embodiment, the cross-sectional area of the portion of the polysilicon 5 corresponding to the Pbody base region 7 is larger than the cross-sectional area of the polysilicon 5 corresponding to the portion below the Pbody base region 7.
As a possible implementation manner of this embodiment, the thickness of the N + region layer is not greater than 0.1 um. When positive voltage larger than threshold is applied to the gate, the device is conducted, and an accumulation layer is formed on the surface of the deep trench thick oxide layer in the N-region due to the positive voltage applied to the gate, the on-resistance of the area can be reduced, but the similar deep groove thick oxide layer ensures that the oxide layer can bear high voltage when the reverse bias is carried out, but when the device is conducted, because the oxide layer is thicker, the electron mobility of the accumulation layer on the surface of the oxide layer is not higher than that of the thin oxide layer, so that the optimization effect of the resistance of the drift region is weakened, the invention forms a thin N + region layer within 0.1um through the epitaxial layer doped outside the thick oxide layer, because the concentration of the N + region at the two sides of the oxide layer is higher than that of the N-drift region, the electron accumulation layer formed on the surface of the oxide layer has more electric charge, the electron mobility is increased, the on-resistance of the region is optimized, and the defect of low electron mobility of the accumulation layer caused by a thick oxide layer is overcome. Therefore, the N + region layer is adopted in the invention to promote the improvement of the electron mobility of the accumulation layer when the device is in forward conduction, and the resistance of the drift region can be reduced.
As a possible implementation manner of this embodiment, the side surfaces of the trench 4 are vertical, and the bottom is rounded.
As a possible implementation manner of this embodiment, the thin oxide layer 62 with a thickness of 400-800A is used as the gate oxide layer in the trench 4 in the depth of the Pbody base region; the oxide layer in the trenches below the depth of Pbody uses a thick oxide layer 61 that is thicker than the thin oxide layer.
The trench MOSFET device comprises a semiconductor substrate and an epitaxial layer, a trench structure is formed in the epitaxial layer, polycrystalline silicon is filled in the trench, silicon of the polycrystalline silicon and the epitaxial layer is isolated through dielectric layer silicon dioxide, a Pbody base region is formed in an N-epitaxial layer through doping, and an N + source region is formed in the Pbody base region through doping. The surface source metal layer and the grid metal are isolated through an ILD silicon dioxide layer (insulating dielectric layer), holes are punched in the ILD layer to connect the source metal layer and the N + source region, and the holes are punched to connect the source metal layer and the Pbody base region.
The trench type MOSFET device of the embodiment is different from the traditional trench MOSFET device in that the depth of a trench is far more than that of a Pbody base region, a thick oxidation layer is adopted in the trench which is more than the Pbody base region, a thin oxidation layer is adopted in the trench oxidation layer which is in the depth of the Pbody base region to form a gate oxidation layer, the thin oxidation layer is adopted in the gate oxidation layer to be beneficial to forming an inversion layer on the surface of the oxidation layer, the thick oxidation layer of the trench which is less than the depth of the Pbody base region is capable of bearing the potential difference between a grid and an N-drift region, and the potential difference is larger when the thick oxidation layer is closer to a substrate. The thick oxide layer thus functions just as a strong electric field.
The traditional trench MOSFET is mainly used for realizing PN junction withstand voltage through Pbody and N-when the device is reversely biased, while the deep trench adopted by the embodiment can be epitaxially depleted at the side face and the bottom of a thick oxide layer of the trench in an area with the structure below Pbody due to the potential difference between grid polysilicon and an N-drift area in an epitaxial layer, and due to the depletion caused by the deep trench, the triangular electric field distribution of the traditional common trench MOSFET is changed, so that the electric field distribution is approximately trapezoidal, and the withstand voltage of the device is improved.
The thickness of the N + region layer is only 0.1um at most, so that depletion of the device in reverse bias is not influenced, but when the device is conducted, the thickness of the accumulation layer is usually only sub-nanometer, and the N + thickness of 0.1um is enough to increase the electron quantity of the accumulation layer so as to improve mobility.
The invention improves the voltage resistance of the device under the condition that the epitaxial resistivity is not changed, thereby manufacturing the MOSFET device with the same voltage grade, and reducing the resistance of a drift region by using the epitaxy with lower resistivity, so that the on-resistance of the trench MOSFET is reduced.
Example 2
The embodiment of the invention provides a preparation method of a groove type MOSFET device, which comprises the following steps:
etching a groove with an upward opening on the epitaxial layer;
injecting As ions into the side wall of the groove according to an angle of 3-7 degrees to form an N + region layer of the side wall of the groove;
forming a thick oxide layer on the inner wall of the trench by a thermal oxidation method;
depositing grid polysilicon in the groove after the thick oxide layer is formed;
etching the polysilicon to remove the upper polysilicon in the trench;
etching the thick oxide layer outwards at the position where the polycrystalline silicon is etched to form a gate oxide layer;
depositing polysilicon again;
injecting boron atoms into the top of the epitaxial layer to form a Pbody base region;
injecting As ions into the Pbody base region close to the top of the trench to form an N + source region;
forming an insulating medium layer above the polycrystalline silicon layer and the N + source region;
opening a contact hole at the position of the N + source region, which is far away from the groove, and depositing contact metal;
and depositing metal on the uppermost layer to form a source metal layer.
The trench type MOSFET device prepared in the embodiment comprises a semiconductor substrate and an epitaxial layer, a trench structure is formed in the epitaxial layer, polycrystalline silicon is filled in the trench, silicon of the polycrystalline silicon and the epitaxial layer is isolated through dielectric layer silicon dioxide, a Pbody base region is formed in an N-epitaxial layer through doping, and an N + source region is formed in the Pbody base region through doping. The surface source metal layer and the grid metal are isolated through an ILD silicon dioxide layer (insulating dielectric layer), holes are punched in the ILD layer to connect the source metal layer and the N + source region, and the holes are punched to connect the source metal layer and the Pbody base region.
The trench type MOSFET device prepared in the embodiment is different from the traditional trench MOSFET device in that the depth of a trench is far more than that of a Pbody base region, a thick oxidation layer is adopted in the trench below the Pbody base region, a thin oxidation layer is adopted in the trench oxidation layer within the depth of the Pbody base region to form a gate oxidation layer, the thin oxidation layer is adopted in the gate oxidation layer to facilitate the formation of an inversion layer on the surface of the oxidation layer, and the thick oxidation layer of the trench below the depth of the Pbody base region bears the potential difference between a gate and an N-drift region, and the potential difference is larger when the thick oxidation layer is closer to a substrate. The thick oxide layer thus functions just as a strong electric field. The deep trench adopted by the trench type MOSFET device prepared in the embodiment can be epitaxially depleted at the side surface and the bottom of the thick oxide layer of the trench in the region with the structure below Pbody due to the potential difference between the grid polysilicon and the N-drift region in the epitaxial layer, and due to the depletion caused by the deep trench, the triangular electric field distribution of the conventional common trench MOSFET is changed, so that the electric field distribution is approximately trapezoidal, and the withstand voltage of the device is improved.
Example 3
As shown in fig. 2 to fig. 7, a method for manufacturing a trench MOSFET device according to an embodiment of the present invention includes the following steps:
depositing silicon nitride on the upper surface of the epitaxial layer to form a masking oxide layer, as shown in fig. 2;
etching a trench with an upward opening in the epitaxial layer, as shown in fig. 2;
carrying out smoothing treatment on the bottom of the groove;
injecting As ions into the side wall of the groove at an angle of 3-7 degrees to form an N + region layer of the side wall of the groove, As shown in FIG. 3;
dry etching the silicon nitride until the silicon nitride is completely etched, namely stripping the masking oxide layer, as shown in FIG. 3;
forming a thick oxide layer on the inner wall of the trench by a thermal oxidation method, as shown in fig. 4;
depositing gate polysilicon in the trench after the thick oxide layer is formed, as shown in fig. 4;
etching the polysilicon to remove the upper polysilicon in the trench, as shown in fig. 5;
etching the thick oxide layer outwards at the position where the polysilicon is etched to form a gate oxide layer, as shown in FIG. 5;
depositing polysilicon again as shown in fig. 6;
implanting boron atoms into the top of the epitaxial layer to form a Pbody base region, as shown in FIG. 6;
implanting As ions into the Pbody base region near the top of the trench to form an N + source region, As shown in FIG. 6;
forming an insulating dielectric layer above the polysilicon layer and the N + source region, as shown in fig. 7;
opening a contact hole at the position of the N + source region far away from the groove, and depositing contact metal, as shown in FIG. 7;
the metal is deposited on the uppermost layer to form a source metal layer, as shown in fig. 7.
As shown in fig. 2 and fig. 3, in this embodiment, a masking oxide layer is first formed on the surface of the epitaxial layer, and then a trench of 1.5-3 um is formed by photolithography and etching; in order to avoid electric field concentration, the bottom of the groove needs to be subjected to smoothing treatment, and then, As ions are implanted into the side wall of the groove at an angle of 3-7 degrees through an ion implantation process to form an N + region layer of the side wall of the groove. In the embodiment, the thin N + region layer within 0.1um is formed by doping the epitaxial layer outside the thick oxide layer, and because the concentration of the N + region on the two sides of the oxide layer is higher than that of the N-drift region, the charge amount of the electron accumulation layer formed on the surface of the oxide layer is more, and the electron mobility is increased, so that the on-resistance of the region is optimized, and the defect of the decrease of the electron mobility of the accumulation layer caused by the thick oxide layer is overcome. The thickness of the N + region layer is only 0.1um at most, so that depletion of the device in reverse bias is not influenced, but when the device is switched on, the thickness of the accumulation layer is usually only sub-nanometer, and the N + thickness of 0.1um is enough to increase the electron quantity of the accumulation layer so as to improve mobility.
After the trench is formed, a thick oxide layer is formed by thermal oxidation, and then 8K-12 KA (angstrom) gate polysilicon is deposited to fill the trench, as shown in fig. 4.
And etching the polycrystalline silicon on the basis of the graph 4, and removing the polycrystalline silicon on the surface, wherein the polycrystalline silicon in the groove is 1000-2000A lower than the silicon surface. And etching the thick oxide layer of the trench, wherein the distance between the surface of the thick oxide layer in the trench and the surface of the silicon surface is 0.7-1.5 um. And etching the polycrystal, and etching the oxide layer, wherein the thick oxygen at the lower part of the groove cannot be etched due to the existence of the polysilicon at the center of the groove, the oxide layer at the side wall can be etched, the etching amount of the oxide layer needs to be controlled, and the thickness of the oxide layer at the upper part of the side wall is kept at 400-800A. As a gate oxide layer, as shown in fig. 6. The trench type MOSFET device prepared in the embodiment is different from the traditional trench MOSFET device in that the depth of a trench is far more than that of a Pbody base region, a thick oxidation layer is adopted in the trench below the Pbody base region, a thin oxidation layer is adopted in the trench oxidation layer within the depth of the Pbody base region to form a gate oxidation layer, the thin oxidation layer is adopted in the gate oxidation layer to facilitate the formation of an inversion layer on the surface of the oxidation layer, and the thick oxidation layer of the trench below the depth of the Pbody base region bears the potential difference between a gate and an N-drift region, and the potential difference is larger when the thick oxidation layer is closer to a substrate. The thick oxide layer thus functions just as a strong electric field.
On the basis of FIG. 5, 5K-8K polysilicon is deposited, the trench is filled, then poly-crystal etching is carried out, the surface of the poly-crystal is lower than the surface of the silicon by 1000-2000A, and boron atom shape is injected, so that a P-type semiconductor called Pbody base region is formed on the surface of the epitaxial silicon, as shown in FIG. 6. The depth Tp of the Pbody base region ranges from 0.5 to 1.5 mu m, then ion implantation is carried out again, As ions are implanted, and an N-type semiconductor, namely an N + source region, also called As XN, is formed on the surface of epitaxial silicon measa (a silicon mesa between trenches), and the depth Tn of the XN ranges from 0.1 to 0.4 mu m.
On the structure of fig. 6, an undoped silicon glass or a phosphorus-doped borosilicate glass is covered as an insulating medium layer. In the actual processing technology, the insulating medium layer 9 is arranged on the device in a full-coverage mode, so that the technology is simpler.
Then, opening a contact hole at the position corresponding to the N + source region, wherein the size of the contact hole is 0.2-1.2 mu m; then, a contact metal is deposited in the contact hole, and finally, an Al metal is deposited on the surface of the contact metal to form a source metal layer, as shown in fig. 7.
The grid polysilicon is punched at two ends or in the middle of the strip-shaped groove by layout to be led out and connected to the grid metal.
The trench type MOSFET device prepared in the embodiment comprises a semiconductor substrate and an epitaxial layer, a trench structure is formed in the epitaxial layer, polycrystalline silicon is filled in the trench, silicon of the polycrystalline silicon and the epitaxial layer is isolated through dielectric layer silicon dioxide, a Pbody base region is formed in an N-epitaxial layer through doping, and an N + source region is formed in the Pbody base region through doping. The surface source metal layer and the gate metal are isolated by an ILD silicon dioxide layer (i.e., an insulating dielectric layer, where the horizontal cross-sectional area of the insulating dielectric layer is the same as the horizontal cross-sectional area of the source metal layer, as shown in fig. 7), holes are punched in the ILD layer to connect the source metal layer and the N + source region, and holes are punched to connect the source metal layer and the Pbody base region.
The deep trench adopted by the trench type MOSFET device prepared in the embodiment can be epitaxially depleted at the side surface and the bottom of the thick oxide layer of the trench in the region with the structure below Pbody due to the potential difference between the grid polysilicon and the N-drift region in the epitaxial layer, and due to the depletion caused by the deep trench, the triangular electric field distribution of the conventional common trench MOSFET is changed, so that the electric field distribution is approximately trapezoidal, and the withstand voltage of the device is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A trench type MOSFET device comprises a drain electrode region, a semiconductor substrate and an epitaxial layer, and is characterized in that a trench is formed in the epitaxial layer, polycrystalline silicon is filled in the trench, an oxide layer is arranged between the polycrystalline silicon and the trench, a Pbody base region is arranged on the epitaxial layer around the upper end of the trench, and the thickness of the oxide layer and the part, corresponding to the Pbody base region, of the oxide layer is smaller than that of the oxide layer and the part, corresponding to the Pbody base region, of the oxide layer and the part of the oxide layer; an N + region layer is arranged at the epitaxial layer corresponding to the oxide layer at the lower part of the Pbody base region; an N + source region is arranged above the Pbody base region and close to the groove, an insulating medium layer is arranged above the groove, an active metal layer is arranged above the insulating medium layer and the epitaxial layer, a contact hole is formed in the insulating medium layer, the contact hole is used for connecting the source metal layer with the N + source region and the Pbody base region respectively, and metal is arranged in the contact hole.
2. The trench MOSFET device of claim 1, wherein the insulating dielectric layer has a lower surface area at least greater than a cross-sectional area of the trench.
3. The trench MOSFET device of claim 1, wherein the polysilicon has a cross-sectional area corresponding to the Pbody base region that is greater than the cross-sectional area of the polysilicon corresponding to the portion of the Pbody base region below.
4. The trench MOSFET device of claim 1, wherein said trench is vertical on its sides and rounded at its bottom.
5. The trench MOSFET device of claim 1, wherein the N + region layer has a thickness of no more than 0.1 um.
6. The trench MOSFET device of any one of claims 1-5, wherein the oxide layer disposed in the trench within the depth of the Pbody base region is a thin oxide layer having a thickness of 400-800A as the gate oxide layer; the oxide layer in the trench below the depth of Pbody uses a thick oxide layer with a thickness greater than the thin oxide layer.
7. A preparation method of a groove type MOSFET device is characterized by comprising the following steps:
etching a groove with an upward opening on the epitaxial layer;
injecting As ions into the side wall of the groove according to an angle of 3-7 degrees to form an N + region layer of the side wall of the groove;
forming a thick oxide layer on the inner wall of the trench by a thermal oxidation method;
depositing grid polysilicon in the groove after the thick oxide layer is formed;
etching the polysilicon to remove the upper polysilicon in the trench;
etching the thick oxide layer outwards at the position where the polycrystalline silicon is etched to form a gate oxide layer;
depositing polysilicon again;
injecting boron atoms into the top of the epitaxial layer to form a Pbody base region;
injecting As ions into the Pbody base region close to the top of the trench to form an N + source region;
forming an insulating medium layer above the polycrystalline silicon layer and the N + source region;
opening a contact hole at the position of the N + source region, which is far away from the groove, and depositing contact metal;
and depositing metal on the uppermost layer to form a source metal layer.
8. The method of forming a trench MOSFET device as claimed in claim 7, further comprising, prior to etching a trench in the epitaxial layer having an upward opening:
depositing silicon nitride on the upper surface of the epitaxial layer to form a masking oxide layer;
after etching a trench with an upward opening in the epitaxial layer, the method further comprises:
and (5) dry etching the silicon nitride until the silicon nitride is completely etched, namely stripping the masking oxide layer.
9. The method of claim 8 wherein the insulating dielectric layer has a horizontal cross-sectional area that is the same as a horizontal cross-sectional area of the source metal layer.
10. The method of forming a trench MOSFET device as claimed in any of claims 7 to 9, wherein the bottom of the trench is rounded during etching of a trench having an upward opening in the epitaxial layer.
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