CN113568349B - Data processing method, device, terminal equipment and readable storage medium - Google Patents
Data processing method, device, terminal equipment and readable storage medium Download PDFInfo
- Publication number
- CN113568349B CN113568349B CN202110852868.4A CN202110852868A CN113568349B CN 113568349 B CN113568349 B CN 113568349B CN 202110852868 A CN202110852868 A CN 202110852868A CN 113568349 B CN113568349 B CN 113568349B
- Authority
- CN
- China
- Prior art keywords
- target
- address
- data
- preset
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Stored Programmes (AREA)
Abstract
The application is applicable to the technical field of embedded systems, and provides a data processing method, a device, terminal equipment and a readable storage medium, wherein the method comprises the following steps: acquiring a data storage request, wherein the data storage request comprises target data to be stored; and converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset idle address, wherein the preset idle address is an idle address in an interrupt vector table. The method and the device can solve the problem that the storage address of the product information is randomly allocated by the existing compiler to waste the storage space of the MCU to a certain extent.
Description
Technical Field
The application belongs to the field of embedded systems, and particularly relates to a data processing method, a data processing device, terminal equipment and a readable storage medium.
Background
With the development of scientific technology, embedded technology is widely applied to various fields such as industrial control, information home appliances, communication equipment and the like.
During embedded development, some product information, such as the version number of the product, the type of the product, the date of compilation of the product, etc., is typically saved for later recall or viewing. Currently, it is common for a compiler to randomly assign memory addresses for product information.
However, because of the memory alignment, the compiler randomly allocates memory addresses, which generates a large amount of memory fragmentation, wasting a large amount of memory space for the single chip microcomputer (Micro Controller Unit, MCU). Since the MCU has a relatively small storage space, the performance of the MCU is seriously affected by the wasted storage space of these memory fragments.
Disclosure of Invention
The embodiment of the application provides a data processing method, a device, a terminal device and a readable storage medium, which can solve the problem that the storage address of the product information is randomly allocated by a compiler to waste the storage space of an MCU to a certain extent.
In a first aspect, an embodiment of the present application provides a data processing method, including:
acquiring a data storage request, wherein the data storage request comprises target data to be stored;
and converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset free address, wherein the preset free address is a free address in an interrupt vector table.
Optionally, the target data includes constant information.
Optionally, the storing the target vector data in a storage space corresponding to a preset free address includes:
determining the size of a storage space corresponding to at least two preset idle addresses;
and storing the target vector data in a target storage space, wherein the target storage space is a storage space with a size not smaller than the size of the target vector data.
Optionally, the storing the target vector data in a storage space corresponding to a preset free address includes:
determining the type of the initial address in the preset idle address;
if the type of the initial address meets the preset alignment condition, the initial address is used as the target initial address of the target vector data;
and storing the target vector data into the storage space from the target start address.
Optionally, after determining the type of the start address in the preset free address, the method further includes:
if the type of the initial address does not accord with the preset alignment condition, sequentially determining the type of each target idle address in the preset idle addresses, wherein the target idle addresses are preset idle addresses except the initial address in the preset idle addresses;
taking a target idle address with the type meeting a preset alignment condition as a target starting address of the target vector data, and determining the size of a corresponding storage subspace between the target starting address and an ending address of the storage space;
and if the size of the storage subspace is larger than or equal to the size of the target vector data, storing the target vector data into the storage subspace from the target starting address.
Optionally, the method further comprises:
receiving a function execution instruction and acquiring an objective function corresponding to the function execution instruction;
acquiring a target storage address of target vector data from the interrupt vector table by executing a target function;
and acquiring the target vector data from a storage space corresponding to the target storage address according to a preset rule.
In a second aspect, an embodiment of the present application provides a data processing apparatus, including:
the request acquisition module is used for acquiring a data storage request, wherein the data storage request comprises target data to be stored;
the data storage module is used for converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset idle address, wherein the preset idle address is an idle address in an interrupt vector table.
In a third aspect, an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the first aspect when the processor executes the computer program.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the first aspect described above.
In a fifth aspect, embodiments of the present application provide a computer program product for causing a terminal device to perform the method of the first aspect described above when the computer program product is run on the terminal device.
It will be appreciated that the advantages of the second to fifth aspects may be found in the relevant description of the first aspect, and are not described here again.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
the application provides a data processing method, firstly, a data storage request is acquired, wherein the data storage request comprises target data to be stored. And then converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset free address, wherein the preset free address is a free address in the interrupt vector table. Since the target vector data is stored in the storage space corresponding to the preset free address, that is, the target vector data has a fixed storage space, the storage address of the target vector data is not randomly allocated any more. And no data is stored in the storage space corresponding to the free address in the interrupt vector table. Therefore, the target vector data is stored in the storage space corresponding to the preset idle address, so that other storage space in the MCU is not required to be occupied, and the storage space of the MCU can be saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a data processing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a start address and a memory space according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a target start address, an end address, and a storage subspace according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a data processing apparatus according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The data processing method provided by the embodiment of the application can be applied to terminal equipment such as mobile phones, tablet computers, notebook computers, ultra-mobile personal computer (UMPC), netbooks, personal digital assistants (personal digital assistant, PDA) and the like, and the embodiment of the application does not limit the specific types of the terminal equipment.
In order to illustrate the technical solutions described in the present application, the following description is made by specific examples.
Example 1
Referring to fig. 1, a data processing method according to a first embodiment of the present application is described below, where the method includes:
step S101, a data storage request is acquired, where the data storage request includes target data to be stored.
When the user side inputs a data storage request, the terminal device can acquire target data to be stored from the data storage request. The target data may include constant information, for example, the version number of the product, the type of the product, the date of compiling the product, and the like.
Step S102, converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset idle address, wherein the preset idle address is an idle address in an interrupt vector table.
Because some free addresses exist in the interrupt vector table in some cores, the storage spaces corresponding to the free addresses do not store data. Therefore, after the terminal device acquires the data storage request, the terminal device can convert the target data in the data storage request into target vector data and store the target vector data into a storage space corresponding to the preset idle address. Thus, there is a fixed memory space for the target vector data, and the memory address of the target vector data is no longer randomly allocated. And no data is stored in the storage space corresponding to the free address in the interrupt vector table. Therefore, the target vector data is stored in the storage space corresponding to the preset idle address, so that other storage space in the MCU is not required to be occupied, and the storage space of the MCU can be saved.
The preset free address refers to a free address in the interrupt vector table, for example, the preset free address is [0x01c,0x01f ], or the preset free address is [0x018,0x01b ].
The following explains the interrupt vector table and related concepts:
(1) Interrupt vector: the entry address of the interrupt service routine.
(2) Interrupt vector table: all interrupt type codes and the corresponding interrupt vectors in the system are stored in a region according to a certain rule, and the storage region is called an interrupt vector table.
(3) Interruption: the interrupt refers to that when the CPU is in normal execution of a program, the CPU temporarily interrupts the currently running program due to the triggering of an internal/external event or the prearrangement of the program, and the CPU is transferred to a service subroutine which is executed as an internal/external event or as an event prearranged for the program, and after the execution of the service subroutine is completed, the CPU returns to the temporarily interrupted program (breakpoint) to continue the execution of the original program, and the process becomes an interrupt. In summary, the present application provides a data processing method, first, a data storage request is obtained, where the data storage request includes target data to be stored. And then converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset free address, wherein the preset free address is a free address in the interrupt vector table. Since the target vector data is stored in the storage space corresponding to the preset free address, that is, the target vector data has a fixed storage space, the storage address of the target vector data is not randomly allocated any more. And no data is stored in the storage space corresponding to the free address in the interrupt vector table. Therefore, the target vector data is stored in the storage space corresponding to the preset idle address, so that other storage space in the MCU is not required to be occupied, and the storage space of the MCU can be saved.
In some embodiments, after the terminal device obtains the data storage request, the size of the storage space corresponding to the two preset idle addresses may be determined first, and then the target vector data is stored in the target storage space, where the target storage space is a storage space with a size not smaller than the size of the target vector data.
Specifically, the detailed procedure of storing the target vector data into the target storage space, the target storage space being a storage space having a size not smaller than the size of the target vector data, may be:
the target vector data is stored to a target storage space with the same size as the target vector data, so that the storage space corresponding to the idle address in the interrupt vector table is saved.
If there is no target storage space of the same size as the target vector data, the terminal device stores the target vector data to a target storage space of a size larger than the size of the target vector data.
In other embodiments, the process of storing the target vector data in the storage space corresponding to the preset free address may be: the terminal equipment firstly determines the type of a starting address in the preset idle address, takes the starting address as a target starting address of target vector data when the type of the starting address meets the preset alignment condition, and then stores the target vector data into the storage space according to the front-to-back sequence among the preset idle addresses from the target starting address. When the type of the initial address meets the preset alignment condition, the initial address is used as the target initial address, so that the storage space of the target vector data meets the alignment requirement, and the efficiency of accessing the storage space of the target vector data is improved.
For example, referring to fig. 2 (S in fig. 2 represents data and the data occupies 3 bytes), the target vector data occupies 2 bytes, and since the alignment is performed in 4 bytes, the type of the start address is a target start address of the target vector data, which meets the preset alignment condition, since the byte corresponding to the start address is 4 bytes.
The preset alignment condition means that the position of the byte corresponding to the target start address of the target vector data is a multiple of the preset number. For example, if the preset number is 4, the byte corresponding to the target start address may be a multiple of 4.
It should be understood that if the type of the start address does not meet the preset alignment condition, the terminal device sequentially determines the type of each target idle address in the preset idle addresses, where the target idle addresses are preset idle addresses except the start address in the preset idle addresses, and then uses the target idle addresses with the type meeting the preset alignment condition as target start addresses of the target vector data. At this time, since the target start address is not a start address of the preset free address, there is a possibility that the size of the storage subspace corresponding between the target start address and the end address of the storage space is smaller than the size of the target vector data.
Therefore, at this time, the terminal device also needs to determine the size of the storage subspace. If the size of the storage subspace is greater than or equal to the size of the target vector data, the target vector data is stored to the storage subspace starting from the target start address. If the size of the storage subspace is smaller than the size of the target vector data, the target vector data needs to be stored into a storage space corresponding to another preset free address.
For example, as shown in fig. 3 (S in fig. 3 represents data, and the data occupies 3 bytes), the target vector data occupies 2 bytes, and since the alignment is performed with 4 bytes, the byte corresponding to the start address is 3 bytes, and thus the type of the start address is not in accordance with the preset alignment condition. At this time, the type of the target idle address corresponding to 4 bytes is firstly determined, and if the type of the target idle address corresponding to 4 bytes is in accordance with the preset alignment condition, the target idle address corresponding to 4 bytes is used as the target starting address. At this time, it is no longer necessary to judge the type of the target free address at the rear. If the type of the target idle address corresponding to the 4 bytes is not in accordance with the preset alignment condition, the type of the target idle address corresponding to the 5 bytes is required to be judged again until the target idle address with the type in accordance with the preset alignment condition is found.
It should be noted that, after storing the target vector data in the storage space corresponding to the free address in the interrupt vector table, the terminal device associates the identifier of the target vector data with the storage address of the target vector data in the interrupt vector table, so that the storage address of the target vector data can be searched from the interrupt vector table later.
Furthermore, the method comprises the following steps: and receiving a function execution instruction and acquiring an objective function corresponding to the function execution instruction. The target memory address of the target vector data is then obtained from the interrupt vector table by executing the target function. And finally, acquiring target vector data from a storage space corresponding to the target storage address according to a preset rule. Illustratively, the specific procedure for obtaining the target storage address of the target vector data from the interrupt vector table by executing the target function may be: the terminal equipment starts to offset from the preset first address of the interrupt vector table according to the preset number or the offset of the integer multiple of the preset number until the target storage address corresponding to the identification of the target vector data is obtained, and finally obtains the target vector data according to the storage space corresponding to the target storage address.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
Example two
Fig. 4 shows an example of a data processing apparatus, and for convenience of explanation, only parts relevant to the embodiments of the present application are shown. The apparatus 400 includes:
the request acquisition module 401 is configured to acquire a data storage request, where the data storage request includes target data to be stored.
The data storage module 402 is configured to convert target data into target vector data, and store the target vector data into a storage space corresponding to a preset free address, where the preset free address is a free address in the interrupt vector table.
Optionally, the target data includes constant information.
Optionally, the data storage module 402 is configured to perform:
determining the size of a storage space corresponding to at least two preset idle addresses;
and storing the target vector data into a target storage space, wherein the target storage space is a storage space with the size not smaller than the size of the target vector data.
Optionally, the data storage module 402 is configured to perform:
determining the type of a starting address in a preset idle address;
if the type of the initial address meets the preset alignment condition, the initial address is used as a target initial address of the target vector data;
the target vector data is stored into the memory space starting from the target start address.
Optionally, the data storage module 402 is configured to perform:
if the type of the initial address does not accord with the preset alignment condition, sequentially determining the type of each target idle address in the preset idle addresses, wherein the target idle addresses are preset idle addresses except the initial address in the preset idle addresses;
taking a target idle address with the type meeting a preset alignment condition as a target starting address of target vector data, and determining the size of a corresponding storage subspace between the target starting address and an ending address of the storage space;
and if the size of the storage subspace is larger than or equal to the size of the target vector data, storing the target vector data into the storage subspace from the target starting address.
Optionally, the request acquisition module 401 is further configured to perform:
receiving a function execution instruction and acquiring an objective function corresponding to the function execution instruction;
acquiring a target storage address of target vector data from the interrupt vector table by executing a target function;
and acquiring target vector data from a storage space corresponding to the target storage address according to a preset rule.
It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the embodiment of the method of the present application, specific functions and technical effects thereof may be referred to a part of the embodiment of the method, and will not be described herein again.
Example III
Fig. 5 is a schematic diagram of a terminal device provided in a third embodiment of the present application. As shown in fig. 5, the terminal device 500 of this embodiment includes: a processor 501, a memory 502 and a computer program 503 stored in the memory 502 and executable on the processor 501. The steps of the various method embodiments described above are implemented when the processor 501 executes the computer program 503. Alternatively, the processor 501, when executing the computer program 503, performs the functions of the modules/units in the above-described apparatus embodiments.
Illustratively, the computer program 503 may be split into one or more modules/units that are stored in the memory 502 and executed by the processor 501 to complete the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions for describing the execution of the computer program 503 in the terminal device 500. For example, the computer program 503 may be divided into a request acquisition module and a data storage module, where each module specifically functions as follows:
acquiring a data storage request, wherein the data storage request comprises target data to be stored;
converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset idle address, wherein the preset idle address is an idle address in an interrupt vector table.
The terminal device may include, but is not limited to, a processor 501, a memory 502. It will be appreciated by those skilled in the art that fig. 5 is merely an example of a terminal device 500 and is not limiting of the terminal device 500, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the terminal device may further include an input-output device, a network access device, a bus, etc.
The processor 501 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 502 may be an internal storage unit of the terminal device 500, for example, a hard disk or a memory of the terminal device 500. The memory 502 may be an external storage device of the terminal device 500, for example, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided in the terminal device 500. Further, the memory 502 may also include both an internal storage unit and an external storage device of the terminal device 500. The memory 502 is used for storing the computer program and other programs and data required for the terminal device. The memory 502 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units described above is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or plug-ins may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of each of the above-described method embodiments, or may be implemented by a computer program to instruct related hardware, where the above-described computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the above-described method embodiments. The computer program comprises computer program code, and the computer program code can be in a source code form, an object code form, an executable file or some intermediate form and the like. The computer readable medium may include: any entity or device capable of carrying the computer program code described above, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the content of the computer readable medium described above can be appropriately increased or decreased according to the requirements of the jurisdiction's legislation and the patent practice, for example, in some jurisdictions, the computer readable medium does not include electrical carrier signals and telecommunication signals according to the legislation and the patent practice.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (9)
1. A method of data processing, comprising:
acquiring a data storage request, wherein the data storage request comprises target data to be stored;
converting the target data into target vector data, and storing the target vector data into a storage space corresponding to a preset idle address, wherein the preset idle address is an idle address in an interrupt vector table;
associating an identification of the target vector data with a storage address of the target vector data in the interrupt vector table;
receiving a function execution instruction and acquiring an objective function corresponding to the function execution instruction;
shifting from a preset first address of the interrupt vector table according to a preset number or an offset which is an integer multiple of the preset number until a target storage address corresponding to the identification of the target vector data is obtained;
and acquiring the target vector data from a storage space corresponding to the target storage address according to a preset rule.
2. The data processing method of claim 1, wherein the target data includes constant information.
3. The data processing method according to claim 1, wherein storing the target vector data in a storage space corresponding to a preset free address includes:
determining the size of a storage space corresponding to at least two preset idle addresses;
and storing the target vector data into a target storage space, wherein the target storage space is a storage space with the size not smaller than the size of the target vector data.
4. The data processing method according to claim 1, wherein storing the target vector data in a memory space corresponding to a preset free address includes:
determining the type of a starting address in the preset idle address;
if the type of the initial address meets a preset alignment condition, the initial address is used as a target initial address of the target vector data;
and storing the target vector data to the storage space from the target starting address.
5. The data processing method of claim 4, further comprising, after said determining the type of the start address in the preset free address:
if the type of the initial address does not accord with a preset alignment condition, sequentially determining the type of each target idle address in the preset idle addresses, wherein the target idle addresses are preset idle addresses except the initial address in the preset idle addresses;
taking a target idle address with the type meeting a preset alignment condition as a target starting address of the target vector data, and determining the size of a corresponding storage subspace between the target starting address and an ending address of the storage space;
and if the size of the storage subspace is larger than or equal to the size of the target vector data, storing the target vector data into the storage subspace from the target starting address.
6. A data processing apparatus, comprising:
the request acquisition module is used for acquiring a data storage request, wherein the data storage request comprises target data to be stored;
the data storage module is used for converting the target data into target vector data, storing the target vector data into a storage space corresponding to a preset idle address, wherein the preset idle address is an idle address in an interrupt vector table, and associating the identification of the target vector data with the storage address of the target vector data in the interrupt vector table;
the request acquisition module is further configured to perform:
receiving a function execution instruction and acquiring an objective function corresponding to the function execution instruction;
shifting from a preset first address of the interrupt vector table according to a preset number or an offset which is an integer multiple of the preset number until a target storage address corresponding to the identification of the target vector data is obtained;
and acquiring the target vector data from a storage space corresponding to the target storage address according to a preset rule.
7. The data processing apparatus of claim 6, wherein the target data includes constant information.
8. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1-5 when executing the computer program.
9. A computer readable storage medium storing a computer program, which when executed by a processor implements the method according to any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110852868.4A CN113568349B (en) | 2021-07-27 | 2021-07-27 | Data processing method, device, terminal equipment and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110852868.4A CN113568349B (en) | 2021-07-27 | 2021-07-27 | Data processing method, device, terminal equipment and readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113568349A CN113568349A (en) | 2021-10-29 |
| CN113568349B true CN113568349B (en) | 2023-05-02 |
Family
ID=78168095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110852868.4A Active CN113568349B (en) | 2021-07-27 | 2021-07-27 | Data processing method, device, terminal equipment and readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113568349B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05265846A (en) * | 1992-03-18 | 1993-10-15 | Fujitsu Ltd | Memory managing system |
| JP2011191865A (en) * | 2010-03-12 | 2011-09-29 | Renesas Electronics Corp | Semiconductor device |
| CN108694684A (en) * | 2017-04-01 | 2018-10-23 | 英特尔公司 | Shared local storage piecemeal mechanism |
| CN110162328A (en) * | 2019-05-28 | 2019-08-23 | 东信和平科技股份有限公司 | A kind of smart card operating system upgrade method and device |
| CN111708715A (en) * | 2020-06-17 | 2020-09-25 | Oppo广东移动通信有限公司 | Memory allocation method, memory allocation device and terminal equipment |
| CN111782368A (en) * | 2020-06-30 | 2020-10-16 | 珠海全志科技股份有限公司 | Interrupt nesting processing method, device, terminal and storage medium |
| CN112198820A (en) * | 2020-09-27 | 2021-01-08 | 中国第一汽车股份有限公司 | Interrupt service implementation method, device, equipment and storage medium |
| CN112346739A (en) * | 2019-08-06 | 2021-02-09 | 珠海格力电器股份有限公司 | Remapping method and device of interrupt vector table, microprocessor and electronic device |
| CN113111001A (en) * | 2021-04-29 | 2021-07-13 | 苏州大学 | Remote software debugging method for embedded terminal |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7849287B2 (en) * | 2006-11-13 | 2010-12-07 | Advanced Micro Devices, Inc. | Efficiently controlling special memory mapped system accesses |
| US8291202B2 (en) * | 2008-08-08 | 2012-10-16 | Qualcomm Incorporated | Apparatus and methods for speculative interrupt vector prefetching |
-
2021
- 2021-07-27 CN CN202110852868.4A patent/CN113568349B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05265846A (en) * | 1992-03-18 | 1993-10-15 | Fujitsu Ltd | Memory managing system |
| JP2011191865A (en) * | 2010-03-12 | 2011-09-29 | Renesas Electronics Corp | Semiconductor device |
| CN108694684A (en) * | 2017-04-01 | 2018-10-23 | 英特尔公司 | Shared local storage piecemeal mechanism |
| CN110162328A (en) * | 2019-05-28 | 2019-08-23 | 东信和平科技股份有限公司 | A kind of smart card operating system upgrade method and device |
| CN112346739A (en) * | 2019-08-06 | 2021-02-09 | 珠海格力电器股份有限公司 | Remapping method and device of interrupt vector table, microprocessor and electronic device |
| CN111708715A (en) * | 2020-06-17 | 2020-09-25 | Oppo广东移动通信有限公司 | Memory allocation method, memory allocation device and terminal equipment |
| CN111782368A (en) * | 2020-06-30 | 2020-10-16 | 珠海全志科技股份有限公司 | Interrupt nesting processing method, device, terminal and storage medium |
| CN112198820A (en) * | 2020-09-27 | 2021-01-08 | 中国第一汽车股份有限公司 | Interrupt service implementation method, device, equipment and storage medium |
| CN113111001A (en) * | 2021-04-29 | 2021-07-13 | 苏州大学 | Remote software debugging method for embedded terminal |
Non-Patent Citations (3)
| Title |
|---|
| 吴炜荣 ; 梁阿磊 ; 王刚 ; .ARM向量中断机制在uClinux下的设计与实现.微型电脑应用.2006,(第03期),全文. * |
| 周筱羽 ; 顾斌 ; 赵建华 ; 杨孟飞 ; .中断驱动控制系统的有界模型检验技术.软件学报.2015,(第10期),全文. * |
| 郑连清 ; 余红欣 ; 刘和平 ; 周念成 ; .终端设备远程下载程序的实现方法.电测与仪表.2006,(第02期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113568349A (en) | 2021-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102200923B (en) | Method of booting host device from MMC/SD device and associated devices | |
| CN112631657B (en) | Byte comparison method for character string processing and instruction processing device | |
| WO2018040270A1 (en) | Method and device for loading linux-system elf file in windows system | |
| CN111694589B (en) | Upgrade package generation method, device, server and computer readable storage medium | |
| CN111767056B (en) | Source code compiling method, executable file running method and terminal equipment | |
| CN112506569B (en) | Byte code executing method, byte code executing device and terminal equipment | |
| US8463972B2 (en) | System and method for dynamic, local retriggered interrupt routing discovery | |
| CN112199272B (en) | Intelligent terminal testing method and device, terminal equipment and medium | |
| CN113568349B (en) | Data processing method, device, terminal equipment and readable storage medium | |
| CN111708715B (en) | Memory allocation method, memory allocation device and terminal equipment | |
| US6349388B1 (en) | Timer processing engine for supporting multiple virtual minimum time timers | |
| CN112799763A (en) | Function management method, management device, terminal equipment and readable storage medium | |
| CN109324838B (en) | Execution method and execution device of single chip microcomputer program and terminal | |
| CN113760810B (en) | Information processing method, information processing device, equipment and storage medium | |
| CN114490074B (en) | Arbitration system, arbitration method, electronic device, storage medium and chip | |
| CN111679909B (en) | Data processing method and device and terminal equipment | |
| CN112673354B (en) | System state detection method, system state device and terminal equipment | |
| CN112445390B (en) | Submenu selection method and device and terminal equipment | |
| CN118312243B (en) | EBPF unloading method of intelligent network card, programmable RSS (really simple syndication) method and device based on eBPF unloading | |
| CN118394351B (en) | Intelligent contract compiling method and device, terminal equipment and storage medium | |
| CN115883645B (en) | Communication configuration method, electronic device and storage medium | |
| CN112612754B (en) | File searching method, system, device and computer storage medium | |
| US10521374B2 (en) | Semiconductor integrated circuit device and method for comparing data | |
| US7512143B2 (en) | Buffer management for a target channel adapter | |
| CN117687633A (en) | Executable file generation method and device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |