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CN113555439B - 共源共栅单元 - Google Patents

共源共栅单元 Download PDF

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Publication number
CN113555439B
CN113555439B CN202110325591.XA CN202110325591A CN113555439B CN 113555439 B CN113555439 B CN 113555439B CN 202110325591 A CN202110325591 A CN 202110325591A CN 113555439 B CN113555439 B CN 113555439B
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fet
common
region
source
gate
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CN113555439A (zh
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李文君
C·珀金斯闫
T·埃西拉詹
C·E·泽姆克
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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Abstract

本公开涉及半导体结构，更具体地涉及具有电阻和电容优化的一体式共源共栅单元及制造方法。该结构包括：位于单个公共半导体区域的第一部分中的共源极FET(CS‑FET)，所述CS‑FET包括源极区和漏极区；位于单个公共半导体区域的第二部分中的共栅极FET(CG‑FET)，所述CG‑FET包括源极区和漏极区；以及单个公共半导体区域的掺杂连接区域，其连接CS‑FET的漏极与CG‑FET的源极。

Description

共源共栅单元
技术领域
本公开涉及半导体结构，更具体地涉及一体式共源共栅单元(unitary Cascodecell)及制造方法。
背景技术
半导体器件中使用共源共栅单元来形成具有优异的输入/输出隔离和高带宽特性的共源共栅放大器电路。典型地使用彼此连接的两个场效应晶体管(FET)，具体地，输入共源极FET(CS-FET)和输出共栅极FET(CG-FET)，来构造共源共栅放大器。特别地，CS-FET的栅极接收RF输入信号，CS-FET的漏极连接到CG-FET的源极，并且共源共栅放大器的输出从CG-FET的漏极提供。CS-FET和CG-FET耦接到其他电路元件(包括电阻器、电感器和电容器)以构成完整的共源共栅放大器电路。
在常规的共源共栅放大器中，CS-FET和CG-FET形成在彼此分离的单元(例如，衬底中的分离的岛)中，或者形成在分离的衬底中。无论哪种情况，CS-FET的漏极都通过金属化层连接到其相应CG-FET的源极，该金属化层例如为位于其中分别形成有CS-FET和CG-FET的分离的岛区域或分离的衬底之间的中段制程(MOL)金属化层或后段制程(BEOL)金属化层。用于连接CS-FET和CG-FET的金属化层会产生额外的电阻(例如，气刨电阻(gougingresistance)和金属电阻)和额外的电容(例如，寄生电容)，这倾向于恶化共源共栅放大器的增益和线性度。
发明内容
在本公开的一方面，一种结构包括：位于单个公共半导体区域的第一部分中的共源极FET(CS-FET)，所述CS-FET包括源极区和漏极区；位于所述单个公共半导体区域的第二部分中的共栅极FET(CG-FET)，所述CG-FET包括源极区和漏极区；以及所述单个公共半导体区域的掺杂连接区域，其连接所述CS-FET的漏极与所述CG-FET的源极。
在本公开的一方面，一种结构包括：位于单个公共半导体区域的第一部分中的共源极FET(CS-FET)；以及位于所述单个公共半导体区域的第二部分中的共栅极FET(CG-FET)；其中，所述单个公共半导体区域是在所述单个公共半导体区域的不同部分中具有不同宽度的跳变(jogged)半导体区域。
在本公开的一方面，一种形成共源共栅单元的方法，包括：在单个公共半导体区域的第一部分中形成共源极FET(CS-FET)，所述CS-FET包括源极区和漏极区；在所述单个公共半导体区域的第二部分中形成共栅极FET(CG-FET)，所述CG-FET包括源极区和漏极区；以及在所述单个公共半导体区域中形成掺杂连接区域，所述掺杂连接区域连接所述CS-FET的漏极与所述CG-FET的源极，其中所述单个公共半导体区域是在所述单个公共半导体区域的不同部分中具有不同宽度的跳变半导体区域。
附图说明
在下面的详细描述中，借助本公开的示例性实施例的非限制性示例，参考所提到的多个附图来描述本公开。
图1示出了根据本公开的方面的利用一体式共源共栅单元的共源共栅放大器的电气示意图。
图2A示出了根据本公开的方面的除其他特征之外的一体式共源共栅单元的俯视图。
图2B示出了根据本公开的方面的图2A所示的一体式共源共栅单元的跨线2B-2B截取的截面图。
图3示出了比较图，该比较图将本文所述的结构与具有在分离的岛区域或分离的衬底中形成的CS-FET和CG-FET的常规器件进行比较。
具体实施方式
本公开涉及半导体结构，更具体地涉及一体式共源共栅单元优化及制造方法。更具体地，本公开涉及设置在单个公共半导体区域上的一体式共源共栅单元，该单个公共半导体区域包括连接CS-FET的漏极与CG-FET的源极的掺杂连接区域，不需要连接这些漏极区和源极区的金属化物(metallization)。有利地，除了减小的面积尺寸之外，一体式共源共栅单元还具有减小的寄生电容和电阻。
在已知的共源共栅放大器布置中，第一半导体区域(例如，岛区域或衬底)被设置用于共源共栅放大器的CS-FET晶体管，分离的第二半导体区域(例如，岛区域或衬底)被设置用于共源共栅放大器的CG-FET晶体管。在这种类型的结构中，每个CS-FET和每个CG-FET具有源极区、漏极区和沟道区，沟道区位于栅电极下方且位于源极区和漏极区之间。使用浅沟槽隔离区确保其中形成有CS-FET的第一半导体区域和其中形成有CG-FET的第二半导体区域之间的隔离，从而确保第一半导体区域和第二半导体区域是衬底中分离的半导体岛区域。另一方面，其中形成有CS-FET的第一半导体区域和其中形成有CG-FET的第二半导体区域可以是形成在下伏的(underlying)绝缘体上的分离的硅衬底(例如，SOI结构)。在任一种情况下，形成在第一半导体区域中的CS-FET的漏极和形成在第二半导体区域中的CG-FET的源极通过在第一和第二半导体区域之间延伸的金属化层(例如BEOL或MOL金属化层)连接。这种金属化层连接的要求增加了共源共栅单元的整体尺寸，并给器件增加了不希望的电阻(例如，气刨电阻)和电容(例如，寄生电容)。
与此形成对比，本公开的CS-FET和CG-FET集成在单个公共半导体区域中，形成一体式共源共栅单元。特别地，在单个公共半导体区域中设置用作浮动内部节点的连接区域，以充当CS-FET的漏极、CG-FET的源极以及CS-FET的漏极和CG-FET的源极之间的连接。这消除了在需要连接CS-FET的漏极和CG-FET的源极的已知结构中使用的金属化层。本文所述的结构也不需要在常规形成有CS-FET的第一半导体区域中设置分离的源极区以及在常规形成有CG-FET的第二半导体区域中设置分离的漏极区。因此，共源共栅放大器的尺寸、电阻和电容都减小了。
换句话说，在实施例中，共源共栅单元具有集成在同一跳变的单个公共半导体区域上的CS-FET和CG-FET，从而减小了单元面积、布线电阻和电容。另外，在实施例中，CG-FET的宽度小于CS-FET的宽度。此外，由于设置了掺杂连接区域作为CS-FET的漏极和CG-FET的源极之间的浮动节点，因此可以消除常规用于连接这些漏极和源极的MOL或BEOL接触。
根据本公开的另一方面，单个公共半导体区域可跳变，以使其不同的部分具有不同的宽度。具体地，在这种布置中，单个公共半导体区域跳变，从而在单个公共半导体区域的形成有CS-FET的部分中较宽，而在单个公共半导体区域的形成有CG-FET的部分中较窄。这允许CG-FET处理更大的电压，使得CS-FET可以具有较小的栅极长度LG，从而提高了用一体式共源共栅单元构造的共源共栅放大器的增益。
本公开的CS-FET和CG-FET晶体管可以使用多种不同的工具，以多种方式来制造。但是，一般地，使用方法和工具来形成具有微米和纳米级尺寸的结构。用于制造本公开的CS-FET和CG-FET晶体管的方法(即，技术)已经从集成电路(IC)技术被采用。例如，这些结构被构造在晶片上，并在借助晶片顶部上的光刻工艺而图案化的材料膜中实现。特别地，CS-FET和CG-FET晶体管的制造使用三个基本构造块：(i)在衬底上沉积材料薄膜；(ii)通过光刻成像在膜顶部施加图案化掩模；以及(iii)对掩模选择性地蚀刻该膜。
图1示出了根据本公开的方面的可以利用一体式共源共栅单元的共源共栅放大器电路10。如图1所示，共源共栅放大器10包括CS-FET 11，其漏极连接到CG-FET 12的源极。CS-FET 11用作共源共栅放大器的输入晶体管，在其栅极处接收由RF源13提供的RF输入。共源共栅放大器输出在CG-FET 12的漏极处提供。如图1所示，共源共栅放大器10包括其他电路元件，这些电路元件包括：耦接在RF源13和CS-FET 11的栅极之间的源电阻器Rs；耦接到CS-FET 11的栅极的电感器Lg；耦接在CS-FET 11的源极和地之间的Ls；耦接在CG-FET的漏极和电压源Vdd之间的LL；以及耦接在源电阻器Rs和电感器Lg之间的输入电容器C1，从而根据共源共栅放大器的公知工作原理，结合晶体管11和12实现放大操作。
图2A示出了根据本公开的方面的除其他特征之外的一体式共源共栅单元及相应的制造工艺的俯视图。图2B示出了沿着图2A所示的线2B-2B截取的一体式单元18的截面图。同时参考图2A和2B，该结构包括形成一体式共源共栅单元的单个公共半导体区域14。在实施例中，单个公共半导体区域14可以是形成在半导体衬底16中的扩散岛区域、在半导体衬底16上的外延生长的岛区域，或者是根据SOI技术的绝缘体上半导体衬底。单个公共半导体区域14和半导体衬底16可以由任何合适的材料组成，其中包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP和其他III/V或II/VI化合物半导体。
单个公共半导体区域14可以代表平面区域或者一个或多个鳍(fin)结构。以此方式，本文所述的晶体管可被提供为平面FET或FinFET。在FinFET实施方式中，可使用常规的侧壁图像转印(SIT)技术形成鳍结构。在SIT技术中，例如，使用常规CVD工艺将芯轴材料(例如SiO2)沉积在衬底上。将抗蚀剂形成在芯轴材料上，并暴露于光下以形成图案(开口)。通过开口执行反应离子蚀刻(RIE)以形成芯轴。在实施例中，取决于窄鳍结构和/或宽鳍结构之间的期望尺寸，芯轴可具有不同的宽度和/或间隔。将间隔物(spacer)形成在芯轴的侧壁上，该间隔物优选地是不同于芯轴的材料，并且使用本领域技术人员公知的常规沉积工艺来形成。间隔物的宽度例如可以与鳍结构的尺寸匹配。使用常规的蚀刻工艺针对芯轴材料有选择性地去除或剥离芯轴。然后在间隔物的间隔内执行蚀刻以形成亚光刻特征。然后可以剥离侧壁间隔物。在实施例中，如本公开所预期的，宽鳍结构也可以在这种或其他图案化工艺期间形成，或者通过其他常规的图案化工艺形成。
仍然参考图2A和图2B，一体式单元(unit cell)18包括两个CS-FET和两个CG-FET，具体地，包括第一CS-FET 20、第一CG-FET 22、第二CS-FET 24和第二CG-FET 26。第一和第二CS-FET 20和24各自包括源极区28、沟道区30、源极接触32、栅电极34(通过栅极绝缘体35而与沟道区30分隔开)，以及耦接到地的源极金属化物36。第一CG-FET 22和第二CG-FET 26各自包括漏极区38、漏极接触40、沟道区42、栅电极44(通过栅绝缘体45而与沟道区42分隔开)以及漏极金属化物46。接触32和40以及栅电极34和44在形成于单个公共半导体区域14上方的电介质材料47中形成。
CS-FET 22和26的栅电极34接收共源共栅放大器的RF输入信号，CG-FET 22和26的漏极金属化物46提供由一体式单元18形成的共源共栅放大器的RF输出信号。在该实施例中，一体式单元18被形成为使两个CS-FET 20和24以及两个CG-FET 22和26共享公共漏极区38和公共漏极接触40，以在漏极金属化物46处提供共源共栅放大器的RF输出信号。
在实施例中，栅电极34和44以及栅极电介质35和45可以被形成为栅结构的一部分，栅结构是通过任何已知的栅极制造工艺(即，先栅极工艺或替换栅极工艺)形成的FET结构。FET结构包括由栅极电介质材料(例如，高k电介质材料)、已知的功函数金属和侧壁间隔物(例如，氧化物或氮化物)组成的栅极电介质35和45。在先栅极工艺中，可以使用任何常规沉积方法(例如化学气相沉积(CVD)、等离子增强CVD(PECVD)等)来沉积栅极电介质和功函数金属(或多晶)。在沉积材料之后，可以使用常规的光刻和蚀刻(RIE)工艺对材料进行图案化。对于侧壁间隔物，在将材料沉积在图案化的栅结构上方之后，可以利用各向异性蚀刻工艺来去除侧壁间隔物材料。
仍然参考图2A和图2B，区域28、38和48可以是通过本领域普通技术人员已知的掺杂外延生长工艺形成的抬升式(raised)源极区和漏极区，因此不需要进一步解释就可以完全理解本公开。替代地，区域28、38和48可以是形成在单个公共半导体区域14中的扩散的源极区和漏极区。在实施例中，可通过本领域普通技术人员已知的常规离子注入工艺来形成区域28、38和48，因此不需要进一步解释就可以完全理解本公开。
接触32和40、栅电极34和44，以及金属化物36和46可使用常规的光刻、蚀刻和沉积工艺来形成。例如，在沉积电介质材料47之后，在电介质材料47中形成沟槽以暴露扩散区域或外延区域28和38以及沟道区30和42。然后在沟道区30和42上方形成栅极电介质，接着将金属材料(例如钨、钴等)沉积在过孔内，随后进行平面化工艺。接触32和40、栅电极34和44，以及金属化物36和46可通过各自的单镶嵌工艺或双镶嵌工艺形成。
接触可以包括漏极区和源极区上的硅化部分。例如，可以使用硅化工艺来形成硅化部分。本领域技术人员应当理解，硅化工艺开始于在完全形成和图案化的半导体器件(例如，掺杂的或离子注入的源极区和漏极区)上方沉积薄过渡金属层(例如镍、钴或钛)。在材料沉积之后，加热该结构，以使过渡金属与半导体器件的有源区(例如，源极区、漏极区、栅极接触区)中的暴露硅(或本文所述的其他半导体材料)发生反应，形成低电阻过渡金属硅化物。反应之后，通过化学蚀刻去除任何残留的过渡金属，从而在器件的有源区中留下硅化物接触。本领域技术人员应当理解，当栅极结构由金属材料构成时，器件上将不需要硅化物接触。
仍然参考图2A和图2B，掺杂连接区域48用作CS-FET 20和24的漏极区、CG-FET 22和26的源极区以及这些相应的源极区和漏极区之间的连接。这些掺杂连接区域48可以形成为抬升式掺杂外延区域，如图2B所示；或者形成为单个公共半导体区域14中扩散的掺杂区域。由于掺杂连接区域48用于多个目的，并且在共源共栅连接中不需要金属化层来连接CS-FET 11的漏极与CG-FET 12的源极，因此，所产生的共源共栅放大器小于常规的共源共栅放大器，并且具有较小的附加电阻和电容。因此，与常规的共源共栅放大器相比，利用本文公开的单个公共半导体区域14构成的一体式共源共栅结构的共源共栅结构具有改善的增益和线性度。
仍然参考图2A，本公开的另一方面是将单个公共半导体区域14构造为跳变结构，该跳变结构在一些部分中具有第一宽度W1，在其他部分中具有更大的第二宽度W2。具体地，在实施例中，CG-FET 22和26形成在单个公共半导体区域14的较小宽度部分中(例如，具有宽度W1)，而CS-FET 20和24形成在单个公共半导体区域14的宽度较大的第二部分(例如，具有宽度W2)中。宽度W1和W2分别对应于CS-FET和CG-FET的栅极宽度。
具有用于CG-FET和CS-FET的不同宽度W1和W2的跳变结构的优点是CG-FET 22和26的单元尺寸较小，这允许这些晶体管处理较大的电压，相应地允许CS-FET 20和24使用较小的栅极长度。在实施例中，宽度W1和W2之比为：W2大于或等于W1且小于或等于2×W1(即，W1的2倍)。
在上面讨论的利用跳变的单个公共半导体区域14的实施例中，在掺杂连接区域48中发生跳变(即，当从诸如图2A的俯视图观察时，单个公共半导体区域14的宽度的变化)。换句话说，如图2A所示，掺杂连接区域48在掺杂连接区域48的用作CG-FET的源极的区域中具有较小宽度W1，而在掺杂连接区域48的用作CS-FET的漏极的区域中具有较大宽度W2。
图3示出了比较图，该比较图比较了本文所述的结构与将分离的半导体器区域用于CS-FET和CG-FET的常规器件。在图3的曲线图中，示出了PEX+HSPICE分析以比较现有技术与本公开。图3示出了上面参考图2A和图2B所述的使用一体式共源共栅单元构造的CS-FET11和CG-FET12的电压电平和器件参数与使用常规共源共栅布置(其中分离的单元被用于CS-FET和CG-FET)构造的类似器件的比较。图3所示的曲线图中的Y轴示出了两个范围的最大稳定性增益(MSG)，而X轴示出了RF输出信号的以μA/μm为单位的漏极电流Id。特别地，图3的下部曲线图的Y轴示出了介于5至30之间的28GHz处的最大稳定性增益(以dB为单位)，而上部曲线图示出了介于0至600之间的28GHz处的最大稳定性增益(采取绝对单位)。线50示出了使用一体式共源共栅单元(例如图2A和图2B所示的共源共栅单元)的结果，线52示出了使用常规共源共栅布置(其中分离的半导体区域被用于CS-FET和CG-FET)的结果。从这两个曲线图可以理解，使用根据本公开的一体式共源共栅单元获得约15％(0.5dB)的改善。注意，该模拟是基于未优化的超大规模设计，包括未优化的工艺路线(routing)、高气刨电阻和高电容。通过设计优化有望实现更大的益处。
尽管以上描述是关于FET的，但应注意，对于使用双极结型晶体管(BJT)的共源共栅放大器，也可以获得改进，特别地，在单个公共半导体区域中形成构成双极共源共栅放大器的共发射极晶体管和共基极晶体管，如在此关于FET所讨论的。而且，尽管已将掺杂连接区域48描述为包括CS-FET的漏极和CS-FET的源极，并在它们之间提供连接，但是在替代实施例中，CS-FET的漏极和CG-FET的源极可以形成为分离的掺杂外延区域或分离的掺杂扩散区域，这些区域分别邻接掺杂连接区域48，使得掺杂连接区域48用作这些分离的源极区和漏极区的连接区域。通过这种布置，掺杂连接区域48的使用仍能避免对用于连接分离的漏极区和源极区的金属化物的需要，从而实现减小不期望的附加电阻和电容的优点。与掺杂连接区域48的掺杂水平相比，这种布置还允许容易地为源极区和漏极区提供不同的掺杂水平。
一体式共源共栅单元可以被用于片上系统(SoC)技术。本领域技术人员应当理解，SoC是将电子系统的所有组件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于组件集成在单个衬底上，因此与具有等效功能的多芯片设计相比，SoC消耗的功率少得多，占用的面积也小得多。因此，SoC正成为移动计算(例如智能手机)和边缘计算市场中的主导力量。SoC也常用于嵌入式系统和物联网。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(即，作为具有多个未封装芯片的单个晶片)，作为裸芯或以封装形式分发。在后一种情况下，芯片以单芯片封装(例如塑料载体，其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体，其具有表面互连和/或掩埋互连)的形式被安装。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成，作为(a)中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出，但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。

Claims (18)

1.一种半导体结构，包括：
位于单个公共半导体区域的第一部分中的共源极FET(CS-FET)，所述共源极FET包括源极区和漏极区；
位于所述单个公共半导体区域的第二部分中的共栅极FET(CG-FET)，所述共栅极FET包括源极区和漏极区；以及
所述单个公共半导体区域的掺杂连接区域，其连接所述共源极FET的漏极与所述共栅极FET的源极，
其中，所述单个公共半导体区域的所述第一部分比所述单个公共半导体区域的所述第二部分宽。
2.根据权利要求1所述的半导体结构，其中，所述掺杂连接区域是掺杂外延区域。
3.根据权利要求1所述的半导体结构，其中，所述掺杂连接区域是衬底中的扩散区域。
4.根据权利要求1所述的半导体结构，其中，所述单个公共半导体区域是衬底中的岛区域。
5.根据权利要求1所述的半导体结构，其中，所述第一部分具有宽度W2，所述第二部分具有宽度W1，其中，W2是处于等于或大于W1且等于或小于2×W1(W1的2倍)的范围内的值。
6.根据权利要求5所述的半导体结构，其中，所述共源极FET的栅极长度小于所述共栅极FET的栅极长度。
7.根据权利要求1所述的半导体结构，其中，所述共源极FET的栅极被配置为接收RF输入信号，所述共栅极FET的漏极被配置为提供RF输出信号。
8.根据权利要求1所述的半导体结构，其中，所述共源极FET和所述共栅极FET选自FinFET和平面FET中的至少一者。
9.根据权利要求8所述的半导体结构，其中，所述掺杂连接区域位于所述单个公共半导体区域的第三部分中，并且包括所述共源极FET的漏极和所述共栅极FET的源极。
10.一种半导体结构，包括：
位于单个公共半导体区域的第一部分中的共源极FET(CS-FET)；以及
位于所述单个公共半导体区域的第二部分中的共栅极FET(CG-FET)；
其中，所述单个公共半导体区域是在所述单个公共半导体区域的不同部分中具有不同宽度的跳变半导体区域，
其中，所述单个公共半导体区域的所述第一部分比所述单个公共半导体区域的所述第二部分宽。
11.根据权利要求10所述的半导体结构，其中，所述共源极FET的漏极和所述共栅极FET的源极共同位于所述单个公共半导体区域的掺杂连接区域中，所述掺杂连接区域连接所述共源极FET的漏极与所述共栅极FET的源极。
12.根据权利要求11所述的半导体结构，其中，所述掺杂连接区域是掺杂外延区域。
13.根据权利要求12所述的半导体结构，其中，所述单个公共半导体区域是衬底中的岛区域。
14.根据权利要求13所述的半导体结构，其中，所述第一部分具有宽度W2，所述第二部分具有宽度W1，其中，W2包括处于等于或大于W1且等于或小于2×W1(W1的2倍)的范围内的值，并且所述共源极FET的栅极长度小于所述共栅极FET的栅极长度。
15.根据权利要求11所述的半导体结构，进一步包括位于所述单个公共半导体区域的另一部分中的第二共源极FET，所述第二共源极FET包括连接到位于所述单个公共半导体区域的不同部分中的第二共栅极FET的源极的漏极，其中，所述不同部分位于所述另一部分和所述掺杂连接区域之间，并且所述共栅极FET和所述第二共栅极FET共享公共漏极区，所述公共漏极区形成共源共栅单元的输出。
16.一种形成共源共栅单元的方法，包括：
在单个公共半导体区域的第一部分中形成共源极FET(CS-FET)，所述共源极FET包括源极区和漏极区；
在所述单个公共半导体区域的第二部分中形成共栅极FET(CG-FET)，所述共栅极FET包括源极区和漏极区；以及
在所述单个公共半导体区域中形成掺杂连接区域，所述掺杂连接区域连接所述共源极FET的漏极与所述共栅极FET的源极，
其中，所述单个公共半导体区域是针对所述单个公共半导体区域中的所述第一部分和所述第二部分具有不同宽度的跳变半导体区域，
其中，所述单个公共半导体区域的所述第一部分比所述单个公共半导体区域的所述第二部分宽。
17.根据权利要求16所述的形成共源共栅单元的方法，其中，所述第一部分具有宽度W2，所述第二部分具有宽度W1，其中，W2是处于等于或大于W1且等于或小于2×W1(W1的2倍)的范围内的值，并且其中，所述共源极FET的栅极长度小于所述共栅极FET的栅极长度。
18.根据权利要求16所述的形成共源共栅单元的方法，其中，所述掺杂连接区域是掺杂外延区域。
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