CN113539170B

CN113539170B - Pixel driving circuit, driving method thereof, display substrate and display device

Info

Publication number: CN113539170B
Application number: CN202110785798.5A
Authority: CN
Inventors: 刘伟星; 彭宽军; 秦斌; 周飞虎; 王铁石; 郭凯; 张春芳
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-07-12
Filing date: 2021-07-12
Publication date: 2022-12-02
Anticipated expiration: 2041-07-12
Also published as: CN113539170A

Abstract

The embodiment of the disclosure provides a pixel driving circuit, a driving method thereof, a display substrate and a display device. The pixel driving circuit includes: the LED chip comprises n light-emitting parts, wherein a first semiconductor layer of the ith light-emitting part is connected with a second semiconductor layer of the (i + 1) th light-emitting part, a first semiconductor layer of the (n-1) th light-emitting part is connected with the first semiconductor layer of the nth light-emitting part, a second semiconductor layer of the nth light-emitting part is connected with the second semiconductor layer of the first light-emitting part, and a connection point of every two light-emitting parts forms an access point; and the n switch control units are connected with the access points in a one-to-one correspondence manner, are configured to receive the data voltage of the data signal end under the control of the scanning signal end, and provide an electric signal to the corresponding access point based on the voltage of the driving power end so as to drive at least one light-emitting part to work. According to the technical scheme, the number of the gray scales of the LED chip is more than that of the LED chip by setting the data voltage of the data signal end.

Description

Pixel driving circuit, driving method thereof, display substrate and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, a display substrate, and a display device.

Background

Organic Light-Emitting diodes (OLEDs) are a display illumination technology that has been gradually developed in recent years, and particularly in the display industry, OLED display is considered to have a wide application prospect because of its advantages of high response, high contrast, flexibility, and the like. The OLED is mainly driven by a pixel circuit, for example, a pixel circuit of 3T1C, 5T1C, 7T1C, or the like.

With the development of display technology, the display of an inorganic Light Emitting Diode (LED) is rapidly developed, and in the prior art, a pixel circuit suitable for an OLED is usually adopted to drive the LED to operate, and the display of different gray scales of the LED is realized by using data voltage. However, for the LED display, the voltage difference between each gray level is only about 0.02V, and it is difficult to achieve the display of 256 gray levels or more.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel driving circuit, a driving method thereof, a display substrate, and a display device, so as to solve or alleviate one or more technical problems in the prior art.

As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a pixel driving circuit including:

the LED chip comprises n light-emitting parts, wherein a first semiconductor layer of the ith light-emitting part is connected with a second semiconductor layer of the (i + 1) th light-emitting part, a first semiconductor layer of the (n-1) th light-emitting part is connected with a first semiconductor layer of the nth light-emitting part, a second semiconductor layer of the nth light-emitting part is connected with a second semiconductor layer of the first light-emitting part, and a connection point of every two light-emitting parts forms an access point, wherein n is a positive integer greater than or equal to 3, and i is an integer from 1 to (n-2);

the switch control units are respectively connected with the jth driving power supply end, the jth data signal end, the jth scanning signal end and the public power supply end, and are configured to receive a data voltage of the jth data signal end under the control of the jth scanning signal end and provide an electric signal for the corresponding access point based on the voltage of the jth driving power supply end so as to drive at least one light-emitting part to work, wherein j is an integer from 1 to n.

In some possible implementations, the pixel driving circuit further includes n data signal lines, each data signal line is connected to each data signal terminal in a one-to-one correspondence, and the data signal lines are configured to supply a data voltage to the corresponding data signal terminal.

In some possible implementations, the pixel driving circuit further includes a data signal generating subunit and a time-sharing driving subunit, the data signal generating subunit is connected with the n data signal lines through the time-sharing driving subunit, and the time-sharing driving subunit is configured to time-share supply the data voltage output by the data signal generating subunit to the n data signal lines.

In some possible implementations, the pixel driving circuit further includes a scan signal line connected to each of the n scan signal terminals to supply the scan signal to the n scan signal terminals.

In some possible implementations, the pixel driving circuit includes n scanning signal lines, each of the scanning signal lines is connected to each of the scanning signal terminals in a one-to-one correspondence, and the scanning signal lines are configured to supply a scanning signal to the corresponding scanning signal terminals.

In some possible implementations, the pixel driving circuit includes a data signal line connected to each of the n data signal terminals to supply the data voltage to the n data signal terminals.

In some of the possible implementations of the present invention,

the light emitting areas of the n light emitting parts are different, so that the brightness values of the LED chips are different when the light emitting parts independently emit light; and/or the presence of a gas in the gas,

the voltage difference between every two adjacent driving power supply ends in the n driving power supply ends is different, so that the brightness values of the LED chips are different when the first to the (n-1) th light emitting parts respectively and independently emit light.

In some possible implementations, the switch control unit includes:

the writing subunit is respectively connected with the jth data signal terminal, the jth scanning signal terminal and the first node, and is configured to provide a data voltage of the jth data signal terminal to the first node under the control of the jth scanning signal terminal;

a driving subunit connected to the jth driving power supply terminal, the access point, and the first node, respectively, and configured to supply an electrical signal to the access point based on a voltage of the jth driving power supply terminal under control of the first node;

and the storage sub-units are respectively connected with the first node and the public power supply end and are configured to store the charges of the first node.

In some of the possible implementations of the method,

the writing subunit comprises a first transistor, the grid electrode of the first transistor is connected with the jth scanning signal end, the first pole of the first transistor is connected with the jth data signal end, and the second pole of the first transistor is connected with the first node;

the driving subunit comprises a second transistor, the grid electrode of the second transistor is connected with the first node, the first pole of the second transistor is connected with the jth driving power supply end, and the second pole of the second transistor is connected with the access point;

the storage subunit comprises a storage capacitor, and two pole plates of the storage capacitor are respectively connected with the first node and a common power supply end.

As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method of a pixel driving circuit, for the pixel driving circuit in any of the above embodiments, the method including:

according to the gray scale to be displayed of the LED chip, the state of each scanning signal end corresponding to the gray scale to be displayed and the data voltage of each data signal end are obtained from the LED chip display gray scale table;

setting the state of each scanning signal end and the data voltage of each data signal end according to the obtained result so as to enable the LED chip to carry out corresponding gray scale display;

the LED chip gray scale table comprises a corresponding relation between a display gray scale of the LED chip and each state of the n scanning signal ends and each data voltage of the n data signal ends.

As a third aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display substrate including an LED chip including n light emitting portions, the display substrate including:

a substrate;

n first semiconductor layers, on one side of the substrate;

the n multi-quantum well layers are positioned on one sides, away from the substrate, of the n first semiconductor layers and correspond to the n first semiconductor layers one to one;

the n second semiconductor layers are positioned on one sides of the n multi-quantum well layers, which are far away from the substrate, and correspond to the n multi-quantum well layers one to one; (ii) a

Wherein the first semiconductor layer of the i-th light emitting part is connected to the second semiconductor layer of the i + 1-th light emitting part, the first semiconductor layer of the n-1-th light emitting part is connected to the first semiconductor layer of the n-th light emitting part, the second semiconductor layer of the n-th light emitting part is connected to the second semiconductor layer of the first light emitting part, n is a positive integer greater than or equal to 3, and i is an integer from 1 to (n-2).

In some possible implementations, the method further includes:

the first insulating layer is positioned on one side, away from the substrate, of the second semiconductor layer, the orthographic projection of each light emitting part on the substrate is positioned in the orthographic projection range of the first insulating layer on the substrate, the first insulating layer is provided with n-2 first via holes, the n-2 first via holes are in one-to-one correspondence with the first to the n-2 first semiconductor layers and expose the corresponding first semiconductor layers, the first insulating layer is further provided with n second via holes, and the n second via holes are in one-to-one correspondence with the n second semiconductor layers and expose the corresponding second semiconductor layers;

the bridge connection metal layer is positioned on one side, away from the substrate, of the insulating layer and comprises n-2 first bridge connection lines and one second bridge connection line, the n-2 first bridge connection lines sequentially pass through the first via hole and the second via hole to connect the corresponding ith first semiconductor layer with the (i + 1) th second semiconductor layer, and the second bridge connection lines connect the first second semiconductor layer with the nth second semiconductor layer through the first second via hole and the nth second via hole.

In some possible implementation manners, an orthographic projection of the second via hole on the substrate is located within an orthographic projection range of the second semiconductor layer on the substrate, the display substrate further includes a transparent conductive layer, the transparent conductive layer includes n electrode connection lines, each electrode connection line is connected with the corresponding second semiconductor layer through each second via hole, the first bridging line is connected with the corresponding second semiconductor layer through the corresponding electrode connection line and the corresponding second via hole, and the second bridging line is connected with both the first electrode connection line and the nth electrode connection line.

As a fourth aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a display device including the pixel driving circuit in any embodiment of the present disclosure or the display substrate in any embodiment of the present disclosure.

According to the technical scheme of the embodiment of the disclosure, one LED chip comprises n light emitting parts, and at least one light emitting part can be driven to work through n switch control units, so that different or different numbers of light emitting parts can be driven to work through n switch control units, and multi-gray scale display of the LED chip can be realized. And the switch control unit receives the data voltage of the jth data signal end Dataj and provides an electric signal to the corresponding access point P based on the voltage of the jth driving power supply end Vj, so that different data voltages can be provided through the jth data signal end Dataj, the brightness of the corresponding light emitting part is controlled, the gray scale number of the LED chip is further improved, higher gray scale display of the LED chip is further realized, and multi-gray scale modulation can be realized.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 7 is a timing diagram of the circuit of FIG. 6;

FIG. 8 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 9 is a timing diagram of the circuit of FIG. 8;

FIG. 10 is a schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

FIG. 11 is a timing diagram of the circuit of FIG. 10;

FIG. 12 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

FIG. 13base:Sub>A isbase:Sub>A schematic view of the cross-sectional structure A-A of FIG. 12;

FIG. 13B is a schematic cross-sectional view B-B of FIG. 12;

FIG. 14 is a schematic plan view showing the substrate after a second semiconductor layer is formed thereon;

FIG. 15base:Sub>A isbase:Sub>A schematic cross-sectional view A-A of FIG. 14;

FIG. 15B is a schematic cross-sectional view B-B of FIG. 14;

FIG. 16 is a schematic plan view showing the substrate after a first insulating layer is formed thereon;

FIG. 17base:Sub>A isbase:Sub>A schematic cross-sectional view A-A of FIG. 16;

FIG. 17B is a schematic cross-sectional view B-B of FIG. 16;

FIG. 18 is a schematic plan view showing a substrate after a bridge metal layer is formed thereon;

FIG. 19base:Sub>A isbase:Sub>A schematic cross-sectional view A-A of FIG. 18;

FIG. 19B is a schematic cross-sectional view B-B of FIG. 18;

FIG. 20 is a schematic plan view showing a transparent conductive layer formed on a substrate;

FIG. 21base:Sub>A isbase:Sub>A schematic cross-sectional view A-A of FIG. 20;

FIG. 21B is a schematic cross-sectional view B-B of FIG. 20;

FIG. 22 is a schematic plan view showing a transparent conductive layer formed on a display substrate;

FIG. 23base:Sub>A isbase:Sub>A schematic cross-sectional view A-A of FIG. 22;

FIG. 23B is a schematic cross-sectional view B-B of FIG. 22;

FIG. 24a is a schematic plan view of a display substrate according to another embodiment of the present disclosure after a second semiconductor layer is formed;

FIG. 24b is a schematic plan view illustrating a display substrate after a first insulating layer is formed thereon according to another embodiment of the present disclosure;

FIG. 24c is a schematic plan view illustrating a transparent conductive layer formed on a display substrate according to another embodiment of the present disclosure;

FIG. 24d is a schematic plan view illustrating a substrate with an encapsulation layer formed thereon according to another embodiment of the present disclosure;

FIG. 24e is a schematic plan view illustrating a substrate with a metal via layer formed thereon according to another embodiment of the present disclosure;

FIG. 25a is a schematic cross-sectional view C-C of FIG. 24 e;

fig. 25b is a schematic cross-sectional view D-D of fig. 24 e.

Description of reference numerals:

10. a light emitting section; 11. writing the subunit; 12. a drive subunit; 13. a storage subunit; 21. a substrate; 221. a first semiconductor layer; 231. a multiple quantum well layer; 241. a second semiconductor layer; 25. a first insulating layer; 251. a first via hole; 252. a second via hole; 26. bridging the metal layers; 261. a first bridge connection line; 262. a second bridge connection; 27. a transparent conductive layer; 271. an electrode connecting wire; 28. a second insulating layer; 29. a packaging layer; 30. a metal transfer layer; 31. a power pad; 43. a third via hole; 44. a fourth via hole; 45. and a fifth via.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors used in embodiments of the present invention are primarily switching transistors depending on the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiments of the present invention, a source (source electrode) is referred to as a first pole and a drain (drain electrode) is referred to as a second pole, or alternatively, the drain may be referred to as the first pole and the source may be referred to as the second pole. In the form shown in the drawings, the transistor has a gate (which may be called a gate electrode) as an intermediate terminal, a source as a signal input terminal, and a drain as a signal output terminal. The switch transistor adopted by the embodiment of the invention can be a P-type switch transistor or an N-type transistor, wherein the P-type switch transistor is switched on when the grid electrode is at a low level and is switched off when the grid electrode is at a high level; the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, the plurality of signals in the embodiments of the present invention correspond to the first potential and the second potential. The first potential and the second potential represent only 2 state quantities of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text. In the embodiment of the present invention, the first potential is taken as an example of the effective potential.

Wherein the coupling may comprise: the two ends are electrically connected or the two ends are directly connected (for example, the two ends are connected through a signal wire). The embodiment of the present invention does not limit the coupling manner between the two ends.

Fig. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the disclosure. As shown in fig. 1, the pixel driving circuit may include an LED chip and n switching control units 10. The LED chip includes n light emitting parts D1, D2, …, dn. Each light emitting portion includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer, which are sequentially stacked. The first semiconductor layer of the i-th light emitting portion is connected to the second semiconductor layer of the i + 1-th light emitting portion, the first semiconductor layer of the n-1-th light emitting portion is connected to the first semiconductor layer of the n-th light emitting portion, and the second semiconductor layer of the n-th light emitting portion is connected to the second semiconductor layer of the first light emitting portion. As is clear from the above, the number of access points P is n, and access points P are formed for each connection point of two light emitting units. Wherein n is a positive integer of 3 or more, i is an integer of 1 to (n-2), for example, i is 1,2, …, n-2.

Each switch control unit 10 is connected to each access point P in a one-to-one correspondence, and is connected to the jth drive power supply terminal Vj, the jth data signal terminal Dataj, the jth scan signal terminal Gatej, and the common power supply terminal VSS, respectively. The switch control unit 10 is configured to receive the data voltage of the jth data signal terminal Dataj under the control of the jth scan signal terminal Gatej, and provide an electrical signal to the corresponding access point P based on the voltage of the jth driving power terminal Vj to drive at least one light emitting part to operate, where j is an integer from 1 to n, e.g., j is 1,2, …, n.

Illustratively, the first semiconductor layer may be regarded as a cathode of the light emitting portion, and the second semiconductor layer may be regarded as an anode of the light emitting portion; alternatively, the first semiconductor layer may be regarded as an anode of the light-emitting portion, and the second semiconductor layer may be regarded as a cathode of the light-emitting portion.

According to the pixel driving circuit, one LED chip comprises n light emitting parts, and at least one light emitting part can be driven to work through n switch control units, so that different or different numbers of light emitting parts can be driven to work through n switch control units, and multi-gray-scale display of the LED chip can be achieved. And the switch control unit receives the data voltage of the jth data signal end Dataj and provides an electric signal to the corresponding access point P based on the voltage of the jth driving power supply end Vj, so that different data voltages can be provided through the jth data signal end Dataj, the brightness of the corresponding light emitting part is controlled, the gray scale number of the LED chip is further improved, higher gray scale display of the LED chip is further realized, and multi-gray scale modulation can be realized.

In one embodiment, as shown in fig. 1, n may be 3, that is, the LED chip includes 3 light emitting parts, D1, D2, and D3, respectively. The first semiconductor layer of the first light emitting part D1 is connected to the second semiconductor layer of the second light emitting part D2, the first semiconductor layer of the second light emitting part D2 is connected to the first semiconductor layer of the third light emitting part D3, the second semiconductor layer of the third light emitting part D3 is connected to the second semiconductor layer of the first light emitting part, the connection point of the first light emitting part D1 and the third light emitting part D3 forms an access point P1, the connection point of the first light emitting part D1 and the second light emitting part forms an access point P2, and the connection point of the second light emitting part D2 and the third light emitting part D3 forms an access point P3.

The number of the switch control units is 3, and the switch control units are respectively 10-1, 10-2 and 10-3. The switch control unit 10-1 is connected to the access point P1, and is respectively connected to the first driving power source terminal V1, the first Data signal terminal Data1, the first scanning signal terminal Gate1, and the common power source terminal VSS. The switch control unit 10-2 is connected to the access point P2, and is connected to the second driving power source terminal V2, the second Data signal terminal Data2, the second scanning signal terminal Gate2, and the common power source terminal VSS, respectively. The switch control unit 10-3 is connected to the access point P3, and is connected to the third driving power source terminal V3, the third Data signal terminal Data3, the third scanning signal terminal Gate3, and the common power source terminal VSS, respectively. The j-th driving power source terminal Vj supplies an electric signal to the access point Pj through the switch control unit 10-j.

As shown in fig. 1, the switch control unit connected to both ends of the light emitting part is used to control the voltage value across the light emitting part. Illustratively, V1, V2, V3 decrease sequentially, i.e., V1 > V2> V3.

Under the condition that the first driving power supply end V1 and the second driving power supply end V2 are respectively connected to the pixel driving circuit, the first light-emitting part D1 emits light; the second light emitting unit D2 emits light when the second driving power source terminal V2 and the third driving power source terminal V3 are connected to the pixel driving circuit, respectively; when the first driving power source terminal V1 and the third driving power source terminal V3 are connected to the pixel driving circuit, the third light emitting part D3 emits light, and the first light emitting part D1 and the second light emitting part D2 emit light by voltage division; when the first power supply driving terminal V1, the second power supply driving terminal V2, and the third power supply driving terminal V3 are connected to the pixel driving circuit, the first light-emitting portion D1, the second light-emitting portion D2, and the third light-emitting portion D3 emit light. In addition, when none of the driving power source terminals Vj is connected to the pixel driving circuit, none of the light emitting portions emits light, and the LED chip does not emit light. It can be seen that the pixel driving circuit shown in fig. 1 can realize 5 gray scales.

The switch control unit is configured to receive the data voltage of the jth data signal terminal under the control of the jth scanning signal terminal and provide an electrical signal to the corresponding access point Pj based on the voltage of the jth driving power terminal, so that the electrical signal of the access point Pj is determined by the data voltage of the jth data signal terminal under the condition that the voltage of the jth driving power terminal is constant, and the electrical signals provided to the access point Pj are different under the condition that the data voltages of the jth data signal terminal are different.

Illustratively, as shown in fig. 1, in the case that each data signal terminal Dataj can provide 3 data voltages, each switch control unit can have 3 voltage write values, and as shown in fig. 1, the pixel driving circuit can implement 2 ³ +2*2*C ₃ ¹ +2*C ₃ ² +C ₃ ³ =27 gradations.

Illustratively, as shown in fig. 1, in the case that each data signal terminal Dataj can provide 4 data voltages, each switch control unit can have 4 voltage write values, and the pixel driving circuit shown in fig. 1 can realize 3 ³ +3*3*C ₃ ¹ +3*C ₃ ² +C ₃ ³ =64 gray levels.

It can be seen from the above embodiments that, in the pixel driving circuit according to the embodiments of the present disclosure, multiple gray scales of the LED chip can be realized by setting the number of data voltages at each data signal terminal, and 256 gray scales or more of gray scales of the LED chip can be displayed by setting each data signal terminal to be capable of providing 4 or more data voltages, which is relatively easy to realize 256 gray scales or more of gray scales of the LED chip.

In one embodiment, each data signal terminal is configured to provide at least 4 different data voltage values. As can be seen from the embodiment of fig. 1, when each data signal terminal is configured to provide 4 different data voltages, the pixel driving circuit shown in fig. 1 can achieve 257 gray levels, and therefore, the pixel driving circuit according to the embodiment of the disclosure can achieve the number of gray levels of the LED chip greater than 256.

The pixel driving circuit of the embodiment of the disclosure sets at least 4 different data voltages for each data signal end, and does not need to limit the voltage difference distance between each gray scale to 0.02V, so that no matter low-brightness display (single light emitting part display) or high-brightness display (multiple light emitting parts display), the light emitting parts can be in a large current density driving state, and the light emitting efficiency of the LED chip is improved.

In order to make the LED chips have different luminance when a single light emitting part emits light, in one embodiment, the light emitting areas of the n light emitting parts are different from each other, so that the luminance values of the LED chips are different from each other when the light emitting parts emit light independently. Therefore, when the light emitting area of each light emitting part is set to realize the light emitting of a single light emitting part, the LED chip has different brightness and realizes different gray scales. For example, among the n light emitting portions, the light emitting area of each light emitting portion may gradually increase from the first light emitting portion to the nth light emitting portion. It is understood that, for one light emitting portion, the first semiconductor layer, the multiple quantum well layer, and the second semiconductor layer, the overlapping region in the stacking direction of the three layers is substantially a light emitting region of the light emitting portion, and the area of the overlapping region in the stacking direction of the three layers is substantially a light emitting area of the light emitting portion.

In one embodiment, the voltage difference between every two adjacent driving power source terminals of the n driving power source terminals is different, that is, as shown in fig. 1, V1-V2 ≠ V2-V3, so that the brightness values of the LED chips are different when the first to the n-1 th light emitting parts respectively emit light independently. It can be understood that the driving voltage value of the light emitting part is the voltage difference value between two access points at two ends of the light emitting part, and when the voltage difference between every two adjacent driving power terminals is different, the voltage difference value at two ends of each light emitting part is also different, that is, the driving voltages of the light emitting parts are different, even if the light emitting areas of the light emitting parts are the same, and the first to (n-1) th light emitting parts respectively and independently emit light, different gray scale display of the LED chip can be realized. Illustratively, the difference between every two adjacent driving voltages of the driving voltages provided by the n driving power supply terminals can be sequentially increased, such as V1-V2> V2-V3> V3-V4 … > V (n-1) -Vn.

Fig. 2 is a schematic diagram of a pixel driving circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 2, the switch control unit 10 may include a writing subunit 11, a driving subunit 12, and a storage subunit 13.

The write subunit 11 is respectively connected to the jth data signal terminal Dataj, the jth scan signal terminal Gatej, and the first node N1, and is configured to provide the data voltage of the jth data signal terminal Dataj to the first node N1 under the control of the jth scan signal terminal Gatej.

The driving sub-unit 12 is connected to the jth driving power supply terminal Vj, the access point Pj, and the first node N1, respectively, and is configured to supply an electric signal to the access point Pj based on a voltage of the jth driving power supply terminal Vj under the control of the first node N1.

The storage sub-unit 13 is connected to the first node N1 and the common power source terminal VSS, respectively, and is configured to store charges of the first node N1.

Fig. 3 is a schematic diagram of a pixel driving circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 3, the write subunit 11 includes a first transistor T1, a gate of the first transistor T1 is connected to the jth scan signal terminal Gatej, a first pole of the first transistor T1 is connected to the jth data signal terminal Dataj, and a second pole of the first transistor T1 is connected to the first node N1.

The driving subunit 12 includes a second transistor T2, a gate of the second transistor T2 is connected to the first node N1, a first pole of the second transistor T2 is connected to the jth driving power supply terminal Vj, and a second pole of the second transistor T2 is connected to the access point Pj;

the storage sub-unit 13 includes a storage capacitor Cst, and both plates of the storage capacitor Cst are connected to the first node N1 and a common power supply terminal VSS, respectively.

Exemplarily, an exemplary structure of the writing subunit, the driving subunit, and the storage subunit is shown in fig. 3, and it is understood by those skilled in the art that the writing subunit, the driving subunit, and the storage subunit are not limited to the structure shown in fig. 3 as long as functions thereof can be implemented.

The pixel driving circuit shown in fig. 3 has a 6T3C structure, in which the first transistor T1 and the second transistor T2 in the switch control unit are both PMOS transistors. It is understood that the first transistor T1 and the second transistor T2 may be both NMOS in other embodiments, and the technical effects of the embodiments of the present disclosure may be achieved as well.

Fig. 4 is a schematic diagram of a pixel driving circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 4, n may be 4, that is, the LED chip includes 4 light emitting parts, D1, D2, D3, and D4, respectively. The first semiconductor layer of the first light-emitting part D1 is connected to the second semiconductor layer of the second light-emitting part D2, the first semiconductor layer of the second light-emitting part D2 is connected to the second semiconductor layer of the third light-emitting part D3, the first semiconductor layer of the third light-emitting part D3 is connected to the first semiconductor layer of the fourth light-emitting part D4, the second semiconductor layer of the fourth light-emitting part D4 is connected to the second semiconductor layer of the first light-emitting part D1, the connection point of the first light-emitting part D1 and the fourth light-emitting part D4 forms an access point P1, the connection point of the first light-emitting part D1 and the second light-emitting part forms an access point P2, the connection point of the second light-emitting part D2 and the third light-emitting part forms an access point P3, and the connection point of the third light-emitting part D3 and the fourth light-emitting part D4 forms an access point P4.

The number of the switch control units is 4, and the switch control units are respectively 10-1, 10-2, 10-3 and 10-4. The switch control unit 10-1 is connected to the access point P1, and is respectively connected to the first driving power source terminal V1, the first Data signal terminal Data1, the first scanning signal terminal Gate1, and the common power source terminal VSS. The switch control unit 10-2 is connected to the access point P2, and is connected to the second driving power source terminal V2, the second Data signal terminal Data2, the second scanning signal terminal Gate2, and the common power source terminal VSS, respectively. The switch control unit 10-3 is connected to the access point P3, and is connected to the third driving power source terminal V3, the third Data signal terminal Data3, the third scanning signal terminal Gate3, and the common power source terminal VSS, respectively. The switch control unit 10-4 is connected to the access point P4, and is connected to the fourth driving power terminal V4, the fourth Data signal terminal Data4, the fourth scanning signal terminal Gate4, and the common power terminal VSS, respectively. The j-th driving power source terminal Vj supplies an electric signal to the access point Pj through the switch control unit 10-j.

In the pixel driving circuit shown in fig. 4, each data signal terminal Dataj has two states of 0 and 1, and the pixel driving circuit shown in fig. 4 can realize 15 gray scales. In the case where three data voltages can be supplied to each data signal terminal Dataj, each switching control unit may have 3 voltage writing values, and the pixel driving circuit shown in fig. 4Way can realize 2 ⁴ +2*2*2*C ₄ ¹ +2*2*C ₄ ² +2*C ₄ ³ +C ₄ ⁴ =81 gray levels. In the case where each data signal terminal Dataj can provide five data voltages, each switch control unit can have 5 voltage writing values, and the pixel driving circuit shown in fig. 4 can realize 4 ⁴ +4*4*4*C ₄ ¹ +4*4*C ₄ ² +4*C ₄ ³ +C ₄ ⁴ =621 gray levels.

Fig. 5 is a schematic diagram of a pixel driving circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 5, n may be 6, that is, the LED chip includes 6 light emitting parts, D1, D2, D3, D4, D5, and D6, respectively. The first semiconductor layer of the first light-emitting portion D1 is connected to the second semiconductor layer of the second light-emitting portion D2, the first semiconductor layer of the second light-emitting portion D2 is connected to the second semiconductor layer of the third light-emitting portion D3, the first semiconductor layer of the third light-emitting portion D3 is connected to the second semiconductor layer of the fourth light-emitting portion D4, the first semiconductor layer of the fourth light-emitting portion D4 is connected to the second semiconductor layer of the fifth light-emitting portion D5, the first semiconductor layer of the fifth light-emitting portion D5 is connected to the first semiconductor layer of the sixth light-emitting portion D6, and the second semiconductor layer of the sixth light-emitting portion D6 is connected to the second semiconductor layer of the first light-emitting portion D1. The point of connection between the first luminescent part D1 and the sixth luminescent part D6 forms an access point P1, the point of connection between the first luminescent part D1 and the second luminescent part forms an access point P2, the point of connection between the second luminescent part D2 and the third luminescent part forms an access point P3, the point of connection between the third luminescent part D3 and the fourth luminescent part D4 forms an access point P4, the point of connection between the fourth luminescent part D4 and the fifth luminescent part D5 forms an access point P5, and the point of connection between the fifth luminescent part D5 and the sixth luminescent part D6 forms an access point P6.

The number of the switch control units is 6, and the switch control units are respectively 10-1, 10-2, 10-3, 10-4, 10-5 and 10-6. The switch control unit 10-1 is connected to the access point P1, and is connected to the first driving power source terminal V1, the first Data signal terminal Data1, the first scanning signal terminal Gate1, and the common power source terminal VSS, respectively. The switch control unit 10-2 is connected to the access point P2, and is connected to the second driving power source terminal V2, the second Data signal terminal Data2, the second scanning signal terminal Gate2, and the common power source terminal VSS, respectively. The switch control unit 10-3 is connected to the access point P3, and is connected to the third driving power source terminal V3, the third Data signal terminal Data3, the third scanning signal terminal Gate3, and the common power source terminal VSS, respectively. The switch control unit 10-4 is connected to the access point P4, and is connected to the fourth driving power terminal V4, the fourth Data signal terminal Data4, the fourth scanning signal terminal Gate4, and the common power terminal VSS, respectively. The switch control unit 10-3 is connected to the access point P3, and is connected to the third driving power source terminal V3, the third Data signal terminal Data3, the third scanning signal terminal Gate3, and the common power source terminal VSS, respectively. The switch control unit 10-4 is connected to the access point P4, and is connected to the fourth driving power terminal V4, the fourth Data signal terminal Data4, the fourth scanning signal terminal Gate4, and the common power terminal VSS, respectively. The switch control unit 10-5 is connected to the access point P5, and is connected to a fifth driving power source terminal V5, a fifth Data signal terminal Data5, a fifth scanning signal terminal Gate5, and a common power source terminal VSS, respectively. The switch control unit 10-6 is connected to the access point P6, and is connected to a sixth driving power source terminal V6, a sixth Data signal terminal Data6, a sixth scanning signal terminal Gate6, and a common power source terminal VSS, respectively. The j-th driving power source terminal Vj supplies an electric signal to the access point Pj through the switch control unit 10-j.

In the pixel driving circuit shown in fig. 5, each data signal terminal Dataj has two states of 0 and 1, and the pixel driving circuit shown in fig. 5 can realize gray scales. In the case that each data signal terminal Dataj can provide two data voltages, each switch control unit can have 3 voltage writing values, and the pixel driving circuit shown in fig. 5 can realize 2 ⁶ +2*2*2*2*2*C ₆ ¹ +2*2*2*2*C ₆ ² +2*2*2*C ₆ ³ +2*2*C ₆ ⁴ +2C ₆ ⁵ +C ₆ ⁶ =549 gray levels.

Fig. 6 is a schematic diagram of a pixel driving circuit according to another embodiment of the disclosure, and fig. 6 shows two rows and two columns of LED chips. In one embodiment, as shown in fig. 3 and 6, the pixel driving circuit may further include n data signal lines, each data signal line Dj is connected to each data signal terminal Dataj in a one-to-one correspondence, and the data signal line Dj is configured to supply a data voltage to the corresponding data signal terminal Dataj. For example, in the case where n is 3, the pixel driving circuit may include 3 Data signal lines, and the first Data signal line D1 is connected to the first Data signal terminal Data1 to supply the Data voltage to the first Data signal terminal Data 1; the second Data signal line D2 is connected to the second Data signal terminal Data2 to supply a Data voltage to the second Data signal terminal Data 2; the third Data signal line D3 is connected to the third Data signal terminal Data3 to supply a Data voltage to the third Data signal terminal Data 1.

In the embodiment shown in fig. 6, the n data signal lines may be independent from each other, and the n data signal lines may be connected to the n data signal generating sub-units in a one-to-one correspondence, so that each data signal generating sub-unit may provide a data signal to the corresponding data signal line.

For example, as shown in fig. 6, the display substrate may include a plurality of rows and a plurality of columns of LED chips, and the LED chips located in the same row may share n data signal lines.

In one embodiment, as shown in fig. 6, the pixel driving circuit may further include a scan signal line G connected to each of the scan signal terminal gates to simultaneously supply the scan signals to the n scan signal terminal gates.

For example, as shown in fig. 6, the display substrate may include a plurality of rows and a plurality of columns of LED chips, and the LED chips located in the same row may share one scanning signal line G.

FIG. 7 is a timing diagram of the circuit of FIG. 6. In the circuit shown in fig. 6, for one LED chip, the scanning signal line G controls n switch control units to be turned on simultaneously, and the n Data signal lines D respectively supply Data voltages to n Data signal terminals Data to control one or more light emitting parts in the LED chip to operate, thereby realizing different gray scale display of the LED chip.

Fig. 8 is a schematic diagram of a pixel driving circuit in another embodiment of the present disclosure, and fig. 8 shows two rows and two columns of LED chips. In one embodiment, as shown in fig. 3 and 8, the pixel driving circuit may further include n data signal lines, each data signal line Dj is connected to each data signal terminal Dataj in a one-to-one correspondence, and the data signal line Dj is configured to supply a data voltage to the corresponding data signal terminal Dataj. For example, in the case where n is 3, the pixel driving circuit may include 3 Data signal lines, and the first Data signal line D1 is connected to the first Data signal terminal Data1 to supply the Data voltage to the first Data signal terminal Data 1; the second Data signal line D2 is connected to the second Data signal terminal Data2 to supply a Data voltage to the second Data signal terminal Data 2; the third Data signal line D3 is connected to the third Data signal terminal Data3 to supply a Data voltage to the third Data signal terminal Data 1.

Exemplarily, as shown in fig. 8, the pixel driving circuit may further include a Data signal generating subunit 14 and a time-sharing driving subunit (Mux) 15, and the Data signal generating subunit 14 is connected with the n Data signal lines Data through the time-sharing driving subunit 15. That is, the n Data signal lines Data share one Data signal generating subunit 14. The time-sharing driving sub-unit 15 is configured to time-share supply the Data voltages output by the Data signal generating sub-unit 14 to the n Data signal lines Data. That is, the time-division driving subunit 15 may supply the Data voltage output by the Data signal generating subunit 14 to one or more of the n Data signal lines Data at a certain timing.

Illustratively, the time-division driving subunit 15 is connected to n control signal lines SW, which correspond one-to-one to n data signal lines D. The time-division driving subunit 15 is configured to supply the data voltage output by the data signal generating subunit 14 to the corresponding data signal line D under the control of each control signal line SW. For example, as shown in fig. 8, n is 3,3 control signal lines, which are respectively a first control signal line SW1, a second control signal line SW2 and a third control signal line SW3, the first control signal line SW1 corresponds to the first data signal line D1, the second control signal line SW2 corresponds to the second data signal line D2, and the third control signal line SW3 corresponds to the third data signal line D3. The time-sharing driving subunit 15 supplies the data voltage output by the data signal generating subunit 14 to the first data signal line D1 under the control of the first control signal line SW 1; the time-sharing driving subunit 15 provides the data voltage output by the data signal generating subunit 14 to the second data signal line D2 under the control of the second control signal line SW 2; the time-division driving sub-unit 15 supplies the data voltage output by the data signal generating sub-unit 14 to the third data signal line D3 under the control of the third control signal line SW 3.

Illustratively, as shown in fig. 8, the time-sharing driving subunit 15 may include n switching devices, for example, a first switching device, a second switching device, and a third switching device. The first control signal line SW1 is connected to a control end of a first switching device, and the first switching device supplies the data voltage output by the data signal generating subunit 14 to the first data signal line D1 under the control of the first control signal line SW 1. The second control signal line SW2 is connected to a control terminal of a second switching device, and the second switching device provides the data voltage output by the data signal generating subunit 14 to the second data signal line D2 under the control of the second control signal line SW 2. The third control signal line SW3 is connected to a control terminal of a third switching device, and the third switching device supplies the data voltage output by the data signal generating subunit 14 to a third data signal line D3 under the control of the third control line signal line SW 3.

Fig. 9 is a timing diagram of the circuit of fig. 8. As shown in fig. 8 and 9, the n control signal lines sequentially supply the active level, so that the time-division driving subunit 15 sequentially supplies the data voltages output by the data signal generating subunit to the n data signal lines. That is, the time-division driving subunit 15 sequentially supplies the data voltages output by the data signal generating subunit to the 3 data signal lines at the active levels of the first control signal line SW1, the second control signal line SW2, and the third control signal line SW 3.

In the embodiments shown in fig. 8 and 9, the control manner of the scan signal is the same as that of the embodiments shown in fig. 6 and 7, and is not repeated here.

Illustratively, the first switching device, the second switching device and the third switching device may employ switching transistors, or other devices that can implement a switching function. The active state of the control signal line shown in fig. 9 is a high level, and it is understood that the active state of the control signal line may be determined according to the type of the switching device.

Fig. 10 is a schematic diagram of a pixel driving circuit according to another embodiment of the disclosure, and fig. 10 shows two rows and two columns of LED chips. In one embodiment, as shown in fig. 3 and 10, the pixel driving circuit may include n scanning signal lines G, each of which is connected to each of the scanning signal terminals Gate in a one-to-one correspondence, the scanning signal lines being configured to supply a scanning signal to the corresponding scanning signal terminal. For example, in the case where n is 3, the pixel driving circuit may include 3 scanning signal lines, respectively, a first scanning signal line G1, a second scanning signal line G2, and a third scanning signal line G3. The first scanning signal line G1 is connected to the first scanning signal terminal Gate1 to supply a scanning signal to the first scanning signal terminal Gate 1; the second scanning signal line G2 is connected to the second scanning signal terminal Gate2 to provide a scanning signal to the second scanning signal terminal Gate 2; the third scan signal line G3 is connected to the third scan signal terminal Gate3 to supply a scan signal to the third scan signal terminal Gate 3.

In the embodiment shown in fig. 10, n scan signal lines, which may be independent of each other, may be connected to n gate driving circuits (GOAs) in a one-to-one correspondence, so that each GOA may provide a scan signal to the corresponding scan signal line.

For example, as shown in fig. 10, the LED chips located in the same row may share n scanning signal lines.

In one embodiment, as shown in fig. 10, the pixel driving circuit may further include a Data signal line D connected to each of the n Data signal terminals Data to simultaneously supply the Data voltages to the n Data signal terminals Data.

FIG. 11 is a timing diagram of the circuit of FIG. 10. As shown in fig. 10 and 11, for one LED chip, the Data signal line D provides Data signals to the Data signal terminals Data of n light-on control units at the same time, and the n scanning signal lines G provide scanning signals to the n scanning signal terminals Gate respectively, so as to control whether the Data signals of the Data signal terminals Data are written into the corresponding switch control units, thereby implementing different gray scale display of the LED chip. As can be seen from fig. 11, when the scan signal line G provides an active level, a data voltage is written into the corresponding on control unit to control the corresponding LED chip to operate.

It is to be understood that the active level of the scanning signal line G shown in the timing diagram is 1, and it is to be understood that the active level of the scanning signal line G may be determined according to the type of the first transistor T1 in the writing subunit, for example, the active level of the scanning signal line G may be 1 when the first transistor T1 is NMOS, and the active level of the scanning signal line G may be 0 when the first transistor T1 is PMOS.

The embodiment of the disclosure also provides a driving method of the pixel driving circuit. According to the above content of the pixel driving circuit in the embodiment of the present disclosure, the LED chip can realize more than 256 gray scales by using the pixel driving circuit in the embodiment of the present disclosure. The display gray scale of the LED chip is related to the selected light emitting part and the data voltage of the data signal terminal, so it can be understood that there is a corresponding relationship between the display gray scale of the LED chip and each state of the n scanning signal terminals and each data voltage of the n data signal terminals, and a display gray scale table of the LED chip can be established according to the corresponding relationship, where the display gray scale table of the LED chip shows the corresponding relationship between the display gray scale of the LED chip and each state of the n scanning signal terminals and each data voltage of the n data signal terminals. When the LED chip is required to display a certain gray scale, the state of each scanning signal end and the data voltage of each data signal end can be obtained from the LED chip display gray scale table, and the state of each scanning signal end and the data voltage of each data signal end are set according to the LED chip display gray scale table, so that the LED chip performs gray scale display.

The driving method of the pixel driving circuit of the embodiment of the present disclosure includes:

the LED chip gray scale table comprises a display gray scale of the LED chip, states of the n scanning signal ends and corresponding relations of data voltages of the n data signal ends.

Fig. 12 isbase:Sub>A schematic plan view ofbase:Sub>A display substrate according to an embodiment of the disclosure, fig. 13base:Sub>A isbase:Sub>A schematic sectional view taken along linebase:Sub>A-base:Sub>A in fig. 12, and fig. 13B isbase:Sub>A schematic sectional view taken along line B-B in fig. 12. The display substrate according to the embodiment of the present disclosure further includes, as shown in fig. 12, 13a and 13b, an LED chip, one LED chip shown in fig. 12, where the LED chip includes n light emitting portions D, and the display substrate includes a substrate 21, n first semiconductor layers 221, n Multiple Quantum Wells (MQW) layers 231, and n second semiconductor layers 241. The n first semiconductor layers 221 are located on one side of the substrate 21. The n mqw layers 231 are located on the side of the n first semiconductor layers 221 away from the substrate 21, and the n mqw layers 231 correspond to the n first semiconductor layers 221 one to one. The n second semiconductor layers 241 are located on the side of the n multiple quantum well layers 231 away from the substrate 21, and the n second semiconductor layers 241 correspond to the n multiple quantum well layers 231 one to one. Each light emitting section D includes a first semiconductor layer 221, a multiple quantum well layer 231, and a second semiconductor layer 241, which are stacked in order and correspond to each other. The overlapping region in the stacking direction of the first semiconductor layer 221, the multiple quantum well layer 231, and the second semiconductor layer 241 is basically a light emitting region of the light emitting portion, and the area of the overlapping region in the stacking direction of the three layers is basically a light emitting area of the light emitting portion. It is understood that the pattern shape and area of the n first semiconductor layers 221 may be different from each other, the pattern and area of the n multi-quantum well layers 231 may be different from each other, and the pattern and area of the n second semiconductor layers 241 may be different from each other. The pattern shape and the area of each first semiconductor layer 221, each multiple quantum well layer 231, and each second semiconductor layer 241 can be set as required.

It is understood that, for one light emitting portion D, the orthographic projection of the multiple quantum well layer 231 on the substrate 21 is within the range of the orthographic projection of the first semiconductor layer 221 on the substrate 21, and the orthographic projection of the second semiconductor layer 241 on the substrate 21 is within the range of the orthographic projection of the multiple quantum well layer 231 on the substrate 21. Exemplarily, the first semiconductor layer 221 may be regarded as a cathode of the light emitting portion, and the second semiconductor layer 241 may be regarded as an anode of the light emitting portion; alternatively, the first semiconductor layer may be regarded as a cathode of the light-emitting portion, and the second semiconductor layer may be regarded as a cathode of the light-emitting portion.

As shown in fig. 12, 13a and 13b, the first semiconductor layer of the i-th light emitting part is connected to the second semiconductor layer of the i + 1-th light emitting part, the first semiconductor layer of the n-1-th light emitting part is connected to the first semiconductor layer of the n-th light emitting part, the second semiconductor layer of the n-th light emitting part is connected to the second semiconductor layer of the first light emitting part, n is a positive integer of 3 or more, and i is an integer of 1 to (n-2). In the embodiment shown in fig. 12, n is 4.

In one embodiment, as shown in fig. 12, 13a and 13b, the display substrate may further include a first insulating layer 25 and a bridge metal layer 26. The first insulating layer 25 is located on the side of the second semiconductor layer 241 facing away from the substrate 21. The orthographic projections of the light emitting parts D on the substrate 21 are all within the range of the orthographic projection of the first insulating layer 25 on the substrate 21. The first insulating layer 25 is provided with n-2 first via holes 251, the n-2 first via holes 251 are in one-to-one correspondence with the first to n-2 first semiconductor layers 221, and the first via holes 251 are used for exposing the corresponding first semiconductor layers 221. The first insulating layer 25 is further provided with n second via holes 252, the n second via holes 252 correspond to the n second semiconductor layers 241 one by one, and the second via holes 252 are used for exposing the corresponding second semiconductor layers 241. It is understood that the pattern and area of the n-2 first vias 251 may be different, and the pattern and area of the n second vias 252 may be different.

The bridge metal layer 26 is located on a side of the first insulating layer 25 facing away from the substrate 21, and the bridge metal layer 26 includes n-2 first bridge lines 261 and one second bridge line 262. The first bridge line 261 sequentially connects the corresponding ith first semiconductor layer 221 and the (i + 1) th second semiconductor layer 241 through the first via hole 251 and the second via hole 252. That is, the first bridge line 261 positioned between the ith light emitting part and the (i + 1) th light emitting part is connected to the ith first semiconductor layer 221 through the first via hole 251 corresponding to the ith first semiconductor layer 221 and connected to the (i + 1) th second semiconductor layer 241 through the second via hole 252 corresponding to the (i + 1) th second semiconductor layer 241, and thus the first bridge line 261 connects the ith first semiconductor layer 221 and the (i + 1) th second semiconductor layer 241. It is understood that the pattern shape and area of the n-2 first bridge threads 261 may be different from each other, and the pattern shape and area of each first bridge thread 261 may be set as desired.

In one embodiment, as shown in fig. 13a, in each light emitting portion, an orthographic projection of the multi-quantum well layer 231 on the substrate 21 is smaller than an orthographic projection of the first semiconductor layer 221 on the substrate 21, so that the first via hole 251 can be disposed on a side surface of the first semiconductor layer 221 facing away from the substrate 21, so that the first bridge line 261 can be lapped on an upper surface of the corresponding first semiconductor layer 221 through the first via hole 251. For example, the first bridge line 261 may extend directly to the second via hole 252 to be connected with the (i + 1) th second semiconductor layer 241.

In one embodiment, as shown in fig. 13a, the orthographic projection of the second via 252 on the substrate 21 is within the range of the orthographic projection of the second semiconductor layer 241 on the substrate. The display substrate may further include a transparent conductive layer 27, the transparent conductive layer 27 including n electrode connection lines 271, each electrode connection line 271 being connected to the corresponding second semiconductor layer 241 through each second via hole 252. The second bridge line 262 is connected to both the first electrode connection line 271 and the nth electrode connection line 271, and thus the second bridge line 262 connects the second semiconductor layer 241 of the first light emitting portion and the second semiconductor layer 241 of the nth light emitting portion. The first bridge lines 261 are connected to the corresponding second semiconductor layers 241 through the corresponding electrode connection lines 271 and the second vias 252. It is understood that the pattern shape and area of the n electrode connection lines 271 may be different from each other, and the pattern shape and area of each electrode connection line 271 may be set as desired.

In this arrangement, the first bridge line 261 and the second bridge line 262 do not block the multi-quantum well layer 231 of the light emitting section, and do not affect the effective light emitting area of the light emitting section.

In one embodiment, as shown in fig. 13a, the display substrate may further include a second insulating layer 28, the second insulating layer 28 is located on a side of the transparent conductive layer 27 away from the substrate 21, and the orthographic projection of each light-emitting portion D on the substrate 21 is located within the range of the orthographic projection of the second insulating layer 28 on the substrate 21. The display substrate may further comprise an encapsulation layer 29, the encapsulation layer 29 being located on a side of the second insulating layer 28 facing away from the substrate 21, an orthographic projection of the second insulating layer 28 on the substrate 21 being within the range of an orthographic projection of the encapsulation layer 29 on the substrate 21. The surface of the encapsulation layer 29 on the side facing away from the substrate 21 may be a flat surface. The display substrate further comprises n-2

third vias

43, 1 fourth via 44 and 1 fifth via 45, the third vias 43, the fourth vias 44 and the fifth vias 45 all passing through the encapsulation layer 29 and the second insulating layer 28. The n-2 third via holes 43 correspond to the n-2 first bridge lines 261 one-to-one and expose the corresponding first bridge lines 261, the nth first semiconductor layer 221 is exposed by the fourth via hole 44, and the second bridge line 262 is exposed by the fifth via hole 45. It is understood that the pattern and area of the n-2 third vias 43 may be different, and the pattern and area of the n-2 third vias 43 may be set as desired.

In one embodiment, as shown in fig. 13a and 13b, the display substrate may further include a metal interposer 30, and the metal interposer 30 is located on a side of the encapsulation layer 29 facing away from the substrate 21. The metal via layer 30 includes n power pads 31, and the first to n-2 th power pads 31 are in one-to-one correspondence with the n-2 first bridge lines 261 and are connected to the corresponding first bridge lines 261 through the corresponding third vias 43. The (n-1) th power pad 31 is connected to the first semiconductor layer 221 of the nth light emitting part through the fourth via hole 44. The nth power pad 31 is connected to the second bridge line 262 through the fifth via hole 45. It is understood that the pattern shape and area of the n power pads 31 may be different from each other, and the pattern shape and area of each power pad 31 may be set as desired.

The technical solution of the embodiment of the present disclosure is further described by the preparation process of the display substrate in an embodiment of the present disclosure, and in the following embodiment, n =4. It is to be understood that "patterning" as used herein includes processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. when the material to be patterned is an inorganic material or a metal, and processes of mask exposure, development, etc. when the material to be patterned is an organic material, and evaporation, deposition, coating, etc. as used herein are well-known preparation processes in the related art.

A first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer are sequentially formed on a substrate. Fig. 14 isbase:Sub>A schematic plan view showingbase:Sub>A second semiconductor layer formed onbase:Sub>A substrate, fig. 15base:Sub>A isbase:Sub>A schematic sectional view taken along linebase:Sub>A-base:Sub>A in fig. 14, and fig. 15B isbase:Sub>A schematic sectional view taken along line B-B in fig. 14. This step may include: forming a first semiconductor thin film on one side of the substrate 21, and patterning the first semiconductor thin film to form 4 first semiconductor layers 221, wherein the 3 rd first semiconductor layer 221 is connected to the 4 th first semiconductor layer 221, or the 3 rd first semiconductor layer 221 and the 4 th first semiconductor layer 221 are integrated, as shown in fig. 14, 15a and 15 b; forming 4 multiple quantum well layers 231,4 multiple quantum well layers 231 on the side of the four first semiconductor layers 221 away from the substrate 21 in one-to-one correspondence with the 4 first semiconductor layers 221, as shown in fig. 14, 15a, and 15 b; the 4 second semiconductor layers 241,4 are formed on the side of the four multi-quantum well layers 231 away from the substrate 21 in one-to-one correspondence with the 4 multi-quantum well layers 231. Each light emitting section D includes a first semiconductor layer 221, a multiple quantum well layer 231, and a second semiconductor layer 241, which are stacked in order and correspond to each other. The thicknesses of the first semiconductor layer, the multiple quantum well layer, and the second semiconductor layer may be set according to actual needs, and are not limited herein.

A first insulating layer 25 is formed on the side of the second semiconductor layer 241 facing away from the substrate 21. Fig. 16 isbase:Sub>A schematic plan view showingbase:Sub>A substrate afterbase:Sub>A first insulating layer is formed thereon, fig. 17base:Sub>A isbase:Sub>A schematic sectional view taken along linebase:Sub>A-base:Sub>A in fig. 16, and fig. 17B isbase:Sub>A schematic sectional view taken along line B-B in fig. 16. This step may include: as shown in fig. 16, 17a, and 17b, a first insulating film is formed on the second conductive layer 24 on the side away from the substrate 21, and the first insulating film is patterned to form a first insulating layer 25, and the orthographic projection of each light emitting portion D on the substrate 21 is located within the range of the orthographic projection of the first insulating layer 25 on the substrate 21. The first insulating layer 25 is provided with 2 first via

holes

251,2, the first via holes 251 are in one-to-one correspondence with the first to 2 nd first semiconductor layers 221, and the first via holes 251 are used for exposing the corresponding first semiconductor layers 221. The first insulating layer 25 is further provided with 4 second via holes 252,4, the second via holes 252 correspond to the 4 second semiconductor layers 241 one by one, and the second via holes 252 are used for exposing the corresponding second semiconductor layers 241. The thickness of the first insulating layer may be set according to actual needs, and is not limited herein.

A bridging metal layer 26 is formed on the side of the first insulating layer 25 facing away from the substrate 21. FIG. 18 isbase:Sub>A schematic plan view showingbase:Sub>A substrate afterbase:Sub>A bridge metal layer is formed thereon, FIG. 19base:Sub>A isbase:Sub>A schematic sectional view taken along line A-A in FIG. 18, and FIG. 19B isbase:Sub>A schematic sectional view taken along line B-B in FIG. 18. This step may include: as shown in fig. 18, 19a and 19b, the bridge metal layer 26 includes 2 first bridge lines 261 and one second bridge line 262, and is formed by forming a bridge metal film on a side of the first insulating layer 25 away from the substrate 21 and patterning the bridge metal film. The first bridge line 261 sequentially connects the corresponding 1 st first semiconductor layer 221 and the corresponding 2 nd second semiconductor layer 241 through the first via hole 251 and the second via hole 252, and connects the second first semiconductor layer 221 and the 3 rd second semiconductor layer 241. That is, the first bridge line 261 positioned between the 1 st light emitting part and the 2 nd light emitting part is connected to the 1 st first semiconductor layer 221 through the first via hole 251 corresponding to the 1 st first semiconductor layer 221 and connected to the 2 nd second semiconductor layer 241 through the second via hole 252 corresponding to the 2 nd second semiconductor layer 241, and thus the first bridge line 261 connects the 1 st first semiconductor layer 221 and the 2 nd second semiconductor layer 241.

A transparent conductive layer 27 is formed on the side of the bridge metal layer 26 facing away from the substrate 21. Fig. 20 isbase:Sub>A schematic plan view showingbase:Sub>A transparent conductive layer formed onbase:Sub>A substrate, fig. 21base:Sub>A isbase:Sub>A schematic sectional view taken along linebase:Sub>A-base:Sub>A in fig. 20, and fig. 21B isbase:Sub>A schematic sectional view taken along line B-B in fig. 20. This step may include: as shown in fig. 20, 21a and 21b, the transparent conductive layer 27 is formed by forming a transparent conductive film on the side of the bridging metal layer 26 away from the substrate 21 and patterning the transparent conductive film, and the transparent conductive layer 27 includes 4 electrode connection lines 271, and each electrode connection line 271 is connected to the corresponding second semiconductor layer 241 through each second via hole 252. The second bridge line 262 is connected to both the first electrode connection line 271 and the 4 th electrode connection line 271, and thus, the second bridge line 262 connects the second semiconductor layer 241 of the first light emitting portion and the second semiconductor layer 241 of the 4 th light emitting portion. The first bridge lines 261 are connected to the corresponding second semiconductor layers 241 through the corresponding electrode connection lines 271 and the second via holes 252.

A second insulating layer 28 and an encapsulation layer 29 are formed in this order on the side of the transparent conductive layer 27 facing away from the substrate 21. Fig. 22 isbase:Sub>A schematic plan view showingbase:Sub>A transparent conductive layer formed onbase:Sub>A substrate, fig. 23base:Sub>A isbase:Sub>A schematic sectional view taken along linebase:Sub>A-base:Sub>A in fig. 22, and fig. 23B isbase:Sub>A schematic sectional view taken along line B-B in fig. 22. This step may include: a second insulating layer 28 is formed on a side of the transparent conductive layer 27 away from the substrate 21, and the second insulating layer 28 is provided with 2 first sub-via holes, 1 third sub-via hole, and 1 fifth sub-via hole. The 2 first sub-via holes correspond to the 2 first bridge lines 261 one by one, and the first sub-via holes expose the corresponding first bridge lines 261; the third sub-via hole corresponds to the 4 th first semiconductor layer 221 and exposes the corresponding first semiconductor layer 221; the fifth sub-via corresponds to the second bridge line 262 and exposes the second bridge line 262. A package layer 29 is formed on a side of the second insulating layer 28 away from the substrate 21, the package layer 29 is provided with a second sub-via corresponding to the first sub-via, a fourth sub-via corresponding to the third sub-via, and a sixth sub-via corresponding to the fifth sub-via, the first sub-via and the second sub-via form a third via 43, the third sub-via and the fourth sub-via form a fourth via 44, the fifth sub-via and the sixth sub-via form a fifth via 45,2, the third via 43 corresponds to the 2 first bridge lines 261 one by one, the third via 43 exposes the corresponding first bridge line 261, the fourth via 44 exposes the 4 th first semiconductor layer 221, and the fifth via 45 exposes the second bridge line 262, as shown in fig. 22, 23a and 23 b.

A metal interposer layer 30 is formed on the side of the encapsulation layer 29 facing away from the substrate 21, as shown in fig. 12, 13a and 13 b. This step may include: a power metal film is formed on a side of the encapsulation layer 29 away from the substrate 21, the power metal film is patterned to form 4 power pads 31, the first power pad 31 (V2) and the second power pad 31 (V3) are respectively connected to the corresponding first bridge line 261 through the corresponding third via hole 43, the third power pad 31 (V4) is connected to the fourth first semiconductor layer 221 through the fourth via hole 44, and the fourth power pad 31 (V1) is connected to the second bridge line 262 through the fifth via hole 45, as shown in fig. 12, 13a and 13 b. The thickness of the metal transition layer 30 can be set as desired, and is not particularly limited.

For example, the Light Emitting Diode chip may be a sub-millimeter Light Emitting Diode (Mini LED) chip, or may be a Micro Light Emitting Diode (Micro LED) chip.

In an exemplary embodiment, the substrate 21 may be, for example, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, a silicon-based substrate, a silicon carbide substrate, a sapphire substrate, or the like. The doping types of the first semiconductor layer 221 and the second semiconductor layer 241 may be different, the first semiconductor layer 221 may be N-type doped gallium nitride (N-GaN), and the second semiconductor layer 241 may be P-type doped gallium nitride (P-GaN); alternatively, the first semiconductor layer 221 may be P-type doped gallium nitride (P-GaN), and the second semiconductor layer 241 may be N-type doped gallium nitride (N-GaN). The materials of the first semiconductor layer 221 and the second semiconductor layer 241 include a variety of materials, and can be selected according to actual needs. Illustratively, the intrinsic semiconductor material in the first and second semiconductor layers 221 and 241 is the same, and may be any one of GaN, gaP, aluminum gallium arsenide (AlGaAs), and aluminum gallium indium phosphide (AlGaInP).

In an exemplary embodiment, the first and second insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The bridge metal layer 26 and the power pad 31 may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, or the like. The transparent conductive layer 27 may be made of a transparent conductive material, such as indium tin oxide, indium zinc oxide, or the like. The encapsulation layer 29 may use an organic material such as an organic resin or the like. The thickness of each film layer can be set as desired.

FIG. 24b is a schematic plan view illustrating a display substrate after a first insulating layer is formed thereon according to another embodiment of the present disclosure; FIG. 24c is a schematic plan view illustrating a transparent conductive layer formed on a display substrate according to another embodiment of the present disclosure; FIG. 24d is a schematic plan view of a display substrate according to another embodiment of the present disclosure after an encapsulation layer is formed thereon; FIG. 24e is a schematic plan view illustrating a substrate with a metal via layer formed thereon according to another embodiment of the present disclosure; fig. 25a is a schematic cross-sectional view taken at C-C in fig. 24e, and fig. 25b is a schematic cross-sectional view taken at D-D in fig. 24 e. In the disclosed embodiment, n =3, i.e. the LED chip includes 3 light emitting portions D, D1, D2 and D3 respectively. The process for manufacturing the display substrate can refer to the process for manufacturing the display substrate in the embodiment shown in fig. 14 to 23, and is not repeated herein. As shown in fig. 24a to 24e and fig. 25a and 25b, the display substrate includes 3 first semiconductor layers 221, 3 multi-quantum well layers 231, and 3 second semiconductor layers 241. The first semiconductor layer 221 of the 1 st light emitting section D1 is connected to the second semiconductor layer 241 of the 2 nd light emitting section D2, the first semiconductor layer 221 of the 2 nd light emitting section D2 is connected to the first semiconductor layer 221 of the 3 rd light emitting section D3, and the second semiconductor layer 241 of the 3 rd light emitting section D3 is connected to the second semiconductor layer 241 of the first light emitting section D1. The first insulating layer 25 is formed with 1 first via hole 251, the first via hole 251 corresponds to the first semiconductor layer 221, and the first via hole 251 is used for exposing the first semiconductor layer 221 of the first light emitting portion D1. The first insulating layer 25 is further provided with 3 second via holes 252,3, wherein the second via holes 252 correspond to the 3 second semiconductor layers 241 one by one, and the second via holes 252 are used for exposing the corresponding second semiconductor layers 241. The bridge metal layer 26 includes 1 first bridge line 261 and one second bridge line 262. The first bridge line 261 connects the first semiconductor layer 221 of the corresponding 1 st light emitting portion D1 and the second semiconductor layer 241 of the 2 nd light emitting portion D2 through the first via hole 251 and the second via hole 252.

The transparent conductive layer 27 includes 3 electrode connection lines 271, and each electrode connection line 271 is connected to the corresponding second semiconductor layer 241 through each second via 252. The second bridge line 262 is connected to both the first electrode connection line 271 and the 3 rd electrode connection line 271, and thus, the second bridge line 262 connects the second semiconductor layer 241 of the first light emitting part D1 and the second semiconductor layer 241 of the 3 rd light emitting part D3. The first bridge line 261 is connected to the second semiconductor layer 241 of the second light emitting section D2 through the corresponding electrode connection line 271 and the second via hole 252. The display substrate further includes 1 third via 43, 1 fourth via 44, and 1 fifth via 45, each of the third via 43, the fourth via 44, and the fifth via 45 passing through the encapsulation layer 29 and the second insulating layer 28. The third via hole 43 corresponds to the first bridging line 261 and exposes the corresponding first bridging line 261, the fourth via hole 44 exposes the first semiconductor layer 221 of the 3 rd light emitting part D3 or the 2 nd light emitting part D2, and the fifth via hole 45 exposes the second bridging line 262.

The metal transfer layer 30 includes 3 power pads 31, and the first power pads 31 (V2) are in one-to-one correspondence with the first bridging lines 261 and are connected to the first bridging lines 261 through the corresponding third vias 43. The 2 nd power pad 31 (V3) is connected to the first semiconductor layer 221 of the 3 rd light emitting part D3 through the fourth via hole 44. The 3 rd power pad 31 (V1) is connected to the second bridge line 262 through the fifth via 45.

Based on the inventive concept of the foregoing embodiments, an embodiment of the present disclosure further provides a display device, where the display device includes the pixel driving circuit or the display substrate in any embodiment of the present disclosure, and further includes a driving backplane. The n switch control units in the pixel driving circuit are arranged in the driving back plate. The display substrate is attached to the driving back plate, the power pads 31 in the display substrate face the driving back plate, and the driving back plate provides electric signals for the corresponding power pads 31.

The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integral with; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, comprising:

the n switch control units are respectively connected with a jth driving power supply end, a jth data signal end, a jth scanning signal end and a public power supply end, and are configured to receive a data voltage of the jth data signal end under the control of the jth scanning signal end and provide an electric signal to the corresponding access point based on the voltage of the jth driving power supply end so as to drive at least one light emitting part to work, wherein j is an integer of 1~n;

wherein, the n switch control units drive different or different numbers of the light emitting parts to work.

2. The pixel driving circuit according to claim 1, further comprising n data signal lines, each of the data signal lines being connected in one-to-one correspondence with each of the data signal terminals, the data signal lines being configured to supply a data voltage to the corresponding data signal terminal.

3. The pixel driving circuit according to claim 2, further comprising a data signal generating subunit and a time-sharing driving subunit, wherein the data signal generating subunit is connected to the n data signal lines through the time-sharing driving subunit, and the time-sharing driving subunit is configured to time-share supply the data voltage output by the data signal generating subunit to the n data signal lines.

4. The pixel driving circuit according to claim 2, further comprising a scanning signal line connected to each of the n scanning signal terminals to supply a scanning signal to the n scanning signal terminals.

5. The pixel driving circuit according to claim 1, wherein the pixel driving circuit comprises n scanning signal lines, each scanning signal line is connected to each scanning signal terminal in a one-to-one correspondence, and the scanning signal lines are configured to provide scanning signals to the corresponding scanning signal terminals.

6. The pixel driving circuit according to claim 5, wherein the pixel driving circuit comprises a data signal line, and the data signal line is connected to each of the n data signal terminals to supply a data voltage to the n data signal terminals.

7. The pixel driving circuit according to claim 1,

8. The pixel driving circuit according to any one of claims 1 to 7, wherein the switching control unit includes:

a write subunit, connected to the jth data signal terminal, the jth scan signal terminal, and a first node, respectively, and configured to provide a data voltage of the jth data signal terminal to the first node under the control of the jth scan signal terminal;

a driving sub-unit respectively connected to the jth driving power supply terminal, the access point, and the first node, and configured to supply an electrical signal to the access point based on a voltage of the jth driving power supply terminal under control of the first node;

a memory sub-unit connected to the first node and the common power source terminal, respectively, configured to store charge of the first node.

9. The pixel driving circuit according to claim 8,

the driving subunit comprises a second transistor, a gate of the second transistor is connected with the first node, a first pole of the second transistor is connected with the jth driving power supply end, and a second pole of the second transistor is connected with the access point;

the storage subunit comprises a storage capacitor, and two polar plates of the storage capacitor are respectively connected with the first node and the common power supply end.

10. A driving method of a pixel driving circuit, applied to the pixel driving circuit according to any one of claims 1 to 9, the method comprising:

11. A display substrate comprising an LED chip including n light emitting parts each including a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer which are laminated, the display substrate comprising:

a substrate;

n first semiconductor layers located on one side of the substrate;

the n second semiconductor layers are positioned on one sides of the n multi-quantum well layers, which are far away from the substrate, and correspond to the n multi-quantum well layers one to one;

wherein the first semiconductor layer of the ith luminous part is connected with the second semiconductor layer of the (i + 1) th luminous part, the first semiconductor layer of the (n-1) th luminous part is connected with the first semiconductor layer of the nth luminous part, the second semiconductor layer of the nth luminous part is connected with the second semiconductor layer of the first luminous part, a connection point of every two luminous parts forms an access point, n is a positive integer greater than or equal to 3, and i is 1 to (n-2);

the display substrate further comprises n light-emitting control units, each switch control unit is connected with each access point in a one-to-one correspondence manner, the switch control units are respectively connected with a jth driving power supply end, a jth data signal end, a jth scanning signal end and a public power supply end, the switch control units are configured to receive data voltage of the jth data signal end under the control of the jth scanning signal end, provide electric signals for the corresponding access points based on the voltage of the jth driving power supply end so as to drive at least one light-emitting part to work, and drive different or different numbers of light-emitting parts to work through the n light-emitting control units, wherein j is an integer of 1~n.

12. The display substrate according to claim 11, further comprising:

the bridging metal layer is positioned on one side, away from the substrate, of the first insulating layer and comprises n-2 first bridging lines and one second bridging line, the n-2 first bridging lines sequentially connect the corresponding ith first semiconductor layer with the (i + 1) th second semiconductor layer through the first via hole and the second via hole, and the second bridging lines connect the first second semiconductor layer with the nth second semiconductor layer through the first second via hole and the nth second via hole.

13. The display substrate according to claim 12, wherein an orthographic projection of the second via hole on the substrate is within an orthographic projection of the second semiconductor layer on the substrate, the display substrate further comprises a transparent conductive layer, the transparent conductive layer comprises n electrode connection lines, each electrode connection line is connected with the corresponding second semiconductor layer through each second via hole, the first bridging line is connected with the corresponding second semiconductor layer through the corresponding electrode connection line and the second via hole, and the second bridging line is connected with both the first electrode connection line and the nth electrode connection line.

14. A display device comprising the pixel driving circuit according to any one of claims 1 to 9 or the display substrate according to any one of claims 11 to 13.