CN113517261B - Semiconductor structure, electronic device and method - Google Patents
Semiconductor structure, electronic device and method Download PDFInfo
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- CN113517261B CN113517261B CN202010276077.7A CN202010276077A CN113517261B CN 113517261 B CN113517261 B CN 113517261B CN 202010276077 A CN202010276077 A CN 202010276077A CN 113517261 B CN113517261 B CN 113517261B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 22
- 238000012545 processing Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor structure, an electronic device and a method, comprising: a wiring layer including a metal wiring; and a shielding layer on the wiring layer, wherein the shielding layer comprises one or more shielding areas, each shielding area covers the metal wiring below the shielding area and corresponds to the shielding area, and the shielding areas are electrically connected with the metal wiring through a through hole. By depositing a shielding layer on the wiring layer and connecting the final wiring layer to the ground pad, the shielding effect can be maximized, the soft error rate generated by alpha particles can be minimized, the stability and performance of the product can be improved, the system or signal processing is not required to be executed again, and the time required for eliminating soft errors can be reduced.
Description
Technical Field
The present application relates to semiconductor memory devices, and more particularly, to a semiconductor structure, an electronic device, and a method.
Background
With the miniaturization of semiconductor process technology, soft Error (Soft Error) generated by Alpha particles (Alpha particles) may affect the action of the product. As shown in fig. 1 and 2, as described above, the α particles generate electron-hole pairs (Electron Hole Pair) after entering the Channel (Channel), resulting in a bad problem that the output is independent of the input signal. This is not a fixed defect, but rather occurs only when alpha particles enter the channel, and is therefore called a soft error.
Soft errors cannot be prevented from the circuit, and can be confirmed by a Parity Check method, and if it is confirmed that a failure occurs, the problem can be solved by re-executing signal processing or re-executing a system. However, if a soft error occurs, there is a problem in that the execution time of the re-execution instruction becomes long. Therefore, how to prevent soft errors generated by alpha particles and ensure the performance of products becomes the key point of technical problems and constant researches to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned problems, the present application provides a semiconductor structure, including: a wiring layer including a metal wiring; and a shielding layer on the wiring layer, wherein the shielding layer comprises one or more shielding areas, each shielding area covers the metal wiring below the shielding area and corresponds to the shielding area, and the shielding areas are electrically connected with the metal wiring through a through hole.
In view of the above problems, the present application further provides an electronic device including the above semiconductor structure.
In view of the above problems, the present application further provides a method for manufacturing a semiconductor structure, including: forming a device layer and one or more wiring layers on a substrate; forming a shielding layer on the wiring layer; a pad layer is formed on the shielding layer.
The application has the advantages that: compared with the traditional mode, the semiconductor structure provided by the application can minimize the Soft Error Rate (SER) generated by alpha particles, improve the stability and performance of products, avoid executing a system or signal processing again, and reduce the time required for eliminating Soft errors.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
fig. 1 shows a schematic cross-sectional view of an alpha particle that would generate electron-hole pairs after entering the channel of a transistor.
FIG. 2 shows a schematic cross-sectional view of an alpha particle entering the channel of a transistor of a DRAM that would generate electron-hole pairs;
fig. 3 shows a schematic diagram of a manufacturing step of a peripheral device of a conventional semiconductor structure;
fig. 4 shows a schematic view of a semiconductor structure of an embodiment of the present application;
FIG. 5 illustrates a schematic top view of a pad layer and a shield layer of a semiconductor structure of an embodiment of the present application;
FIG. 6 illustrates a schematic top view of a pad layer and a shield layer of another semiconductor structure of an embodiment of the present application;
fig. 7 shows a schematic step diagram of a method of manufacturing a semiconductor structure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
As shown in fig. 1, when α particles enter the channel of the transistor, electron-hole pairs 1 are generated, and the transistor is erroneously operated. This malfunction is called soft error since it occurs only when alpha particles enter the channel. Transistors that generate soft errors caused by alpha particles can function properly after other signals are input.
Such soft errors occur in a Transistor Cell (Cell Transistor) or logic circuit of a Static Random-Access Memory (SRAM), but as a micro process progresses in a dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), soft errors also occur in the DRAM, as shown in fig. 2, which is a schematic diagram of the entry of alpha particles into a short channel small width Transistor (Short Channel Small Width Transistor) in the dynamic Random Access Memory.
As shown in fig. 3, the conventional DRAM structure includes: a substrate 110, a device Layer 120, a Routing Layer 130, and a pad Layer 140. Wherein the pad layer 140 is electrically connected to the metal wiring 135 of the wiring layer 130 through a via hole. The metal wiring 135 in the wiring layer 130 is electrically connected to the substrate 110 through a via hole. The wiring layer 130 may be a plurality of layers. The substrate 110 includes an isolation trench 111 and a first transistor 112. The device layer 120 includes a capacitor 121, a second transistor 122, and a conductive plug 101.
As shown in fig. 4, the semiconductor structure of the present application includes: a wiring layer 130, wherein the wiring layer 130 includes a metal wiring 131; a shielding layer 150 on the wiring layer 130, wherein the shielding layer 150 includes one or more shielding regions 151, and each shielding region 151 covers the metal wiring 131 thereunder. The shielding region 151 is electrically connected to the metal wiring 131 via a via hole.
The semiconductor structure of the present application further includes: and a pad layer 140 on the shielding layer 150, wherein the pad layer 140 includes one or more pads 141, and each pad 141 covers one or more shielding regions 151 thereunder and corresponding thereto. The ground pad 141a of the pads 141 is electrically connected to the shielding layer 150 via a via hole.
Also included on the substrate 110 is a first transistor 112; also included in the device layer 120 on the substrate 110 is a second transistor 122. The shielding layer 150 is located above the topmost wiring layer (final wiring layer) 130 of the wiring layers, and each shielding region 151 covers the metal wiring 131, the first transistor 112, and the second transistor 122 thereunder; one or more pads 141 located on the shielding layer 150 cover one or more shielding regions 151 thereunder and corresponding thereto. The non-ground pad 141b in the pad layer 140 is insulated from the shield layer 150. One end of the conductive plug 101 in the device layer 120 is connected to the metal wiring 131 in the wiring layer 130, and the other end is in contact with the substrate 110.
Gaps between the pads in the pad layer 140 are small, and the shielding regions 151 in the shielding layer 150 are completely covered by the pads 141 in the pad layer 140 corresponding thereto. Since the shield layer 150 serves to prevent α particles, each shield region 151 in the shield layer 150 needs to entirely cover the metal wiring 131 corresponding to each shield region 151 in the final wiring layer 130 thereunder. As shown in fig. 4, the ground pad 141a covers the shielding region 151a thereunder and is electrically connected to the shielding region 151a through the conductive plug 101 in the via hole. The non-ground pad 141b covers the shielding region 151b thereunder, but is not connected to the shielding region 151 b. The shielding region 151a is connected to the metal wiring 131a of the final wiring layer 131, and the shielding region 151b is connected to the metal wiring 131b of the final wiring layer 131. The thickness of the dielectric film between the final wiring layer 131 and the shielding layer 151 is greater than the thickness of the dielectric film between the final wiring layers. The pad layer 140 and the final wiring layer 131 are kept insulated from each other by filling the dielectric 102 material. Dielectric is filled between the shielding regions 151 in the shielding layer 150, dielectric is filled in the device layer 120, and a material of the dielectric film includes silicon nitride. The metal wiring includes: co, ni, cu, al, pd, pt, ru, re, mo, ta, ti, hf, zr, W, ir, eu, nd, er, la, or an alloy of these metals, or a nitride of these metals. The substrate is one of a silicon substrate, a silicon germanium substrate, or a III-V compound semiconductor substrate.
Fig. 7 illustrates a method of fabricating a semiconductor structure, an example method begins at operation 701 by forming a device layer 120 and one or more wiring layers 130 on a substrate 110. Continuing with operation 702, a shield layer 150 is formed on the wiring layer 130. Continuing with operation 703, a pad layer 140 is formed on the shield layer 150. Wherein the shield layer 150 is formed on the topmost wiring layer (final wiring layer) 130 among the wiring layers.
In order to prevent soft errors caused by the entrance of α particles into the transistor channel, when forming the shield layer 150, in order to prevent RC signal delay in the wiring layer 140 under the shield layer 150, it is necessary to use a technique of raising the dielectric film 102 between the shield layer 150 and the wiring layer, and to increase the thickness of the dielectric film 102.
However, when the thickness of the dielectric film 102 between the shield layer 150 and the wiring layer 140 is made large, there is a possibility that an increase in resistance occurs, resulting in a problem of delay of a signal or voltage drop, and therefore, it is necessary to fully open the portion where the pads 141 are formed, that is, each pad 141 in the pad layer 140 is an open pad for reducing contact resistance.
In order to prevent soft errors from occurring when alpha particles enter the transistor channel, when the shielding layer 150 is formed, if the assembly process uses a Wire Bonding (Wire Bonding) technique, a shielding region 151 forming the quadrangular pad 141 and the shielding layer 150 as shown in fig. 5 is formed.
In order to prevent soft errors from occurring when alpha particles enter the transistor channel, when the shielding layer 150 is formed, if the assembly process uses Flip chip (Flip chip) technology, the hexagonal bonding pads 141 and the shielding regions 151 of the shielding layer 150 are formed as shown in fig. 6.
In one embodiment, an electronic device may include the semiconductor structure described above.
The electronic equipment comprises a smart phone, a computer, a tablet personal computer, a wearable intelligent device, an artificial intelligent device, a mobile power supply and the like.
Soft errors frequently occur in space due to alpha particles generated by radiation outside the atmosphere. For this reason, in equipment such as space ships and airplanes, equipment to be protected is protected by a shield (Shielding Case) or the like in order to prevent soft errors. In the circuit aspect, the parity check can be used to detect errors, and when soft errors occur, signals are repeatedly input, so that the circuit can operate normally. Either generating an output signal or mirroring (Mirror) the storage, retrieving information from the storage on the other side. But this approach takes a long time to handle soft errors. In terms of the process, materials with low alpha particles are used, and the generation of alpha particles and the phenomenon of entering a transistor channel are reduced as much as possible. But this approach results in a smaller selection at the time of manufacture. In addition, a shielding layer for preventing α particles has been formed on the intermediate film of the metal wiring of the high-performance CPU. However, the use of such a shield layer is limited due to the process problems of the copper damascene method and the parasitic RC signal delay problems.
The shielding layer 150 connected with the grounding pad 141a is added on the wiring layer 130, so that the shielding effect is maximized, the soft error rate generated by alpha particles can be minimized, the stability and the performance of a product are improved, the system or the signal processing is not required to be executed again, and the time required for eliminating the soft error is reduced.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (11)
1. A semiconductor structure, comprising:
a wiring layer including a metal wiring;
a shielding layer on the wiring layer, the shielding layer including one or more shielding regions, each shielding region entirely covering the metal wiring thereunder and corresponding thereto, the shielding regions being electrically connected to the metal wiring via a via hole; further comprises:
a pad layer on the shielding layer, the pad layer including one or more pads, each pad covering one or more shielding regions thereunder corresponding thereto; the ground pad of the pads is electrically connected to the shielding layer via a via.
2. The semiconductor structure of claim 1, further comprising:
a substrate including a first transistor thereon;
a device layer on the substrate, the device layer including a second transistor therein;
the wiring layer is located on the device layer.
3. The semiconductor structure of claim 1, wherein a non-ground pad in the pad layer is insulated from the shield layer.
4. The semiconductor structure of claim 2, further comprising a conductive plug in the device layer, one end of the conductive plug connecting to a metal wiring in the wiring layer, the other end being in contact with the substrate.
5. The semiconductor structure of claim 1, wherein a topmost wiring layer is a final wiring layer; the thickness of the dielectric film between the final wiring layer and the shield layer is greater than the thickness of the dielectric film between the wiring layers.
6. The semiconductor structure of claim 1, wherein each pad in the pad layer is further quadrilateral or hexagonal.
7. The semiconductor structure of claim 1, wherein each shielding region in the shielding layer is filled with a dielectric.
8. The semiconductor structure of claim 1, wherein the metal wiring comprises: co, ni, cu, al, pd, pt, ru, re, mo, ta, ti, hf, zr, W, ir, eu, nd, er, la, or an alloy of these metals, or a nitride of these metals.
9. An electronic device comprising the semiconductor structure of any one of claims 1 to 8.
10. The electronic device of claim 9, comprising a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power source.
11. A method of manufacturing a semiconductor structure according to any one of claims 1 to 8, comprising:
forming a device layer and one or more wiring layers on a substrate;
forming a shielding layer on the wiring layer;
a pad layer is formed on the shielding layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010276077.7A CN113517261B (en) | 2020-04-09 | 2020-04-09 | Semiconductor structure, electronic device and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010276077.7A CN113517261B (en) | 2020-04-09 | 2020-04-09 | Semiconductor structure, electronic device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113517261A CN113517261A (en) | 2021-10-19 |
| CN113517261B true CN113517261B (en) | 2024-04-05 |
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| CN202010276077.7A Active CN113517261B (en) | 2020-04-09 | 2020-04-09 | Semiconductor structure, electronic device and method |
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| CN115799227B (en) * | 2023-01-10 | 2023-06-09 | 荣耀终端有限公司 | Bare chip, chip and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005033230A (en) * | 2004-10-28 | 2005-02-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| CN101548371A (en) * | 2005-07-18 | 2009-09-30 | 国际商业机器公司 | Method and structure for reduction of soft error rates in integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070045844A1 (en) * | 2005-08-24 | 2007-03-01 | Andry Paul S | Alpha particle shields in chip packaging |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005033230A (en) * | 2004-10-28 | 2005-02-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| CN101548371A (en) * | 2005-07-18 | 2009-09-30 | 国际商业机器公司 | Method and structure for reduction of soft error rates in integrated circuits |
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| CN113517261A (en) | 2021-10-19 |
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