CN113506540A - Pixel circuit beneficial to high-order display - Google Patents
Pixel circuit beneficial to high-order display Download PDFInfo
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- CN113506540A CN113506540A CN202110644652.9A CN202110644652A CN113506540A CN 113506540 A CN113506540 A CN 113506540A CN 202110644652 A CN202110644652 A CN 202110644652A CN 113506540 A CN113506540 A CN 113506540A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention belongs to the field of pixel circuits, and particularly relates to a pixel circuit beneficial to high-order display, which comprises an upper circuit and a lower circuit, wherein the upper circuit comprises a switch TFT T5, the lower circuit comprises a switch TFT T5 ', the TFT T5 is connected with a grid electrode of a TFT T5 ', and a common end of the connected TFT T5 and TFT T5 ' is connected with an EM1(n) scanning signal line. In the invention, the common end after the TFTT5 is connected with the TFT T5' is connected with an EM1(n) scanning signal line, so that an upper circuit and a lower circuit share an EM1 signal. And the circuit structure is simple in structure and convenient to realize and popularize in specific implementation.
Description
Technical Field
The invention belongs to the field of pixel circuits, and particularly relates to a pixel circuit beneficial to high-order display.
Background
Due to the self-luminous property of the OLED panel, the future OLED panel must pursue low power consumption, lightness and thinness, and diversification of shapes. The LTPO technology can make the GOA frame narrower, reduce the whole power consumption of the panel and promote future products to be more competitive. Since the threshold voltage of the TFT is shifted after long-term electrical stress, which causes variation in the luminance of the OLED, the OLED must use a pixel compensation circuit to compensate for the influence of the variation in the threshold voltage of the driving TFT on the luminance of the OLED. Currently, apple proposes a 6T1C LTPO pixel circuit in mass production, which is complicated and has a large number of input signals, so that the application in high-level display is limited.
Disclosure of Invention
The invention mainly aims to provide a pixel circuit beneficial to high-order display, which reduces the use of input signal sources and is beneficial to the layout wiring design of high-resolution pixels.
The invention mainly aims to provide a pixel circuit beneficial to high-order display, which is simple in structure and convenient to popularize.
In order to achieve the above object, the present invention has the following technical means.
A pixel circuit for facilitating high-order display includes an upper circuit and a lower circuit, the upper circuit includes a switch TFT T5, the lower circuit includes a switch TFT T5 ', the TFT T5 is connected with the grid electrode of the TFT T5 ', and the common terminal of the TFT T5 and the TFT T5 ' is connected with an EM1(n) scanning signal line. In the circuit, the common end after the TFT T5 is connected with the TFT T5' is connected with an EM1(n) scanning signal line, so that an EM1 signal is shared by an upper circuit and a lower circuit, the design reduces the use of input signal sources, and the design is favorable for the layout wiring design of high-resolution pixels. And the circuit structure is simple in structure and convenient to realize and popularize in specific implementation.
Further, the TFT T5 and the TFT T5' are both LTPS-TFTs.
Further, the upper circuit further comprises a TFT T1, a TFT T2, a TFT T3, a TFT T4, a TFT T6, a capacitor C1 and a diode D1; the grid electrode of the TFT T6 is connected with the grid electrode of the TFT T3, and the connected common end is connected with a Scan1(n) scanning signal line; the grid electrode of the TFT T4 is connected with an EM2(n) scanning signal line; the grid electrode of the TFT T2 is connected with a Scan2(n) scanning signal line; one end of the TFT T5, one end of the TFT T6, one end of the capacitor C1 and the anode of the diode D1 are connected, and a common end N1 is formed; the other end of the capacitor C1, the drain electrode of the TFT T1 and one end of the TFT T3 are connected, and a common end N2 is formed; the other end of the TFT T3, one end of the TFT T1, and one end of the TFT T4 are connected, and a common terminal N3 is formed; the other end of the TFT T1, one end of the TFT T2 and the other end of the TFT T5 are connected, and a common terminal N4 is formed; the other end of the TFT T2 is connected with a lower circuit.
The working process of the upper circuit is mainly divided into 4 stages.
1. An initialization stage: scan1(N) is raised to high potential, EM1(N) is lowered to low potential, EM2(N) is maintained high potential, Scan2(N) is maintained low potential, T5 is turned off, T3 is turned on, N2 and N3 are high potential, T1 is turned on, T2 is turned off, so N4 is high potential, T6 is turned on, the potential of OLED anode point N1 is initialized to low potential VINI, so the OLED does not emit light; vth extraction phase: scan2(N) is raised to a high potential, Data is written into a point N4, EM2(N) is lowered to a low potential, T1 forms a diode structure, a current flows through T1 due to the fact that the potential of N4 is low, the potentials of N4 are fixed to Data, the potentials of N2 and N3 are constantly pulled low, the potentials of N2 and N3 are equal, and theoretically, when the potential of N2 is lowered to Vth + Vdata of T1, Vgs-Vth of T1 is Vth + Vdata-Vdata-Vth is 0V, T1 is cut off; 3. data maintenance: scan2(N) is reduced to low potential, T2 is closed, EM2(N) and EM1(N) are increased to high potential, T4 and T5 are opened, Scan1(N) is reduced to low potential, T3 and T6 are closed, therefore, N3 is increased to high potential VDD, N2 maintains Data + Vth potential, N1 maintains Data potential, and T5 is closed because EM1(N) maintains low potential, and OLED is not turned on; OLED light emitting phase: EM1(n) goes high, T5 turns on, and the OLED turns on.
Further, the lower circuit further comprises a TFT T1 ', a TFT T2 ', a TFT T3 ', a TFT T4 ', a TFT T6 ', a capacitor C2 and a diode D2; the grid electrode of the TFT T6 'is connected with the grid electrode of the TFT T3', and the connected common end is connected with a Scan1(n +1) scanning signal line; the grid electrode of the TFT T4' is connected with an EM2(n +1) scanning signal line; the grid electrode of the TFT T2' is connected with a Scan2(n +1) scanning signal line; one end of the TFT T5 ', one end of the TFT T6', one end of the capacitor C2 and the anode of the diode D2 are connected, and a common end N1b is formed; the other end of the capacitor C2, the drain electrode of the TFT T1 'and one end of the TFT T3' are connected, and a common end N2b is formed; the other end of the TFT T3 ', the one end of the TFT T1 ' and the one end of the TFT T4 ' are connected and a common terminal N3b is formed; the other end of the TFT T1 ', one end of the TFT T2 ' and the other end of the TFT T5 ' are connected, and a common terminal N4b is formed; the other end of the TFT T2' is connected with the other end of the TFT T2. The common terminal in this circuit refers to a common and commonly accessed terminal.
The working process of the lower circuit is mainly divided into 4 stages.
OLED quenching: EM1(n) is reduced to low potential, T5' is closed, and OLED is extinguished; 2. an initialization stage: scan1(N +1) is raised to high potential, EM1(N) is low potential, EM2(N +1) is maintained to high potential, Scan2(N +1) is maintained to low potential, T5 ' is turned off, T3 ' is turned on, N2b and N3b are high potential, T1 ' is turned on, T2 ' is turned off, therefore, N4b is high potential, T6 ' is turned on, the potential of OLED anode point N1b is initialized to low potential VINI, and thus, the OLED does not emit light; vth extraction phase: scan2(N +1) is raised to a high potential, Data is written into a point N4b, EM2(N +1) is lowered to a low potential, T1 ' forms a diode structure, current flows through T1 ' because N4b is low in potential, N4b is fixed to Data, N2b and N3b are continuously pulled low in potential, N2b is equal to N3b in potential, and in theory, when N2b is lowered to Vth + Vdata of T1 ', Vgs-Vth of T1 ' is Vth + Vdata-Vdata-Vth is 0V, T1 ' is cut off; and (3) an OLED light-emitting stage: scan2(N +1) is lowered to low potential, T2 'is turned off, EM2(N +1) and EM1(N) are raised to high potential, T4' and T5 'are turned on, Scan1(N +1) is lowered to low potential, T3' and T6 'are turned off, therefore, N3b is raised to high potential VDD, current flows through T1', and OLED is turned on.
Further, the TFT T3 and the TFT T3 ' are IGZO-TFTs, and the TFT T1, the TFT T2, the TFT T4, the TFT T6, the TFT T1 ', the TFT T2 ', the TFT T4 ' and the TFT T6 ' are LTPS-TFTs. LTPS (low temperature poly-silicon) is also a technology adopted by most of mobile phone screens at present, has the greatest advantages of ultrahigh electron mobility, high resolution, high reaction speed, high brightness, high aperture ratio and the like, but has obvious defects, and large leakage current, so that low drive power consumption is large, and the low refresh rate is not suitable. The IGZO-indium gallium zinc oxide has a lower electron mobility than LTPS, has the advantages of good uniformity, transparency, simple manufacturing process, and the like, is lower in cost than LTPS, and is generally used in large-sized display devices. Moreover, the IGZO has less leakage, can ensure the stability at the time of low refresh rate, and has relatively lower power consumption. The combination of LTPS and IGZO adopted by the technical scheme can realize low refresh rate, cover a wider refresh rate range and further reduce power consumption.
Compared with the prior art, the invention has the beneficial effects that in the invention, the common end after the TFT T5 is connected with the TFT T5' is connected with the EM1(n) scanning signal line, so that the upper circuit and the lower circuit share the EM1 signal, the design reduces the use of input signal sources, and the design is favorable for the layout wiring design of high-resolution pixels. And the circuit structure is simple in structure and convenient to realize and popularize in specific implementation.
Drawings
Fig. 1 is a timing diagram of the prior art.
Fig. 2 is a schematic diagram of a prior art trace.
Fig. 3 is a circuit schematic of the present invention.
Fig. 4 is a timing diagram of the present invention.
Fig. 5 is a trace diagram of the present invention.
Fig. 6 is a timing diagram of the present invention.
Fig. 7 is a waveform diagram of an input signal of the present invention.
Fig. 8 is a waveform diagram of the upper circuit of the present invention.
Fig. 9 is a waveform diagram of the lower circuit of the present invention.
FIG. 10 is a diagram of a conventional display panel structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A pixel circuit for facilitating high-order display includes an upper circuit and a lower circuit, the upper circuit includes a switch TFT T5, the lower circuit includes a switch TFT T5 ', the TFT T5 is connected with the grid electrode of the TFT T5 ', and the common terminal of the TFT T5 and the TFT T5 ' is connected with an EM1(n) scanning signal line.
Further, the TFT T5 and the TFT T5' are both LTPS-TFTs.
Further, the upper circuit further comprises a TFT T1, a TFT T2, a TFT T3, a TFT T4, a TFT T6, a capacitor C1 and a diode D1; the grid electrode of the TFT T6 is connected with the grid electrode of the TFT T3, and the connected common end is connected with a Scan1(n) scanning signal line; the grid electrode of the TFT T4 is connected with an EM2(n) scanning signal line; the grid electrode of the TFT T2 is connected with a Scan2(n) scanning signal line; one end of the TFT T5, one end of the TFT T6, one end of the capacitor C1 and the anode of the diode D1 are connected, and a common end N1 is formed; the other end of the capacitor C1, the drain electrode of the TFT T1 and one end of the TFT T3 are connected, and a common end N2 is formed; the other end of the TFT T3, one end of the TFT T1, and one end of the TFT T4 are connected, and a common terminal N3 is formed; the other end of the TFT T1, one end of the TFT T2 and the other end of the TFT T5 are connected, and a common terminal N4 is formed; the other end of the TFT T2 is connected with a lower circuit.
The working process of the upper circuit is mainly divided into 4 stages.
1. An initialization stage: scan1(N) is raised to high potential, EM1(N) is lowered to low potential, EM2(N) is maintained high potential, Scan2(N) is maintained low potential, T5 is turned off, T3 is turned on, N2 and N3 are high potential, T1 is turned on, T2 is turned off, so N4 is high potential, T6 is turned on, the potential of OLED anode point N1 is initialized to low potential VINI, so the OLED does not emit light; vth extraction phase: scan2(N) is raised to a high potential, Data is written into a point N4, EM2(N) is lowered to a low potential, T1 forms a diode structure, a current flows through T1 due to the fact that the potential of N4 is low, the potentials of N4 are fixed to Data, the potentials of N2 and N3 are constantly pulled low, the potentials of N2 and N3 are equal, and theoretically, when the potential of N2 is lowered to Vth + Vdata of T1, Vgs-Vth of T1 is Vth + Vdata-Vdata-Vth is 0V, T1 is cut off; 3. data maintenance: scan2(N) is reduced to low potential, T2 is closed, EM2(N) and EM1(N) are increased to high potential, T4 and T5 are opened, Scan1(N) is reduced to low potential, T3 and T6 are closed, therefore, N3 is increased to high potential VDD, N2 maintains Data + Vth potential, N1 maintains Data potential, and T5 is closed because EM1(N) maintains low potential, and OLED is not turned on; OLED light emitting phase: EM1(n) goes high, T5 turns on, and the OLED turns on.
Further, the lower circuit further comprises a TFT T1 ', a TFT T2 ', a TFT T3 ', a TFT T4 ', a TFT T6 ', a capacitor C2 and a diode D2; the grid electrode of the TFT T6 'is connected with the grid electrode of the TFT T3', and the connected common end is connected with a Scan1(n +1) scanning signal line; the grid electrode of the TFT T4' is connected with an EM2(n +1) scanning signal line; the grid electrode of the TFT T2' is connected with a Scan2(n +1) scanning signal line; one end of the TFT T5 ', one end of the TFT T6', one end of the capacitor C2 and the anode of the diode D2 are connected, and a common end N1b is formed; the other end of the capacitor C2, the drain electrode of the TFT T1 'and one end of the TFT T3' are connected, and a common end N2b is formed; the other end of the TFT T3 ', the one end of the TFT T1 ' and the one end of the TFT T4 ' are connected and a common terminal N3b is formed; the other end of the TFT T1 ', one end of the TFT T2 ' and the other end of the TFT T5 ' are connected, and a common terminal N4b is formed; the other end of the TFT T2' is connected with the other end of the TFT T2.
The working process of the lower circuit is mainly divided into 4 stages.
OLED quenching: EM1(n) is reduced to low potential, T5' is closed, and OLED is extinguished; 2. an initialization stage: scan1(N +1) is raised to high potential, EM1(N) is low potential, EM2(N +1) is maintained to high potential, Scan2(N +1) is maintained to low potential, T5 ' is turned off, T3 ' is turned on, N2b and N3b are high potential, T1 ' is turned on, T2 ' is turned off, therefore, N4b is high potential, T6 ' is turned on, the potential of OLED anode point N1b is initialized to low potential VINI, and thus, the OLED does not emit light; vth extraction phase: scan2(N +1) is raised to a high potential, Data is written into a point N4b, EM2(N +1) is lowered to a low potential, T1 ' forms a diode structure, current flows through T1 ' because N4b is low in potential, N4b is fixed to Data, N2b and N3b are continuously pulled low in potential, N2b is equal to N3b in potential, and in theory, when N2b is lowered to Vth + Vdata of T1 ', Vgs-Vth of T1 ' is Vth + Vdata-Vdata-Vth is 0V, T1 ' is cut off; and (3) an OLED light-emitting stage: scan2(N +1) is lowered to low potential, T2 'is turned off, EM2(N +1) and EM1(N) are raised to high potential, T4' and T5 'are turned on, Scan1(N +1) is lowered to low potential, T3' and T6 'are turned off, therefore, N3b is raised to high potential VDD, current flows through T1', and OLED is turned on.
Further, the TFT T3 and the TFT T3 ' are IGZO-TFTs, and the TFT T1, the TFT T2, the TFT T4, the TFT T6, the TFT T1 ', the TFT T2 ', the TFT T4 ' and the TFT T6 ' are LTPS-TFTs. LTPS (low temperature poly-silicon) is also a technology adopted by most of mobile phone screens at present, has the greatest advantages of ultrahigh electron mobility, high resolution, high reaction speed, high brightness, high aperture ratio and the like, but has obvious defects, and large leakage current, so that low drive power consumption is large, and the low refresh rate is not suitable. The IGZO-indium gallium zinc oxide has a lower electron mobility than LTPS, has the advantages of good uniformity, transparency, simple manufacturing process, and the like, is lower in cost than LTPS, and is generally used in large-sized display devices. Moreover, the IGZO has less leakage, can ensure the stability at the time of low refresh rate, and has relatively lower power consumption. The combination of LTPS and IGZO adopted by the technical scheme can realize low refresh rate, cover a wider refresh rate range and further reduce power consumption.
Specifically, the TFT T5 and the TFT T5 'are both switching TFTs, and control the current generated by driving the TFT T1 and the TFT T1' to pass through the OLED device. The circuit adopts a diode mode to extract Vth of the TFT T1 and the TFT T1', and pulse widths of other signals EM2, Scan2 and Scan1 control the Vth extraction time and extraction process of the TFT T1, for example, Scan1 controls the drain and gate potentials of the TFT T1, the TFT controlled by EM2 influences the drain potential of the TFT T1, and the TFT controlled by Scan2 influences the source potential of the TFT T1. In the process of potential resetting and diode extraction Vth of the TFT T5 and the TFT T5 ' (Roman numeral 1 st and 2 nd stages), the controlled TFT T5 and the controlled TFT T5 ' are both closed, so that the common use of signals cannot influence the potentials of the sources of the TFT T1 and the TFT T1 '. Therefore, in order to ensure that the time and accuracy of Vth of the TFT T1 and the TFT T1 'coincide, it is eventually ensured that currents flowing through the TFT T1 and the TFT T1' coincide, and other signals cannot be commonly used. Therefore, in the present circuit, the design in which the common terminal of the TFT T5 and the TFT T5 'is connected to the EM1(n) scanning signal line is a design that reduces the use of the input signal source while ensuring the time and accuracy of Vth of the TFT T1 and the TFT T1' to be uniform and the current to be uniform.
In the present circuit: the source and drain electrodes of the TFT are dynamically changed continuously, the N-type TFT used in the circuit has the drain electrode with high voltage and the source electrode with low voltage.
| TFT | Ⅰ | Ⅱ | Ⅲ |
| T1 | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
| T2 | Left drain and right source | Left drain and right source | Left drain and right source |
| T3 | Left source and right drain | Left source and right drain | Left source and right drain |
| T4 | Upper drain electrode, lower source electrode | A drain electrode at the upper end of the substrate,lower source electrode | Upper drain electrode, lower source electrode |
| T5 | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
| T6 | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
| T1′ | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
| T2′ | Left drain and right source | Left drain and right source | Left drain and right source |
| T3′ | Left source and right drain | Left source and right drain | Left source and right drain |
| T4′ | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
| T5′ | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
| T6′ | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode | Upper drain electrode, lower source electrode |
The positions of the upper end, the lower end, the left end and the right end in the upper table specifically refer to the positions of the upper end, the lower end, the left end and the right end of each TFT in fig. 3. The above I, II and III refer to FIG. 4 in three stages.
EM1(n), EM2(n), EM2(n +1), Scan1(n), Scan1(n +1), Scan2(n), and Scan2(n +1) are scanning signals. A common structure of a display panel is shown in fig. 10, and the AA area is a display area. The goa (gate driver on array) provides scanning signals for the display area. EM1(n), EM2(n), EM2(n +1), Scan1(n), Scan1(n +1), Scan2(n), Scan2(n +1) are all provided by GOA. Data is provided by a Data chip (source) at the bottom.
Compared with the prior art, the invention has the beneficial effects that in the invention, the common end after the TFT T5 is connected with the TFT T5' is connected with the EM1(n) scanning signal line, so that the upper circuit and the lower circuit share the EM1 signal, the design reduces the use of input signal sources, and the design is favorable for the layout wiring design of high-resolution pixels. And the circuit structure is simple in structure and convenient to realize and popularize in specific implementation.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to cover the technical solutions and the inventive concepts of the present invention within the technical scope of the present invention.
Claims (5)
1. A pixel circuit for facilitating high-order display includes an upper circuit and a lower circuit, the upper circuit includes a switch TFT T5, the lower circuit includes a switch TFT T5 ', the TFT T5 is connected with the grid electrode of the TFT T5 ', and the common terminal of the TFT T5 and the TFT T5 ' is connected with an EM1(n) scanning signal line.
2. The pixel circuit for facilitating high-order display of claim 1, wherein the TFT T5 and the TFT T5' are LTPS-TFTs.
3. The pixel circuit for facilitating high-order display of claim 1, wherein the upper circuit further comprises a TFT T1, a TFT T2, a TFT T3, a TFT T4, a TFT T6, a capacitor C1, a diode D1; the grid electrode of the TFT T6 is connected with the grid electrode of the TFT T3, and the connected common end is connected with a Scan1(n) scanning signal line; the grid electrode of the TFT T4 is connected with an EM2(n) scanning signal line; the grid electrode of the TFT T2 is connected with a Scan2(n) scanning signal line; one end of the TFT T5, one end of the TFT T6, one end of the capacitor C1 and the anode of the diode D1 are connected, and a common end N1 is formed; the other end of the capacitor C1, the drain electrode of the TFT T1 and one end of the TFT T3 are connected, and a common end N2 is formed; the other end of the TFT T3, one end of the TFT T1, and one end of the TFT T4 are connected, and a common terminal N3 is formed; the other end of the TFT T1, one end of the TFT T2 and the other end of the TFT T5 are connected, and a common terminal N4 is formed; the other end of the TFT T2 is connected with a lower circuit.
4. A pixel circuit for facilitating high-order display according to claim 3, wherein the lower circuit further comprises a TFT T1 ', a TFT T2 ', a TFT T3 ', a TFT T4 ', a TFT T6 ', a capacitor C2 and a diode D2; the grid electrode of the TFT T6 'is connected with the grid electrode of the TFT T3', and the connected common end is connected with a Scan1(n +1) scanning signal line; the grid electrode of the TFT T4' is connected with an EM2(n +1) scanning signal line; the grid electrode of the TFT T2' is connected with a Scan2(n +1) scanning signal line; one end of the TFT T5 ', one end of the TFT T6', one end of the capacitor C2 and the anode of the diode D2 are connected, and a common end N1b is formed; the other end of the capacitor C2, the drain electrode of the TFT T1 'and one end of the TFT T3' are connected, and a common end N2b is formed; the other end of the TFT T3 ', the one end of the TFT T1 ' and the one end of the TFT T4 ' are connected and a common terminal N3b is formed; the other end of the TFT T1 ', one end of the TFT T2 ' and the other end of the TFT T5 ' are connected, and a common terminal N4b is formed; the other end of the TFT T2' is connected with the other end of the TFT T2.
5. A pixel circuit for facilitating high-order display according to claim 4, wherein the TFT T3 and the TFT T3 ' are IGZO-TFTs, and the TFT T1, the TFT T2, the TFT T4, the TFT T6, the TFT T1 ', the TFT T2 ', the TFT T4 ', and the TFT T6 ' are LTPS-TFTs.
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| CN202110644652.9A CN113506540A (en) | 2021-06-09 | 2021-06-09 | Pixel circuit beneficial to high-order display |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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Application publication date: 20211015 |