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CN113496976A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN113496976A
CN113496976A CN202010895058.2A CN202010895058A CN113496976A CN 113496976 A CN113496976 A CN 113496976A CN 202010895058 A CN202010895058 A CN 202010895058A CN 113496976 A CN113496976 A CN 113496976A
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CN
China
Prior art keywords
terminal
semiconductor device
semiconductor element
electrodes
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010895058.2A
Other languages
Chinese (zh)
Other versions
CN113496976B (en
Inventor
岩渊春彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to CN202210670342.9A priority Critical patent/CN115050719A/en
Publication of CN113496976A publication Critical patent/CN113496976A/en
Application granted granted Critical
Publication of CN113496976B publication Critical patent/CN113496976B/en
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Anticipated expiration legal-status Critical

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/4952—Additional leads the additional leads being a bump or a wire
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The semiconductor device of the present embodiment includes a semiconductor element, a first terminal, a plurality of second terminals, and an internal package. The semiconductor element is rectangular. The first terminal is bonded to the back surface of the semiconductor element at the upper surface. The plurality of second terminals are arranged around the first terminals. The inner package seals the conductive line, the semiconductor element, the first terminal, and the plurality of second terminals, which are arranged between the surface of the semiconductor element and the upper surfaces of the plurality of second terminals, and has a rectangular bottom surface including first to fourth sides and first to fourth sides respectively connected to the first to fourth sides, the first side surface is opposite to the third side surface, and the second side surface is opposite to the fourth side surface. The plurality of second terminals are disposed so as to be exposed from the bottom surface at the 4-corner of the inner package, the sides of the semiconductor element face the first to fourth sides, the first terminals are separated from the first side surface and the third side surface, the lower surfaces of the first terminals are exposed from the bottom surface, and the first terminals are partially exposed from the second side surface and the fourth side surface.

Description

Semiconductor device with a plurality of semiconductor chips
RELATED APPLICATIONS
The present application enjoys priority based on Japanese patent application No. 2020-. This application contains all of the contents of the base application by reference to the base application.
Technical Field
Embodiments relate to a semiconductor device.
Background
A semiconductor device is generally known as a surface-mount package (surface-mount package) in which a lead is not extended from a resin package, and an electrode is exposed on a lower surface of the resin package. A semiconductor device using a leadless package has a structure in which a rectangular semiconductor element is sealed together with a lead frame by a resin package.
The semiconductor device includes, for example, an island formed by appropriately cutting a metal lead frame patterned by etching or the like, and a plurality of leads arranged around the island. Such a semiconductor device is further required to be miniaturized. Therefore, the leads are generally formed at four corners of the resin package, and the semiconductor element is disposed so as to be inclined at 45 degrees with respect to the resin package.
However, in order to arrange the semiconductor element at an angle of 45 degrees with respect to the resin package, a rotation process of the semiconductor element is required, and the production efficiency may be reduced.
Disclosure of Invention
Embodiments provide a semiconductor device which can be miniaturized and has improved production performance.
A semiconductor device according to an embodiment includes a semiconductor element, a first terminal, a plurality of second terminals, and an internal package. The semiconductor element is rectangular. The first terminal is bonded to the back surface of the semiconductor element at the upper surface. The plurality of second terminals are arranged around the first terminals. The inner package seals the conductive line, the semiconductor element, the first terminal, and the plurality of second terminals, which are arranged between the surface of the semiconductor element and the upper surfaces of the plurality of second terminals, and has a rectangular bottom surface including a first side, a second side, a third side, and a fourth side, and a first side surface, a second side surface, a third side surface, and a fourth side surface which are respectively connected to the first side, the second side, the third side, and the fourth side, the first side surface and the third side surface being opposed to each other, and the second side surface and the fourth side surface being opposed to each other. The plurality of second terminals are disposed at the 4-corner of the inner package so as to be exposed from the bottom surface, the sides of the semiconductor element face the first side, the second side, the third side, and the fourth side, the first terminals are separated from the first side surface and the third side surface, the lower surface is exposed from the bottom surface, and a part of the lower surface is exposed from the second side surface and the fourth side surface.
Drawings
Fig. 1(a) is a bottom view illustrating a configuration of a semiconductor device 1 according to an embodiment.
Fig. 1(B) is a plan view of a semiconductor device according to an embodiment.
FIG. 1(C) is a sectional view taken along line A-A of FIG. 1 (B).
FIG. 1(D) is a sectional view taken along line B-B of FIG. 1 (B).
Fig. 2 is a diagram showing an example of arrangement of a plurality of semiconductor devices 1 in a resin sealing body.
Fig. 3(a) is a bottom view illustrating the structure of the semiconductor device 1 a.
Fig. 3(B) is a plan view of the semiconductor device 1 a.
FIG. 3(C) is a sectional view taken along line A-A of FIG. 3 (B).
Fig. 3(D) is a sectional view B-B of fig. 3 (B).
Fig. 4(a) is a bottom view illustrating the structure of the semiconductor device 1 b.
Fig. 4(B) is a plan view of the semiconductor device 1B.
FIG. 4(C) is a sectional view taken along line A-A of FIG. 4 (B).
Fig. 4(D) is a sectional view B-B of fig. 4 (B).
Detailed Description
Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. The embodiments described below are merely examples of the embodiments of the present invention, and the present invention is not limited to these embodiments. In the drawings referred to in the present embodiment, the same reference numerals or similar reference numerals are given to the same portions or portions having the same functions, and redundant description thereof may be omitted. For convenience of explanation, the dimensional ratios in the drawings may be different from the actual ratios, and some of the components may be omitted from the drawings.
(one embodiment)
The structure of the semiconductor device 1 according to one embodiment will be described with reference to fig. 1(a) to (D). Fig. 1(a) to (D) are diagrams illustrating the structure of the semiconductor device 1. Fig. 1(a) is a bottom view of the semiconductor device 1. Fig. 1(B) is a plan view of the semiconductor device 1. FIG. 1(C) is a sectional view taken along line A-A of FIG. 1 (B). FIG. 1(D) is a sectional view taken along line B-B of FIG. 1 (B). In the present embodiment, the direction from the upper surface to the lower surface of the semiconductor device 1 is represented by the Z direction, and the directions orthogonal to the Z direction are represented by the X direction and the Y direction.
As shown in fig. 1(a) to (D), the semiconductor device 1 includes four leads 2, an island 3, a semiconductor element 4, a bonding wire 5, and a resin package 6. The semiconductor device 1 is a rectangular parallelepiped. The size of the semiconductor device 1 is not particularly limited. The broken line 50 in fig. 1(a) indicates the lead 50 of the comparative example described later using fig. 3(a) to (D), and the broken line 60 indicates an example of forming an island 60 of the comparative example described later. Fig. 1(B) is a plan view of the resin package 6. Therefore, the upper surface of the semiconductor device 1 is actually covered with the resin package 6. A broken line 200 in fig. 1(B) indicates the lead 2 shown in fig. 1(a), and a broken line 300 indicates the lower surface pattern of the island 3.
Fig. 2 is a diagram showing an example of arrangement of a plurality of semiconductor devices 1 in a resin package 400.
As shown in fig. 2, a plurality of semiconductor devices 1 are arranged in the resin package 400. The lead frame 500 of the resin sealing body 400 is cut out together with the resin, thereby producing the semiconductor device 1.
The material of the lead 2 and the island 3 is not particularly limited, and is Cu, for example. For example, the lead 2 and the island 3 are formed of the same metal plate, and have the same maximum thickness. In the present embodiment, the island 3 corresponds to the first terminal, the lead 2 corresponds to the second terminal, the bonding wire 5 corresponds to the conductive wire, and the resin package 6 corresponds to the inner package.
The four leads 2 are separated from the island 3 and the semiconductor element 4. That is, in the present embodiment, four leads 2 are disposed separately from each other with an island 3 and a semiconductor element 4 interposed therebetween. In this way, the four leads 2 are arranged at the 4-corner of the resin package 6. In this case, as shown by an arrow W2 in fig. 1(a), the side surface of the semiconductor device 1 may have an edge portion in which the lead 2 is covered with the resin package 6.
Each lead 2 has a non-etched portion exposed from the bottom surface of the resin package 6, and a terminal half-etched portion 2a that is covered with the resin package 6 on the lower surface side and has a smaller thickness than the non-etched portion. The terminal half-etched portion 2a extends a predetermined length (width) from the non-etched portion toward the island 3 and the adjacent lead 2. The terminal half-etched portion 2a can be formed by, for example, chemical etching or flattening. The material of the resin package 6 enters and covers the terminal half-etched portion 2 a.
In this specification, the lower surfaces and shapes of the lead 2 and the island 3 refer to the non-etched portion exposed from the bottom surface of the resin package 6 and the shape thereof. The shape of the lead 2 and the island 3 or the shape of the upper surface refers to a shape in which the non-etched portion and the half-etched portion are integrated in a plan view. The non-etched portions and half-etched portions of the leads 2 and the islands 3 are smoothly continuous on the upper surface. The upper surfaces of the lead 2 and the island 3 have a shape in which the width of the lead 2 and the lower surface of the island 3 is increased by half etching.
The lower surface of each lead 2 is exposed on the bottom surface of the resin package 6 except for the terminal half-etched portion 2a, and functions as an external terminal connected to a wiring board (not shown).
The lower surface of the lead 2 has a pentagonal shape, and has sides 20 and 22 parallel to one pair of opposing sides of the semiconductor element 4, and sides 21 and 23 parallel to the other pair of opposing sides of the semiconductor element 4. Each lead 2 further has a side 24 which is not parallel to any one side of the semiconductor element 4, for example, inclined by 45 degrees. Side 23 is shorter than side 20.
The upper surface of the lead 2 is pentagonal in shape, and has sides 120 and 122 parallel to one set of opposing sides of the semiconductor element 4, and sides 121 and 123 parallel to the other set of opposing sides of the semiconductor element 4. Each lead 2 further has a side 124 which is not parallel to any one side of the semiconductor element 4, for example, inclined by 45 degrees. Edge 123 is shorter than edge 120.
The lower surface of the island 3 is substantially diamond shaped. The lower surface of the island 3 of the present embodiment has a shape obtained by rounding the corners of a diamond, for example, by cutting. The sides of the rhomboid shape in the lower surface of the island 3 are not parallel to the sides of the resin package 6. In other words, the lower surface of the island 3 has a shape having 2 sets of opposite sides parallel to each other. The opposite sides of the group 2 of islands 3 are not parallel to any one side of the resin package 6. The length of the lower surface of the island 3 in the X direction is longer than the length in the Y direction. The upper surface of the island 3 is substantially rhombic except for the portions 30a and 30b, and the substantially rhombic shape can be said to be the same as the lower surface of the island 3.
The lower surface of the island 3 is exposed at the bottom surface of the resin package 6. An island half-etched portion 3a is formed on a side surface of the island 3 facing the lead 2. The material of the resin package 6 enters the island half-etched portion 3 a. In other words, each lead 2 has a non-etched portion exposed from the bottom surface of the resin package 6, and an island half-etched portion 2a that is covered with the resin package on the lower surface side and has a smaller thickness than the non-etched portion. The island half-etched portion 2a extends from the non-etched portion in the XY plane by a predetermined length (width). This can improve the bonding strength between the island 3 and the resin package 6. The island half-etched portions 3a can be formed by, for example, chemical etching or flattening.
The island half-etched portion 3a of the island 3 has arm portions 30a and 30b extending and protruding in the X direction. As shown in fig. 2, the arm portions 30a, 30b are connected to the lead frame 500, thereby preventing the island 3 from falling off from the lead frame 500. In the present embodiment, as shown in fig. 2, the regions 30a and 30b of the island 3 connected to the adjacent lead frame 500 before cutting are referred to as a boom portion or a hanger pin. The plurality of leads 2 are disposed at respective end portions of 2 sides of the resin package 6 extending in the X direction when viewed in plan in the Z direction. The two spaces a2 formed between the ends adjacent in the Y direction include the boom portions 30a, 30 b.
On the other hand, the island 3 is separated from 2 sides extending in the X direction when viewed in plan in the Z direction. In other words, the island 3 is separated from the side surface of the resin package 6 parallel to the Z direction and the X direction. Therefore, the region B2 in which 2 sides of the island 3 and the resin package 6 extending in the X direction do not contact each other can be provided when viewed in plan in the Z direction.
In fig. 1(B), in other words, when viewed in plan in the Z direction, the points at which the arm portions 30a and 30B are in contact with the opposing 2 sides of the resin package 6 are at least 2 points apart. As shown in fig. 1(a), the midpoint of the island 3 is located between 2 points of the boom portions 30a and 30b in a plan view.
The semiconductor element 4 (semiconductor chip) has a rectangular shape. The semiconductor element 4 has a back surface bonded to the island 3 via an adhesive in a state where the front surface (device formation surface) on which the functional element is formed is directed upward. The bonding material is, for example, a non-conductive bonding material, but a conductive bonding material can also be used.
The angle formed by the side of the semiconductor element 4 and the side of the resin package 6 is 20 degrees or less. It is more preferable that the sides of the semiconductor element and the sides of the resin package 6 are parallel. As shown in fig. 1(B), when viewed in plan in the Z direction, the corners of the semiconductor element 4 are not included between two leads 2 adjacent in the X direction. The corners of the semiconductor element 4 are included between two leads 2 adjacent in the Y direction when viewed in plan in the Z direction.
On the surface of the semiconductor element 4, pads 4a corresponding to the respective leads 2 are formed. One end of the bonding wire 5 is bonded to each pad 4 a. The other end of the bonding wire 5 is bonded to the upper surface of each lead 2. Thereby, the semiconductor element 4 is electrically connected to the lead 2 via the bonding wire 5.
The structure of comparative example 1a of semiconductor device 1 according to one embodiment will be described with reference to fig. 3(a) to (D). Fig. 3(a) to (D) are diagrams illustrating the structure of the semiconductor device 1 a. Fig. 3(a) is a bottom view of the semiconductor device 1 a. Fig. 3(B) is a plan view of the semiconductor device 1 a. Fig. 3(C) is a sectional view taken along a-a of fig. 3 (B). Fig. 3(D) is a sectional view taken along B-B of fig. 3 (B).
As shown in fig. 3(a) to (D), the semiconductor device 1a includes four leads 50, an island 60, a semiconductor element 4, a bonding wire 5, and a resin package 6. The semiconductor device 1a is a rectangular parallelepiped. The semiconductor device 1a includes a semiconductor element 4 and a resin package 6 included in the semiconductor device 1. Fig. 3(B) is a plan view of the resin package 6. Therefore, the upper surface of the semiconductor device 1 is actually covered with the resin package 6. The broken line 200a in fig. 3(B) represents the lead 50 shown in fig. 3 (a). The semiconductor element 4 has, for example, the same shape as the lower surface pattern of the island 60, and is provided directly above the lower surface pattern of the island 60.
As shown in fig. 3(a), 1 side of each lead 50 and 4 sides of the island 60 are arranged on the lower surface so as to be inclined at a predetermined angle, for example, at 45 degrees, with respect to the side of the resin package 6. That is, on the lower surface, 1 side of each lead 50 is arranged in parallel with any one side of the island 60 with a space.
In the semiconductor device 1a of the comparative example, the side of the semiconductor element 4 was arranged at 45 degrees with respect to the side of the resin package 6. Thus, the semiconductor device 1a is arranged such that the upper surface of the lead 50 provided at the 4-corner of the package 6 is separated from the lower surface of the semiconductor element 4 while taking the areas of the island 60 and the lead 50 large.
In manufacturing the semiconductor device 1a of the comparative example, it is necessary to perform a rotation operation in which the side of the semiconductor element 4 is rotated by 45 degrees with respect to the side of the resin package 6. In general, the alignment of the semiconductor element 4 is less accurate in the case of the rotation operation. In the comparative example, one corner of the semiconductor element 4 was cut at 45 degrees, and the edge formed by the cutting was aligned in the X direction, thereby improving the accuracy of alignment during the rotation operation. Further, by obtaining the area of the island 60 to be large, the alignment margin of the semiconductor element 4 is obtained to be large. The apex of the rectangular semiconductor element 4 is close to the side of the resin package 6.
Further, the lead 50 has a triangular shape. The lower surface of the island 60 of the present embodiment has a shape obtained by rounding the corners of a triangle, for example, by cutting. The arm portions of the islands 60 extend and protrude toward the sides of the resin package 6. Since the island 3 has a large area, the possibility of the island 60 being close to each lead 50 and short-circuited is increased in both the X direction and the Y direction.
The arm portions of the comparative example extend in the X direction and the Y direction, and are prevented from shifting and twisting when the island 60 is connected to the lead frame.
Since the semiconductor device 1 of example 1 is not provided with the arm portion extending in the Y direction, the region B2 can be acquired largely. This makes it possible to widely obtain the gap between the side 121 of the lead 2 and the island 3 in the X direction. Therefore, even when the size is further reduced, it is possible to suppress short-circuiting between the lead 2 and the island 3, which may occur due to metal dragging or the like when the lead frame is cut along the line extending in the X direction.
The island 3 of the semiconductor device 1 has a substantially rhombic shape having a length in the Y direction smaller than that in the X direction. Therefore, the distance between the island 3 and the side 24 of each lead 2 increases from the end of the side surface of the resin package 6 toward the midpoint in the X direction.
The length of the lead 2 in the Y direction is shorter than the length in the X direction. Therefore, even in the vicinity of the end in the X direction of the side surface of the resin package 6, the distance between the island 3 and the side 24 of each lead 2 can be obtained largely. Further, the distance between side 22 of each lead 2 and each of arms 30a and 30b and the distance between side 22 of each lead 2 and the rear surface of semiconductor element 4 can be obtained widely.
Therefore, the possibility of short-circuiting the lead 2 and the island 3 and the like is further reduced. That is, the gap is further increased. This enables further miniaturization of the semiconductor device 1.
The arm portions 30a and 30b are exposed from the resin package 6 at least at 2 points separated in the Y direction and connected to the lead frame. Since the boom portions 30a and 30b are divided into 2, compared with 1 thick boom portion, the metal cutting area during dicing can be reduced, stress concentration can be alleviated, and the quality of packaging can be improved. Also, in the case of using the cutting blade, clogging of the cutting blade can be prevented.
In the semiconductor device 1, the angle formed by the side of the semiconductor element 4 and the side of the resin package 6 is 20 degrees or less or parallel. Therefore, the operation of making the semiconductor element 4 meet 45 degrees with respect to the side of the resin package 6 as in the comparative example is not necessary, and the productivity of the semiconductor device 1 is further improved. In other words, by further shortening the side 23 of the lead 2, the semiconductor device 1 can be arranged without making the side of the semiconductor element 4 at 45 degrees with respect to the side of the resin package 6.
Further, in the semiconductor element 1, since the distance between the semiconductor element 4 and the side surface of the resin package 6 can be obtained largely, the stress applied to the semiconductor element 4 when the resin package 6 is cut can be reduced.
As described above, according to the present embodiment, the plurality of leads 2 are arranged at the 4-angle of the resin package 6, and the angle formed by the side of the semiconductor element 4 and the side of the resin package 6 is 20 degrees or less. This makes the distance between the apex of the semiconductor element 4 and the side of the resin package 6 longer, and the possibility of short-circuiting between the island 3 and each lead 2 is further suppressed, so that the semiconductor device can be further miniaturized, and the operation of making the semiconductor element 4 meet 45 degrees with respect to the side of the resin package 6 is not required, thereby further improving the productivity of the semiconductor device 1.
The island half-etched portion 3a of the island 3 has arm portions 30a and 30b extending in the X direction and exposed from the side surface of the resin package 6 when viewed in plan in the Z direction, and is formed separately from the side surface of the resin package 6 in the Y direction. This prevents the island 3 from falling off the lead frame, and provides the region B2 where the island 3 does not contact the side surface of the resin package 6. In this way, the semiconductor device 1 can be further miniaturized, and the productivity of the semiconductor device 1 can be further improved.
(modification of the first embodiment)
The semiconductor device 1b according to the modification of the embodiment is different from the semiconductor device 1 according to the modification of the embodiment in that the semiconductor device 1b is disposed so that the arm portions 32 and 34 of the island 3 are offset in the opposite left and right directions from the midpoint of the opposing sides of the resin package 6.
Fig. 4(a) to (D) are diagrams illustrating the configuration of a semiconductor device 1b according to a modification of the embodiment. Fig. 4(a) is a bottom view of the semiconductor device 1 b. Fig. 4(B) is a plan view of the semiconductor device 1B. Fig. 4(C) is a sectional view taken along a-a of fig. 4 (B). Fig. 4(D) is a sectional view taken along B-B of fig. 4 (B). The arm portions 32 and 34 of the island 3 are arranged offset in the opposite left-right direction from the midpoint of the opposing sides of the resin package 6. Torsion can be suppressed by the boom portions 32, 34.
Although the semiconductor device 1 has been described in the present specification as having the semiconductor element 4 mounted on the lead frame, it may be of a so-called lead-free type having the semiconductor element 4 mounted on a substrate or the like.
While several embodiments of the present invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope and gist of the invention, and are included in the scope and equivalents of the invention described in the claims.

Claims (16)

1. A semiconductor device includes:
a rectangular semiconductor element;
a first terminal bonded to a back surface of the semiconductor element on an upper surface;
a plurality of second terminals disposed around the first terminals; and
an inner package sealing the conductive line, the semiconductor element, the first terminal, and the second terminals, the conductive line being arranged between a surface of the semiconductor element and upper surfaces of the second terminals, the inner package having a rectangular bottom surface including a first edge, a second edge, a third edge, and a fourth edge, and having a first side surface, a second side surface, a third side surface, and a fourth side surface connected to the first edge, the second edge, the third edge, and the fourth edge, respectively, the first side surface facing the third side surface, the second side surface facing the fourth side surface,
the plurality of second terminals are disposed so as to be exposed from the bottom surface at 4 corners of the inner pack portion,
each side of the semiconductor element is opposed to the first side, the second side, the third side, and the fourth side,
the first terminal is separated from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and a part of the first terminal is exposed from the second side surface and the fourth side surface.
2. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
each side of the semiconductor element is parallel to the first side, the second side, the third side, and the fourth side.
3. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the first terminal has an island portion to be bonded to the semiconductor element, and a suspending arm portion extending from the island portion and protruding from the second side surface and the fourth side surface.
4. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the first terminals are exposed at least two locations of the second side surface that are separated from each other, and at least two locations of the fourth side surface that are separated from each other.
5. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
in a plan view of the bottom surface, a midpoint of each side of the bottom surface is not included in a portion of the first terminal exposed on the second side surface and the fourth side surface.
6. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the lower surface of the first terminal has a shape having at least 2 sets of opposite sides parallel to each other,
2 sets of said opposing sides are not parallel to any of said first side, said second side, said third side, and said fourth side,
a length of a lower surface of the first terminal in a direction parallel to the first side is longer than a length of a lower surface of the first terminal in a direction parallel to the second side.
7. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the length of the second terminal in a direction parallel to the first side is longer than the length of the second terminal in a direction parallel to the second side.
8. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the first terminal has a first portion exposed from the bottom surface and a second portion provided around the first portion, covered with the inner package, and having a thickness smaller than that of the first portion.
9. The semiconductor device as set forth in claim 2,
the first terminal has an island portion to be bonded to the semiconductor element, and a suspending arm portion extending from the island portion and protruding from the second side surface and the fourth side surface.
10. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the second terminal has a third portion exposed from the bottom surface and a fourth portion provided around the third portion, covered with the inner package, and having a thickness smaller than that of the third portion.
11. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the upper surface of the second terminal has a pentagonal shape, and has 2 sides parallel to one set of opposing sides of the semiconductor element, 2 sides parallel to the other set of opposing sides of the semiconductor element, and 1 side parallel to the upper surface of the first terminal.
12. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the lower surface of the second terminal has a pentagonal shape, has 2 sides parallel to one set of opposing sides of the semiconductor element, and 2 sides parallel to the other set of opposing sides of the semiconductor element, and has a side that is not parallel to any one side of the semiconductor element and is inclined at 45 degrees with respect to 1 side of the semiconductor element.
13. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the inner package portion has an edge portion covering the second terminal on a side surface of the inner package portion.
14. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the surface of the second terminal exposed from the bottom surface is connected to a wiring board.
15. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the first terminal and the second terminal are formed of the same metal plate.
16. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
the first terminal and the second terminal are made of copper.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189222A1 (en) * 2002-04-01 2003-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device
CN1571151A (en) * 2003-07-15 2005-01-26 佛里斯凯尔半导体公司 Double gauge lead frame
CN1574331A (en) * 2003-06-05 2005-02-02 株式会社瑞萨科技 Semiconductor device
JP2008153710A (en) * 2008-03-17 2008-07-03 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
CN102428558A (en) * 2009-05-15 2012-04-25 罗姆股份有限公司 Semiconductor device with a plurality of semiconductor chips
JP2018125530A (en) * 2018-01-25 2018-08-09 株式会社加藤電器製作所 Electronic device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968827A (en) 1982-10-12 1984-04-18 Sony Corp Bias magnetic head for magnetic transfer
JP4840893B2 (en) * 2000-05-12 2011-12-21 大日本印刷株式会社 Resin-encapsulated semiconductor device frame
US8525305B1 (en) * 2010-06-29 2013-09-03 Eoplex Limited Lead carrier with print-formed package components
JP5968827B2 (en) 2013-04-25 2016-08-10 アオイ電子株式会社 Semiconductor package and manufacturing method thereof
US10128434B2 (en) 2016-12-09 2018-11-13 Rohm Co., Ltd. Hall element module
JP6928463B2 (en) 2016-12-09 2021-09-01 ローム株式会社 Hall element module
JP6283131B1 (en) 2017-01-31 2018-02-21 株式会社加藤電器製作所 Electronic device and method for manufacturing electronic device
JP7265502B2 (en) * 2020-03-19 2023-04-26 株式会社東芝 semiconductor equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189222A1 (en) * 2002-04-01 2003-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device
CN1574331A (en) * 2003-06-05 2005-02-02 株式会社瑞萨科技 Semiconductor device
CN1571151A (en) * 2003-07-15 2005-01-26 佛里斯凯尔半导体公司 Double gauge lead frame
JP2008153710A (en) * 2008-03-17 2008-07-03 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
CN102428558A (en) * 2009-05-15 2012-04-25 罗姆股份有限公司 Semiconductor device with a plurality of semiconductor chips
JP2018125530A (en) * 2018-01-25 2018-08-09 株式会社加藤電器製作所 Electronic device

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