CN113495762A

CN113495762A - Starting method of system on chip

Info

Publication number: CN113495762A
Application number: CN202010189864.8A
Authority: CN
Inventors: 林世陵
Original assignee: Jmicron Tech Corp
Current assignee: Jmicron Tech Corp
Priority date: 2020-03-18
Filing date: 2020-03-18
Publication date: 2021-10-12

Abstract

The invention provides a starting method capable of dynamically modifying a starting program of a system-on-chip under the condition of not modifying a starting program in a read-only memory, which changes the starting position of reading a springboard program by reading an external input signal, and then reads a real target program by the springboard program.

Description

Starting method of system on chip

Technical Field

The present invention relates to a System-on-Chip (soc) booting method, and more particularly, to a booting method capable of dynamically modifying soc booting program without modifying the boot program in the rom.

Background

In the embedded system, the boot program is a section of program code executed before the operating system runs, and is intended to execute hardware initialization operation before the operating system runs, and finally, the operating system is loaded into a memory for execution. In the system on chip, the boot program is stored in the ROM. Before the operation system runs, the starting program is executed, and the target program is read and executed to complete the starting up of the external storage device. So that the user can update the target program at any time.

However, as electronic products become more complex, a plurality of systems on chip are often integrated into one electronic product, and if each system on chip has its own corresponding external storage device, the cost and routing difficulty of the whole system will be increased. On the contrary, if the plurality of soc share the same external storage device, the boot program in the plurality of soc roms is modified by modifying the masks of the plurality of soc and re-downloading the masks.

Therefore, there is a need for improvement in the prior art.

Disclosure of Invention

Therefore, the present invention is directed to a boot method capable of dynamically modifying a boot program of a system on chip without modifying a boot program in a rom, so as to overcome the drawbacks of the prior art.

The embodiment of the invention discloses a starting method, which is suitable for a starting program of a system on a chip, wherein the system on the chip comprises an input port for providing an external input signal, a processing unit for executing a program and a read-only memory for storing an initial starting program; reading the springboard program and executing the springboard program by the processing unit; and executing the target program by the processing unit through the springboard program; wherein, the springboard program and the target program are stored in an external storage device; the springboard program is used for reading the target program, and the target program is used for executing the starting program.

Drawings

FIG. 1A is a diagram of a system-on-chip and a system thereof according to the prior art.

FIG. 1B is a diagram illustrating a prior art system on a chip integrated with a system.

FIGS. 2A and 2B are schematic diagrams illustrating a memory allocation method of an external storage device according to the prior art.

FIGS. 3A and 3B are schematic diagrams of an on-chip system and a system thereof according to an embodiment of the invention.

FIG. 4 is a diagram illustrating an external storage device memory arrangement according to an embodiment of the present invention.

FIGS. 5A and 5B are schematic diagrams of an external storage device memory arrangement according to an embodiment of the invention.

FIG. 6 is a flowchart illustrating a booting method of a system-on-a-chip according to an embodiment of the invention.

FIG. 7 is a diagram of a system-on-a-chip according to an embodiment of the invention.

Description of the reference numerals

10 prior art system on chip

100 prior art processing unit

102 prior art read-only memory

104 prior art random access memory

12 prior art external storage device

Prior art system on chip

140 prior art processing unit

142 prior art read only memory

144 prior art random access memory

Prior art external storage device

30 system on chip

300 processing unit

302 read-only memory

304 random access memory

306 input port

32 external storage device

34 system on chip

340 processing unit

342 read-only memory

60, the process is

600 to 612 steps

Detailed Description

Certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. The terms "including" and "comprising" as used herein in the specification and in the claims are open-ended terms that should be interpreted as "including, but not limited to. Furthermore, the term "coupled" as used herein includes any direct and indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1A is a schematic diagram of a System on Chip (SoC) 10 and a System thereof according to the prior art. As shown in fig. 1A, the system-on-chip 10 includes a processing unit 100, a Read-Only Memory (ROM) 102 and a Random Access Memory (RAM) 104, and the system-on-chip 10 is coupled to an external storage device 12 to form a system. To initialize the system-on-chip 10, in the boot process, the processing unit 100 first reads and executes a boot loader (BootLoader) stored in the rom 102, then loads a target program from the external storage device 12 to the ram 104 through the boot loader, and finally the processing unit 100 executes the target program to complete the boot process.

In practical applications, the system is not implemented as a system-on-chip, as shown in fig. 1B, and fig. 1B is a schematic diagram illustrating a prior art system-on-

chip

10 and 14 integrated into a system. In the prior art, two systems-on-

chips

10 and 14 are coupled to

external storage devices

12 and 16, respectively, and are integrated into a system. In short, if a system includes a plurality of soc, the system needs a plurality of external storage devices to store target programs of the soc.

For example, FIGS. 2A and 2B are schematic diagrams of an external storage device memory arrangement of the prior art. As shown in FIG. 2A, if the boot program stored in the two

SoC ROMs

102 and 142 reads data from the

external storage devices

12 and 16 at the start locations 0000_0000 and 8000_0000, the circuit of FIG. 1B is simplified such that the two

SoC

30 and 34 are coupled to an external storage device. On the other hand, if the external storage device memory configuration is as shown in FIG. 2B, the boot program stored in the two

SoC ROMs

102 and 142 reads data from the

external storage devices

12 and 16 at the starting location 0000_0000 and 0000_0000, the circuit in FIG. 1B cannot be further simplified to be commonly coupled to an external storage device because the two SoC boot program reads data from the same starting location. That is, two

external storage devices

12 and 16 are needed, and the two

external storage devices

12 and 16 have wasted free space.

After the ROM goes down the system on chip (Tape out), it cannot be modified unless the Mask (Mask) is modified. In other words, if the memory configuration of the two

soc

10 and 14 in the external storage device is as shown in fig. 2B, the two

external storage devices

12 and 16 are used in the whole soc of fig. 1B unless the contents of the rom 102 or the rom 142 in the

soc

10 or 14 are modified by modifying the mask.

FIGS. 3A and 3B are schematic diagrams of a system-on-chip 30 and a system thereof according to an embodiment of the invention. As shown in fig. 3A, the booting method provided by the present invention utilizes the springboard program and the target program to enable the system-on-chip 30 and the other system-on-chip 34 to share the same external storage device 32; the external storage device 32 already stores existing programs or data, and the free space of the external storage device 32 is larger than the size of the springboard program and the size of the target program. The system-on-chip 30 includes a processing unit 300, a read-only memory 302, a random access memory 304, and an input port 306. The embodiment of the invention stores the starting program in the read-only memory 302, firstly judges the signal of the input port 306 to determine the position of the springboard program, then reads the springboard program from the external storage device 32 to the random access memory 304 and then executes the springboard program by the processing unit 300, the information of the position, the size and the like of the real target program is described in the springboard program, and then the processing unit 300 can read the target program from the external storage device 32 to the random access memory 304 and then execute the target program to complete the starting program. In addition, the system-on-chip 30 may be decorated differently depending on the scenario in which it is used. For example, the system-on-chip 30 in FIG. 3B removes the RAM 304 to save cost compared to FIG. 3A.

With reference to FIG. 4, regarding the operation of the system-on-chip 30, FIG. 4 is a diagram illustrating an embodiment of a memory configuration of the external storage device 32. As shown in FIG. 4, the external storage device 32 has existing data and programs at 4000_0000 to 7FFF _ FFFF and C000_0000 to EFFF _ FFFF. In the embodiment, a jump program is stored at F000_0000, and the start program can determine the start position of the jump program to be F000_0000 by the processing unit 300 first reading the input signal from the input port 306. Then, the jump board program is loaded into the random access memory 304 and executed by the processing unit 300, so as to execute the target program, thereby completing the boot-up procedure of the soc 30.

Since the content in the external storage device 32 can be modified by the user at any time, the user can modify the springboard program stored in the external storage device 32 at any time, so that the processing unit 300 can correspondingly change the position when reading the target program, and the boot method of the boot program of the system on chip can be dynamically modified under the condition that the boot program in the read-only memory is not modified.

The RAM 304 is not an essential component during the boot process. For example, in the memory configuration of the external storage device shown in fig. 4, the addresses of the external storage device 32 are 0000_0000 to 3FFF _ FFFF, and the system on chip 30 can directly execute the operation by accessing the external storage device 32, loading the instruction portions of the target program and the jumper program into the processing unit 300, and temporarily storing the intermediate data in the external storage device 32 during the operation of the processing unit 300, so as to implement the boot process.

In addition, the object program is loaded through the springboard program, wherein the user can modify the springboard program stored in the external storage device according to different usage scenarios at any time, and further, the memory allocation of the object program in the external storage device does not need to perform byte alignment (word alignment), and does not need to include a file header (header), an end-of-file (end-of-file), a check code (checksum), or a hash value (hash value), but is not limited thereto. For example, FIG. 5A is a diagram illustrating an external storage device memory arrangement according to an embodiment of the invention. In FIG. 5A, the target program starts with bit3 of 8000_0002 and does not include file header, file end, checksum or hash value, so that the user can still complete the loading, reading and executing of the target program by modifying the jump board program. Similarly, the memory configuration of the springboard program in the external storage device does not need to be byte aligned, and is not described herein again.

FIG. 5B is a diagram illustrating an external storage device memory arrangement according to an embodiment of the present invention. In fig. 5B, since the continuous free space of 0000_0000 to 3FFF _ FFFF in the memory configuration of the external storage device 32 is not enough to accommodate the target program, in an embodiment, the user can still modify the jump board program to divide the target program into two segments, and store the two segments in 0000_0000 to 3FFF _ FFFF and 8000_0000 to 8FFF _ FFFF, respectively, and in the boot program of the system-on-chip 32, the two segments are loaded into the ram 304 in sequence through the modified jump board program and then executed by the processing unit 300 to complete the boot program.

It should be noted that, for example, the springboard program and the target program may be divided into several segments according to the free space of the external storage device, or the springboard program may further distinguish the primary springboard program and the plurality of secondary springboard programs, etc., the primary springboard program is read by the boot program in the rom 302, the plurality of secondary springboard programs are read by the primary springboard program, and finally the plurality of target program segments are read to complete the boot process. It is not limited to these modifications and variations which will be apparent to those skilled in the art.

Finally, the operation of the booting method of the system-on-chip 30 can be summarized as a system-on-chip booting method flow 60, as shown in FIG. 6. The system-on-chip boot method flow 60 includes the following steps:

step 600: and starting.

Step 602: the system-on-chip 30 determines the start position of the springboard process through external input.

Step 604: the springboard program is read from the external storage device 32 and executed by the processing unit 300.

Step 606: step 604 is repeated until all the springboard programs have been read and executed.

Step 608: the target program is read from the external storage device 32 through the jump board program, and the processing unit 300 executes the target program.

Step 610: step 608 is repeated until all target programs have been read and executed.

Step 612: and (6) ending.

In step 602, the soc 30 obtains an external input signal through the input port 306 to determine a start position of the springboard process, wherein the external input signal can be a direct address of the start position or a corresponding table stored in the rom 302. For example, in one embodiment, the input port 306 has a bit, and an input value of 0 indicates that the start position of the jump program in the external storage device 32 is 0000_0000, and an input value of 1 indicates that the start position of the jump program in the external storage device 32 is F000_ 0000. In addition, the type of the Input port is not limited to General-Purpose Input/Output (GPIO) of the system on chip, and may also be Bonding Option (Bonding Option), direct addressing or indirect addressing mode, which is a common technique of those skilled in the art and will not be described herein.

In

steps

606 and 610, due to the memory allocation factor of the external storage device, the target program and the diving board program may not be continuously stored in a space of the external storage device (as shown in fig. 5B), so the diving board program and the target program may need to be divided into a plurality of segments, and after the start position of the diving board program in step 602, the system-on-chip 30 still needs to read and execute the diving board program for a plurality of times, and then reads and executes the target program by the diving board program, so as to implement the complete boot process.

For other steps of the system-on-chip booting method process 60, reference is made to the foregoing description, and further description is omitted here.

It is noted that the external input signal is external to the system-on-chip 30, not external to the entire system. If there are multiple SoCs in the electronic device, as long as other SoCs complete initialization earlier than SoC 30, the external signal of the system-on-chip 30 can be obtained by a wire-bonding selection or a programmable logic device coupling in other systems-on-chip, wherein the Programmable logic device can be a One-Time Programmable (OTP) memory, a FTP memory, a Multiple-Time Programmable (MTP) memory, such as an electronic fuse (eFuse), an antifuse (Anti-fuse), a read-only Memory (ROM), a random access Memory (ram), a compact disc read only Memory (CD-ROM), a magnetic Tape (magnetic Tape), a Floppy Disk (flexible Disk), an Optical Data Storage Device (Optical Data Storage Device), and a Non-volatile Memory (Non-volatile Memory), but not limited thereto.

For example, fig. 7 is a schematic diagram of a system on a chip according to an embodiment of the invention. In FIG. 7, system-on-chip 30, a SoC1, a SoC2, and an eFuse are integrated into a system, wherein the initialization sequence of SoC1 and the eFuse is completed earlier than that of system-on-chip 30, and then coupled to input port 306 of system-on-chip 30 through the output port of the eFuse. One of ordinary skill in the art can select an appropriate configuration for the applicable device. Such circuit design methods are well known to those skilled in the art and will not be described herein.

Furthermore, although the system-on-chip 30 and the external storage device 32 are shown as separate units for illustrative purposes, all or a portion of these units may be integrated into the same circuit. For example, the external storage device 32 and the System on chip 30 may be integrated into the same System on chip through a System in a Package (SIP). In one embodiment, the electronic fuses and the anti-fuses may be separate components or integrated with the system-on-chip 30.

The foregoing embodiments are provided to illustrate the concepts of the invention, and various modifications can be made by those skilled in the art without limiting the scope of the invention. Therefore, as long as the booting method of the system on chip can dynamically change the reading position of the target program in the external storage device after reading a signal, the requirement of the invention can be met, and the invention belongs to the scope of the invention.

In summary, the present invention provides a boot method capable of dynamically modifying a boot program of a system-on-chip without modifying a boot program in a rom, the boot method changes a start position of a boot program read by the boot program by reading an external input signal, and then reads a real object program by the boot program.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should be covered by the present invention.

Claims

1. A boot method, suitable for a boot program of a system-on-chip, wherein the system-on-chip includes an input port for providing external input signals, a processing unit for executing programs, and a read-only memory for storing an initial boot program, the boot method comprising:

selecting a starting position of a springboard program;

reading the springboard program and executing the springboard program by the processing unit; and

executing the target program by the processing unit through the springboard program;

wherein, the springboard program and the target program are stored in an external storage device;

the springboard program is used for reading the target program, and the target program is used for executing the starting program.

2. A boot method as recited in claim 1, wherein said rom is programmed to be non-alterable.

3. A boot method according to claim 1, wherein the external storage device has an existing program or data and has a free space larger than the size of the target program and the diving board program.

4. A boot method as recited in claim 1, wherein said system-on-chip further comprises a random access memory for storing code for execution by said processing unit;

wherein, the step of reading the springboard program and executing the springboard program by the processing unit is reading the springboard program, downloading the springboard program to the random access memory, and executing the springboard program by the processing unit.

5. A boot method as recited in claim 1, wherein said system-on-chip further comprises a random access memory for storing code for execution by said processing unit;

wherein, the step of executing the target program by the processing unit through the springboard program downloads the target program into the RAM through the springboard program, and the processing unit executes the target program.

6. A power-on method as claimed in claim 1, wherein the start position of the springboard program is controlled by an external signal inputted from the input port.

7. A boot method according to claim 6, wherein said input port is a general purpose input/output port.

8. The booting method of claim 1 wherein the system-on-chip further includes a wire-bonding option or a programmable logic device for directly or indirectly determining the starting position of the jumping program.

9. The boot method of claim 8 wherein said programmable logic device is a write-once memory, a write-many memory.

10. A boot method according to claim 1, wherein said diving board program is composed of a plurality of sub-diving board programs.

11. A boot method according to claim 1, wherein the target program is composed of a plurality of sub-target programs.

12. A boot method according to claim 1, wherein said springboard program is not aligned with a location of an external storage device.

13. A boot method according to claim 1, wherein the target program is not aligned with a location of an external storage device.

14. A boot method according to claim 1, wherein said external storage device is serial or parallel addressed.

15. A boot method as recited in claim 1, wherein the external storage device and the system-on-chip are integrated as a chip.