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CN113472343A - Construction method of logic gate - Google Patents

Construction method of logic gate Download PDF

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CN113472343A
CN113472343A CN202110794885.7A CN202110794885A CN113472343A CN 113472343 A CN113472343 A CN 113472343A CN 202110794885 A CN202110794885 A CN 202110794885A CN 113472343 A CN113472343 A CN 113472343A
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drain current
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CN113472343B (en
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陈杰智
汪倩文
冯扬
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Shandong University
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    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract

本发明公开一种逻辑门的构建方法,本方法使用输出为U型转移特性曲线的MOS管作为逻辑门的基本单元,基本单元的输入端输入包括源极电压、漏极电压、栅极电压在内的输入变量,输入变量的改变使得电荷的注入量发生改变,基本单元的输出端输出包括漏极电流、转移特性曲线、亚阈值摆幅和阈值电压在内的输出变量;单个MOS管独立实现逻辑门或者各MOS管通过串联、并联的方式实现逻辑门。相比传统逻辑门,本方法能够减小电路尺寸,提高面积使用效率,提高应用效率。

Figure 202110794885

The invention discloses a construction method of a logic gate. The method uses a MOS tube whose output is a U-shaped transfer characteristic curve as the basic unit of the logic gate. The change of the input variable changes the injection amount of charge, and the output terminal of the basic unit outputs output variables including drain current, transfer characteristic curve, sub-threshold swing and threshold voltage; a single MOS tube is independently implemented The logic gate or each MOS transistor realizes the logic gate by means of series or parallel connection. Compared with the traditional logic gate, the method can reduce the circuit size, improve the area use efficiency, and improve the application efficiency.

Figure 202110794885

Description

Construction method of logic gate
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a logic construction method, namely a logic gate designed based on a U-shaped transmission characteristic metal oxide semiconductor field effect transistor.
Background
The number of equivalent logic gates in a chip is defined as the integration level. The digital circuit is divided into small Scale integrated circuits SSI (Small Scale integration) according to the integration level, and the integration level is 1-10 logic gates/chips; MSI (Medium Scale integration) with an integration of 10-100 logic gates/slice; large Scale integrated circuit (LSI) with an integration level of more than 100 logic gates/chip; very Large Scale Integration (VLSI) circuit, each chip contains more than ten thousand equivalent logic gates.
Due to the limitations of semiconductor process technology development and the approaching physical device size limits, the size reduction of conventional integrated circuits and the increase in cell device density have met with increasing difficulties. The existing logic gate circuit is difficult to be smaller in size, high in power consumption and lower in working efficiency.
Disclosure of Invention
The invention aims to provide a method for constructing a logic gate, which uses a metal semiconductor field effect transistor with U-shaped transmission characteristics as a basic unit of the logic gate, and can reduce the circuit size, improve the area utilization efficiency and improve the application efficiency.
In order to solve the technical problem, the sampling technical scheme of the invention is as follows: a method of constructing a logic gate, comprising: an MOS tube with an output of a U-shaped transfer characteristic curve is used as a basic unit of a logic gate, input variables including source voltage, drain voltage and grid voltage are input to the input end of the basic unit, the injection quantity of charges is changed due to the change of the input variables, and output variables including drain current, the transfer characteristic curve, sub-threshold swing and threshold voltage are output from the output end of the basic unit; the logic gate is realized independently by a single MOS tube or realized by all MOS tubes in a serial or parallel mode.
Further, a not gate is realized by using one MOS tube, and the realization process is as follows: at a large threshold voltage VthWhen the grid voltage is at a low level, the output drain current is at a high level, and when the grid voltage is at a high level, the output drain current is at a low level.
Further, an exclusive-or gate is realized by using one MOS transistor, and the realization process is as follows: using the grid voltage V of MOS tubeRThreshold voltage VthAs input variable, using the drain current of MOS transistor as output variable, when V isthAt a low level, VRWhen the level is low, the drain current is low, when VthAt a low level, VRAt high level, the drain electrodeThe current is high when VthIs at a high level, VRWhen the voltage is low, the drain current is high, and when V is lowthIs at a high level, VRAt high, the drain current is low.
Further, the AND gate is realized by using two MOS tubes connected in series, and the realization process is as follows: with threshold voltage V of two MOS transistors connected in seriesth1And Vth2As an input variable, taking the drain current of two MOS tubes connected in series as an output variable; keeping the grid voltage of two MOS tubes at low level as reference when V isth1And Vth2All maintain high level, drain current is high level, when Vth1Is at a high level, Vth2When the voltage is at low level, one MOS transistor in series is turned on, the other MOS transistor is turned off, the drain current is at low level, and similarly, when V is at low levelth1At a low level, Vth2When high, the drain current is also low, when Vth1And Vth2When the two MOS tubes are kept at a low level, the two MOS tubes are cut off, and the drain current is low current.
Further, the AND gate is realized by using two MOS tubes connected in series, and the realization process is as follows: the threshold voltage V of two MOS tubesth1And Vth2Keeping the low level unchanged, namely taking the small threshold voltage as a reference, and keeping the grid voltage V of the two MOS tubes unchangedR1、VR2As input variable, the drain current of two MOS tubes is output variable when V isR1、VR2When the high level is input simultaneously, the output drain current is high level when VR1Input high level, VR2When the input is low level, the output drain current is low level, when V isR1Input low level, VR2When the high level is input, the output drain current is low level, when V isR1And VR2When a low level is inputted, the outputted drain current is at a low level.
Further, two MOS transistors connected in series are used to realize a nor gate, and the realization method is as follows: the threshold voltage V of two MOS tubes connected in seriesth1And Vth2As input variable, the grid voltage V of two MOS tubesR1、VR2Keeping high level input as reference, using two MOS tubesThe drain current after series connection is used as the output variable when Vth1And Vth2When both are kept at high level, the drain current is at low level, when V isth1Is at a high level, Vth2At low level or when Vth1Is at a low level, Vth2When the voltage is high level, one of the two MOS tubes in series is switched on, the other is switched off, the drain current is low level, and when the voltage is Vth1、Vth2When the low level is kept, the two MOS tubes are both conducted, and the drain current is high level.
Further, two MOS transistors connected in series are used to realize a nor gate, and the realization method is as follows: grid voltage V of two MOS tubes connected in seriesR1、VR2The drain current of two MOS tubes connected in series is used as an output variable as an input variable, and the threshold voltage V of the two MOS tubesth1And Vth2Keeping the high level constant as a reference when VR1、VR2When a high level is inputted at the same time, the drain current is at a low level when V isR1Input high level, VR2When the input voltage is low, the drain current is low, and when V isR1Input low level, VR2When the input voltage is high, the drain current is low, and when V is highR1、VR2When a low level is inputted at the same time, the drain current is at a high level.
Further, two MOS transistors connected in parallel are used to realize an or gate, and the realization method is as follows: the threshold voltage V of two parallel MOS tubesth1And Vth2Taking the drain current of two parallel MOS tubes as an output variable as an input variable, and taking the grid voltage V of the two parallel MOS tubesR1、VR2Holding the low level input as a reference when Vth1And Vth2When all are kept at high level, the drain current is high, when V isth1Is at a high level, Vth2At low level or when Vth1Is at a low level, Vth2When the voltage is high level, one of the two MOS tubes in parallel connection is switched on and the other is switched off, and because the two MOS tubes are in parallel connection, the drain current is high level, and when V is high levelth1、Vth2When the two MOS tubes are kept at a low level, the two MOS tubes are cut off, and the drain current is at a low level.
Further, using two parallelThe MOS tube realizes an OR gate, and the realization mode is as follows: grid voltage V of two parallel MOS tubesR1、VR2The drain current of two MOS tubes connected in parallel is used as an output variable as an input variable, and the threshold voltage V of the two MOS tubesth1And Vth2Keeping the low level constant as a reference when VR1、VR2When a high level is inputted at the same time, the drain current is at a high level when VR1Is at a high level, VR2At low level or when VR1Is at a low level, VR2When the voltage is high level, one of the two MOS tubes in parallel connection is switched on and the other is switched off, and because the two MOS tubes are in parallel connection, the drain current is high level, and when V is high levelR1、VR2When the two MOS tubes are kept at a low level, the two MOS tubes are cut off, and the drain current is at a low level.
Further, two parallel MOS are used to implement a nand gate, and the implementation manner is as follows: the threshold voltage V of two parallel MOS tubesth1And Vth2Taking the drain current of two parallel MOS tubes as an output variable as an input variable, and taking the grid voltage V of the two parallel MOS tubesR1、VR2Holding the high input as a reference when Vth1And Vth2When both are kept at high level, the drain current is at low level, when V isth1Is at a high level, Vth2At low level or when Vth1Is at a low level, Vth2When the voltage is high level, one of the two MOS tubes in parallel connection is switched on and the other is switched off, and because the two MOS tubes are in parallel connection, the drain current is high level, and when V is high levelth1、Vth2When the low level is kept, the two MOS tubes are both conducted, and the drain current is high level.
Further, two MOS transistors connected in parallel are used for realizing a nand gate, and the realization method is as follows: grid voltage V of two parallel MOS tubesR1、VR2The drain current of two MOS tubes connected in parallel is used as an output variable as an input variable, and the threshold voltage V of the two MOS tubesth1And Vth2Keeping the high level constant as a reference when VR1、VR2When a high level is inputted at the same time, the drain current is at a low level when V isR1Is at a high level, VR2At low level or when VR1Is at a low level, VR2When it is high, the drain current is low, when VR1、VR2The drain current is high while both remain low.
The invention has the beneficial effects that: the invention uses the metal oxide semiconductor field effect transistor with the output of U-shaped transfer characteristic curve as the basic unit of the logic gate circuit. The basic unit can independently realize the logic gate or each unit can realize the application of the logic gate in a serial connection and parallel connection mode. The invention discloses a method for integrating a logic circuit by using a single element and multiple elements by taking a cold source field effect transistor as an example, and the logic operation can be realized by a special threshold voltage change mechanism based on a metal oxide field effect transistor with a U-shaped transmission characteristic curve. The logic circuit design method can effectively reduce the circuit size, improve the area use efficiency and improve the application efficiency.
Drawings
FIG. 1 is a schematic diagram of basic unit structures of a conventional semiconductor field effect transistor and a heat sink field effect transistor;
FIG. 2 is a schematic diagram of a MOSFET logic symbol and NMOS logic gate circuit;
FIG. 3 is a schematic band diagram of the CS FET operating principle;
FIG. 4 is a schematic diagram of two logic gates implemented using a single unitary transistor device;
FIG. 5 is a schematic diagram of two logic gates implemented with two transistor devices in series;
FIG. 6 is a schematic diagram of two logic gates implemented with two transistor devices in parallel;
1. source, 2, drain, 3, substrate, 4, gate, 5, oxide layer.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
In this embodiment, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) logic circuit design method with U-shaped transmission characteristics is briefly described, taking a cold source fet as an example. The circuit is characterized in that the logic gate circuit design of a plurality of NMOS, PMOS or CMOS devices can be completed by using a single device or two devices.
A Logic Gate (Logic Gate) circuit refers to a unit circuit for implementing basic Logic operation and complex Logic operation, and is called a Gate circuit for short. The digital signal processing circuit is composed of devices such as a crystal diode, a crystal triode or an MOS (metal oxide semiconductor) transistor, a resistor and the like, and is the most basic unit circuit of a digital system. The basic logic gates include and gates, or gates and not gates, and the most commonly used logic gates include nand gates, nor gates, and nor gates, xor gates, and nor gates, and the like.
Fig. 1 shows a schematic diagram of basic unit structures of a conventional semiconductor Field Effect Transistor (FET) and a heat sink field effect transistor (CS FET). Fig. 1 (a) is a schematic diagram of a basic structural unit of a conventional semiconductor field effect transistor, and shows that the semiconductor field effect transistor has a source 1, a drain 2, a substrate 3, a gate 4 and an oxide layer 5. It uses P-type silicon chip as bottom 3, and utilizes diffusion method to form two N regions with high doping concentration on it, and can extract electrode, and on the silicon surface there is SiO2Insulating layer, SiO between source 1 and drain 22On the insulating layer, a metal electrode gate 4 is formed, typically of aluminum or copper. Between the gate 4 and the substrate 3 is SiO2The insulating layers are separated, so the transistor is called a metal-oxide-semiconductor field effect transistor, and is also called an insulated gate field effect transistor.
When no positive voltage is applied to the grid 4, two PN junctions with opposite directions exist between the source and the drain, even if a voltage U is applied between the drain and the sourceDSSince there is always one PN junction reverse biased, the transistor will not have current even when operating in the off state, IDS=0。
When a positive voltage U is applied to the gate 4GSElectrons will be induced (holes are repelled) at the substrate surface. But in UGSSmaller, the induced electron concentration is small and no conductive channel can be formed between the source and drain.
When U is turnedGSWhen the temperature is increased to a certain value, enough electrons are induced, an N-type layer is formed on the surface of the substrate, and the source electrode is connected with the drain electrode, so that a conductive channel (N-channel) is formed. At this time, the process of the present invention,applying a voltage U between the source and the drainDSThen a current I is generatedDI.e. the transistor is in the on state. The gate voltage at which the conductive channel begins to form is referred to as the turn-on voltage UT
If N-type silicon wafer is used as substrate, two P regions are diffused on the substrate, and negative voltage is applied to the grid, then P-channel enhancement type MOS tube can be formed.
The MOS integrated circuit mainly comprises 3 types: a PMOS circuit implemented with P-channel transistors; an NMOS circuit implemented with N-channel transistors; and meanwhile, the complementary symmetrical logic gate circuit CMOS circuit is realized by a PMOS tube and an NMOS tube.
Fig. 1 (b) shows a cooling Source field effect transistor (CS FET) which is composed of a Source 1 (Source), a Drain 2 (Drain), a Substrate 3 (Substrate), a Gate 4 (Gate), and a metal-oxide dielectric layer 5. The source electrode 1 is a heterojunction structure in which a channel material and graphene are combined by van der waals force. If the channel material of the source 1 and the drain 2 is n+(p+) Doping, then the graphene is p+(n+) And (4) doping. The electronic state density of graphene in the source heterojunction is in a linear decreasing trend, namely the state density of a source carrier is decreased along with the increase of a channel potential barrier, the state density is multiplied by a Fermi Dirac function, and the concentration distribution function of the source carrier is decreased in a super-exponential mode. The contribution of a Boltzmann thermal tail distribution tail at a higher energy position to off-state current is eliminated, most of source carriers are positioned near a Fermi energy level, the effect that the transistor breaks through a sub-threshold swing range (SS) limit is achieved, and the power consumption of the device is reduced.
Fig. 2 is a schematic diagram of a mosfet logic symbol and an NMOS integrated gate circuit. Fig. 2 (a) is 4 types of MOS field effect transistors: the device comprises an N-channel enhancement type MOS field effect transistor, an N-channel depletion type MOS field effect transistor, a P-channel enhancement type MOS field effect transistor and a P-channel depletion type field effect transistor. In the figure, the substrate is drawn with dashed lines for enhancement and with solid lines for depletion, the channel type being indicated by the substrate lead-out arrows, the arrows pointing inwards towards the N-channel and the arrows pointing outwards towards the P-channel.
FIG. 2 (b) is a diagram of 4 types of NMOS integrated gate circuits: NMOS inverter, NMOS NAND gate, NMOS NOR gate and NMOS and NOR gate. The structure is relatively complex.
FIG. 3 is a band diagram illustrating the operation principle of the CS FET. There are generally two transport mechanisms for carriers for a common field effect transistor: one is Thermal excitation of carriers (Thermal Emission), and the other is Band-to-Band Tunneling (BTBT) of carriers between bands. In the CS FET of the present invention, when the applied gate voltage is small, carriers are transmitted from the Valence Band Maximum (VBM) of the channel to the Conduction Band Minimum (CBM) of the drain, implementing Band-to-Band tunneling, so that the sub-threshold Swing (SS) breaks through the 60mV/dec limit; when the grid voltage is slowly increased, the channel potential barrier is reduced along with the increase of the voltage, and the channel CBM and the channel VBM are reduced along with the increase of the grid voltage, so that a carrier at the position of the channel VBM cannot tunnel to the drain electrode, and the output current is reduced; and continuously increasing the gate voltage, when the channel potential barrier is reduced to a certain degree, the hot carriers at the source electrode CBM are transmitted to the channel CBM, and the current is further increased along with the increase of the gate voltage. Therefore, in the process that the grid voltage is increased all the time, the output current is increased after being reduced, a U-shaped transmission characteristic curve appears, and window current appears.
At CS FET gate input voltage VRSource input source drain bias voltage VdAnd the drain outputs current. The transmission characteristic of the output of the device is U-shaped, so that the output has two threshold voltages (V) of one larger threshold voltage and one smaller threshold voltageth). The combination of these transistors may cause the high and low levels representing both signals to produce a high or low level signal after passing through them. The high and low levels may represent logically true and false or 1 and 0 in binary, respectively, to implement a logical operation.
In this embodiment, the U-shaped transfer characteristic curve means that the current is low in a window region, and if a certain voltage is not in the window region, the current is high regardless of the voltage.
The transistor units are field effect transistors with the output characteristics of U-shaped transfer characteristics, each transistor unit can independently complete tasks, and each unit can realize the construction of a logic gate in a serial or parallel mode.
In the embodiment, a cold source field effect transistor is adopted to realize the construction of a logic gate, and source electrode charges of the cold source field effect transistor are injected into a channel, and the charge injection is controlled by changing the doping concentration, the magnitude, the positive polarity, the negative polarity and the duration of gate voltage; the heterojunction structure of the source electrode of the cold source field effect transistor forms a U-shaped transfer characteristic curve output by the output layer, and the U-shaped discrete transfer characteristic curve is output by continuously changing the positive and negative or the large and small grid voltage. The larger the grid voltage and the duration time in the charge injection are, the more the injected charges are, the more the positive and negative polarities of the grid voltage can influence the offset direction of the threshold voltage, the more the charge injection is, the more the electrons captured by the grid oxide layer are increased, the more the threshold voltage is increased, and therefore the threshold voltage is controlled.
The cold source field effect transistor realizes a U-shaped transmission characteristic curve by changing the size of the grid voltage, the drain current is reduced and then increased in the process of applying the grid voltage, and a very small current is shown at a certain grid voltage.
The output process of the U-shaped discrete transfer characteristic curve is that in a cold source field effect transistor, through the doping of a heterojunction structure and materials of a source electrode, in the process of initially increasing the grid voltage, band-to-band tunneling is formed between a channel and a drain electrode, in the process of increasing the grid voltage, charges from the channel to the drain electrode are reduced, current is reduced, along with the further increase of the grid voltage, the potential barrier of the channel is further reduced, the thermal current transmission from the source electrode to the channel occurs, the current is increased along with the increase of the grid voltage, and finally the discrete transfer transmission characteristic curve is formed.
The minimum bit line current means that the output drain current is 1 × 10 when the drain current is assumed to be at the gate voltage of 0.5V-10uA/um, if the current obtained by connecting a plurality of transistors in parallel is the sum of the currents of single transistors, if the current obtained by connecting a plurality of transistors in series is the current of single transistor.
Both logic gate functions can be realized with only one transistor device.
The first method comprises the following steps: NOT (NOT) (FIG. 4 (a))
At a large threshold voltage VthAs reference (1), when VRWhen the output current is low level (0), the output drain current is high current (1); when V isRAt high level (1), the output drain current is low current (0). Thus conforming to the logic operation of the not gate. A NOT gate (NOT gate), also called inverter, is a basic unit of a logic circuit, and has an input terminal and an output terminal. The output terminal is at a low level (logic 0) when the input terminal thereof is at a high level (logic 1), and at a high level when the input terminal thereof is at a low level. That is, the level states of the input terminal and the output terminal are always inverted.
And the second method comprises the following steps: XOR gate (XOR) (FIG. 4 (b))
Logic gate still formed of a single device, at which time the threshold voltage V isthIs also one of the considerations. When is expressed as VthWhen it is at low level (0), when V is the referenceRWhen the level is low (0), the output drain current is small current (0); when V isRAt high level (1), the output current is high current (1). When is expressed as VthWhen V is set to high level (1) as referenceRWhen the output current is low level (0), the output drain current is high current (1); when V isRAt high level (1), the output drain current is low current (0).
A variety of logic gate functions can be achieved using two transistor devices.
When two transistors are connected in series:
the first method comprises the following steps: AND gate (AND) (FIG. 5 (a) (b))
At this time, the threshold voltages V of the two devices are adjustedth1And Vth2As input variables, let VR1And VR2The low level input is kept as a reference. When V isth1And Vth2When the output drain current is kept at a high level (1), the output drain current is a high current (1); when V isth1Is a high level (1) input, the device 1 is on when Vth2When the input is low level (0), the device is cut off, so that low current (0) is output; in the same way, when Vth1Is a low level input (0), Vth2When the input is high level input (1), low current (0) is output; when V isth1And Vth2All remain at low level (0)Both devices are off, and the output current is low (0).
The threshold voltages V of the two devices can also be adjustedth1And Vth2Keeping the low level constant, i.e. with reference to a small threshold voltage, VR1And VR2As input variables. When V isR1And VR2When a high level (1) is input at the same time, the device outputs a high current (1); when V isR1Input high level (1), VR2When a low level (0) is input, the device current outputs a low current (0); in the same way, when VR1Input low level (0) VR2When a high level (1) is input, the device outputs a low current (0) similarly; when V isR1And VR2When a low level (0) is input at the same time, the device outputs a low current (0).
AND gates (AND gates) are also called AND circuits. Is the basic logic gate that performs the and operation. There are multiple inputs, one output. The output is high when all inputs are high (logic 1) at the same time, and low (logic 0) otherwise.
And the second method comprises the following steps: and a NOR gate (NOR) formed by combining an OR gate and a NOR gate. (FIG. 5 (c) (d))
At this time, the threshold voltages V of the two devices are adjustedth1And Vth2As input variables, let VR1And VR2And keeping the high-level input as a reference. When V isth1And Vth2When the high level (1) is kept, the output current is low current (0); when V isth1Is high level (1) input, device 1 is off when Vth2When the input is low level (0), the device is conducted, so that low current (0) is output; in the same way, when Vth1Is a low level input (0), Vth2When the input is high level input (1), low current (0) is output; when V isth1And Vth2When both are kept at low level (0), both devices are turned on, and the output current is high current (1).
The threshold voltages V of the two devices can also be adjustedth1And Vth2Keeping the high level constant, i.e. with a large threshold voltage as reference, VR1And VR2As input variables. When V isR1And VR2When a high level (1) is input at the same time, the device outputs a low current (0); when V isR1Input high level (1), VR2When a low level (0) is input, the device current outputs a low current (0); in the same way, when VR1Input low level (0) VR2When a high level (1) is input, the device outputs a low current (0) similarly; when V isR1And VR2When a high level (1) is input at the same time, the device outputs a high current (1).
When two devices are connected in parallel:
the first method comprises the following steps: OR gate (OR) (FIG. 6 (a) (b))
At this time, the threshold voltages V of the two devices are adjustedth1And Vth2As input variables, let VR1And VR2The low level input is held as a reference. When V isth1And Vth2When the high level (1) is kept, the output current is high current (1); when V isth1Is a high level (1) input, the device 1 is on when Vth2When the input is low level (0), the device is cut off, and high current (1) is output because the device is connected in parallel; in the same way, when Vth1Is a low level input (0), Vth2When the input is high level input (1), high current (1) is output; when V isth1And Vth2When both are kept at the low level (0), both devices are turned off, and the output current is a low current (0).
The threshold voltages V of the two devices can also be adjustedth1And Vth2Keeping the low level constant as a reference, VR1And VR2As input variables. When V isR1And VR2When a high level (1) is input at the same time, the device outputs a high current (1); when V isR1Input high level (1), VR2When a low level (0) is input, the device current outputs a high current (1); in the same way, when VR1Input low level (0) VR2When a high level (1) is input, the device outputs a high current (1) as well; when V isR1And VR2When a low level (0) is input at the same time, the device outputs a low current (0).
Or gate (Or gate) is also called Or circuit. If, of several conditions, an event occurs as long as one is satisfied, this relationship is called an "OR" logical relationship. A circuit having an or logical relationship is called an or gate. The or gate has a plurality of inputs and an output, and the multiple-input or gate may be formed of a plurality of 2-input or gates. As long as one of the inputs is high (logic 1), the output is high (logic 1); the output is low (logic 0) only if all inputs are low (logic 0).
And the second method comprises the following steps: and the NAND gate (NAND) is formed by combining an AND gate and an NAND gate. (FIG. 6 (c) (d))
At this time, the threshold voltages V of the two devices are adjustedth1And Vth2As input variables, let VR1And VR2The high input is held as a reference. When V isth1And Vth2When the high level (1) is kept, the output current is low current (0); when V isth1Is high level (1) input, device 1 is off when Vth2When the input is low level (0), the device is conducted, and high current (1) is output because the two devices are connected in parallel; in the same way, when Vth1Is a low level input (0), Vth2When the input is high level input (1), high current (1) is output; when V isth1And Vth2When both are kept at low level (0), both devices are turned on, and the output current is high current (1).
The threshold voltages V of the two devices can also be adjustedth1And Vth2Keeping the high level constant as a reference, VR1And VR2As input variables. When V isR1And VR2When a high level (1) is input at the same time, the device outputs a low current (0); when V isR1Input high level (1), VR2When a low level (0) is input, the device current outputs a high current (1); in the same way, when VR1Input low level (0) VR2When a high level (1) is input, the device outputs a high current (1) as well; when V isR1And VR2When a high level (1) is input at the same time, the device outputs a high current (1).
In summary, with devices having U-shaped transfer characteristics, a maximum of six logic gates can be realized by two devices. The design method of the logic circuit can reduce the circuit size, improve the area use efficiency and improve the retrieval efficiency in the process.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.

Claims (11)

1.一种逻辑门的构建方法,其特征在于:使用输出为U型转移特性曲线的MOS管作为逻辑门的基本单元,基本单元的输入端输入包括源极电压、漏极电压、栅极电压在内的输入变量,输入变量的改变使得电荷的注入量发生改变,基本单元的输出端输出包括漏极电流、转移特性曲线、亚阈值摆幅和阈值电压在内的输出变量;单个MOS管独立实现逻辑门或者各MOS管通过串联、并联的方式实现逻辑门。1. the construction method of a logic gate, it is characterized in that: use the MOS tube that the output is U-shaped transfer characteristic curve as the basic unit of logic gate, the input terminal input of basic unit comprises source voltage, drain voltage, gate voltage The change of the input variable changes the amount of charge injected, and the output terminal of the basic unit outputs output variables including drain current, transfer characteristic curve, sub-threshold swing and threshold voltage; a single MOS tube is independent The logic gate is realized or each MOS tube realizes the logic gate by means of series or parallel connection. 2.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用一个MOS管实现非门,实现过程为:以大阈值电压Vth为基准,以MOS管的栅极电压为输入变量,以MOS管的漏极电流为输出变量,栅极电压为低电平时,输出的漏极电流为高电平,栅极电压为高电平时,输出的漏极电流为低电平。2. the construction method of logic gate according to claim 1 is characterized in that: use a MOS tube to realize NOT gate, and the realization process is: take the large threshold voltage V th as a reference, and take the gate voltage of the MOS tube as an input variable , Taking the drain current of the MOS tube as the output variable, when the gate voltage is low, the output drain current is high, and when the gate voltage is high, the output drain current is low. 3.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用一个MOS管实现异或门,实现过程为:以MOS管的栅极电压VR、阈值电压Vth为输入变量,以MOS管的漏极电流为输出变量,当Vth为低电平、VR为低电平时,漏极电流为低电平,当Vth为低电平、VR为高电平时,漏极电流为高电平,当Vth为高电平、VR为低电平时,漏极电流为高电平,当Vth为高电平、VR为高电平时,漏极电流为低电平。3. the construction method of logic gate according to claim 1 is characterized in that: use a MOS tube to realize XOR gate, and the realization process is: take the gate voltage VR of MOS tube, threshold voltage V th as input variables, Taking the drain current of the MOS tube as the output variable, when V th is low level and VR is low level, the drain current is low level, when V th is low level and VR is high level, the drain current is low level . The pole current is high, when V th is high and VR is low, the drain current is high, and when V th is high and VR is high, the drain current is low level. 4.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个串联的MOS管实现与门,实现过程为:以两个串联的MOS管的阈值电压Vth1和Vth2作为输入变量,以两个MOS管串联后的漏极电流作为输出变量;将两个MOS管的栅极电压保持低电平输入作为基准,当Vth1和Vth2都保持高电平时,漏极电流为高电平,当Vth1为高电平、Vth2为低电平时,串联的两个MOS管一个导通,一个戒指,漏极电流为低电平,同理,当Vth1为低电平、Vth2为高电平时,漏极电流也为低电平,当Vth1和Vth2都保持低电平时,两个MOS管都截止,漏极电流为低电流。4. the construction method of logic gate according to claim 1 is characterized in that: use two MOS tubes connected in series to realize AND gate, and the realization process is: with the threshold voltages V th1 and V th2 of two MOS tubes connected in series as Input variable, take the drain current of the two MOS transistors in series as the output variable; take the gate voltage of the two MOS transistors to keep the low level input as the reference, when both V th1 and V th2 remain high, the drain current is high level, when V th1 is high level and V th2 is low level, one of the two MOS transistors connected in series is turned on, and the other is a ring, and the drain current is low level. Similarly, when V th1 is low level When V th2 is at a high level, the drain current is also at a low level. When both V th1 and V th2 are kept at a low level, both MOS tubes are turned off and the drain current is low. 5.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个串联的MOS管实现与门,实现过程为:将两个MOS管的阈值电压Vth1和Vth2保持低电平不变,即以小阈值电压为基准,两个MOS管的栅极电压VR1、VR2作为输入变量,两个MOS管的漏极电流为输出变量,当VR1、VR2同时输入高电平时,输出的漏极电流为高电平,当VR1输入高电平,VR2输入低电平时,输出的漏极电流为低电平,当VR1输入低电平,VR2输入高电平时,输出的漏极电流为低电平,当VR1和VR2同时输入低电平时,输出的漏极电流为低电平。5. The construction method of logic gate according to claim 1, is characterized in that: use two MOS tubes connected in series to realize AND gate, and the realization process is: keep the threshold voltages V th1 and V th2 of two MOS tubes at low power It is flat and unchanged, that is, based on the small threshold voltage, the gate voltages VR1 and VR2 of the two MOS tubes are used as input variables, and the drain currents of the two MOS tubes are the output variables. When VR1 and VR2 are simultaneously input high When the voltage level is high, the output drain current is high level, when VR1 input high level, VR2 input low level, the output drain current is low level, when VR1 input low level, VR2 input high level When the level is low, the output drain current is low level, and when VR1 and VR2 input low level at the same time, the output drain current is low level. 6.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个串联的MOS管实现或非门,实现方式为:将两个串联MOS管的阈值电压Vth1和Vth2作为输入变量,两个MOS管的栅极电压VR1、VR2保持高电平输入为基准,以两个MOS管串联后的漏极电流作为输出变量,当Vth1和Vth2都保持高电平时,漏极电流为低电平,当Vth1是高电平、Vth2是低电平时或者当Vth1是低电平、Vth2是高电平时,串联的两个MOS管一个导通,一个截止,漏极电流是低电平,当Vth1、Vth2都保持低电平时,两个MOS管都导通,漏极电流为高电平。6. The construction method of logic gate according to claim 1, is characterized in that: use two series-connected MOS transistors to realize the NOR gate, and the realization mode is: the threshold voltages V th1 and V th2 of the two series-connected MOS transistors are used as Input variable, the gate voltages V R1 and V R2 of the two MOS tubes are kept at high level as the input, and the drain current of the two MOS tubes in series is used as the output variable. When both V th1 and V th2 are kept at high level , the drain current is low level, when V th1 is high level, V th2 is low level or when V th1 is low level, V th2 is high level, one of the two MOS transistors connected in series is turned on, and the other When it is turned off, the drain current is at a low level. When both V th1 and V th2 are kept at a low level, both MOS transistors are turned on and the drain current is at a high level. 7.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个串联的MOS管实现或非门,实现方式为:将两个串联MOS管的栅极电压VR1、VR2作为输入变量,以两个MOS管串联后的漏极电流作为输出变量,将两个MOS管的阈值电压Vth1和Vth2保持高电平不变,即以大阈值电压为基准,当VR1、VR2同时输入高电平时,漏极电流为低电平,当VR1输入高电平,VR2输入低电平时,漏极电流为低电平,当VR1输入低电平,VR2输入高电平时,漏极电流为低电平,当VR1、VR2同时输入低电平时,漏极电流为高电平。7. The construction method of logic gate according to claim 1, is characterized in that: use two MOS tubes connected in series to realize NOR gate, and the realization mode is: the gate voltages VR1 , VR2 of two MOS tubes connected in series As the input variable, the drain current of the two MOS transistors in series is used as the output variable, and the threshold voltages V th1 and V th2 of the two MOS transistors are kept at a high level, that is, based on the large threshold voltage, when V R1 When V R2 input high level at the same time, the drain current is low level, when VR1 input high level, VR2 input low level, the drain current is low level, when VR1 input low level, V R2 When a high level is input, the drain current is at a low level, and when both VR1 and VR2 are input at a low level, the drain current is at a high level. 8.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个并联的MOS管实现或门,实现方式为:将两个并联MOS管的阈值电压Vth1和Vth2作为输入变量,以两个MOS管并联后的漏极电流作为输出变量,将两个并联MOS管的栅极电压VR1、VR2保持低电平输入作为基准,当Vth1和Vth2都保持高电平时,漏极电流为高电流,当Vth1是高电平、Vth2是低电平时或者当Vth1是低电平、Vth2是高电平时,并联的两个MOS管一个导通,一个截止,由于是并联,漏极电流为高电平,当Vth1、Vth2都保持低电平时,两个MOS管都截止,漏极电流为低电平。8. The method for constructing a logic gate according to claim 1 , wherein the OR gate is realized by using two parallel MOS tubes, and the implementation is as follows: the threshold voltages V th1 and V th2 of the two parallel MOS tubes are used as inputs Variable, take the drain current of the two MOS transistors in parallel as the output variable, and take the gate voltages VR1 and VR2 of the two parallel MOS transistors to keep the low level input as the reference, when both V th1 and V th2 are kept high. Usually, the drain current is high current. When V th1 is high level and V th2 is low level or when V th1 is low level and V th2 is high level, one of the two MOS transistors connected in parallel is turned on and the other is connected. When it is turned off, the drain current is at a high level due to the parallel connection. When both V th1 and V th2 are kept at a low level, both MOS tubes are turned off and the drain current is at a low level. 9.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个并联的MOS管实现或门,实现方式为:将两个并联MOS管的栅极电压VR1、VR2作为输入变量,以两个MOS管并联后的漏极电流作为输出变量,将两个MOS管的阈值电压Vth1和Vth2保持低电平不变,即以小阈值电压作为基准,当VR1、VR2同时输入高电平时,漏极电流为高电平,当VR1是高电平、VR2是低电平时或者当VR1是低电平、VR2是高电平时,并联的两个MOS管一个导通,一个截止,由于是并联,漏极电流为高电平,当VR1、VR2都保持低电平时,两个MOS管都截止,漏极电流为低电平。9. The construction method of logic gate according to claim 1 is characterized in that: use two parallel MOS tubes to realize OR gate, and the realization mode is: the gate voltages V R1 and V R2 of two parallel MOS tubes are used as The input variable takes the drain current of the two MOS transistors in parallel as the output variable, and keeps the threshold voltages V th1 and V th2 of the two MOS transistors at a low level, that is, with the small threshold voltage as the reference, when V R1 , V th2 When V R2 input high level at the same time, the drain current is high level, when VR1 is high level, VR2 is low level or when VR1 is low level, VR2 is high level, two parallel connected One of the MOS tubes is turned on and the other is turned off. Since they are connected in parallel, the drain current is at a high level. When both VR1 and VR2 are kept at a low level, both MOS tubes are turned off and the drain current is at a low level. 10.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个并联的MOS实现与非门,实现方式为:将两个并联MOS管的阈值电压Vth1和Vth2作为输入变量,以两个MOS管并联后的漏极电流作为输出变量,将两个并联MOS管的栅极电压VR1、VR2保持高电平输入作为基准,当Vth1和Vth2都保持高电平时,漏极电流为低电平,当Vth1是高电平、Vth2是低电平时或者当Vth1是低电平、Vth2是高电平时,并联的两个MOS管一个导通,一个截止,由于是并联,漏极电流为高电平,当Vth1、Vth2都保持低电平时,两个MOS管都导通,漏极电流为高电平。10. The method for constructing a logic gate according to claim 1, characterized in that: using two parallel MOSs to realize a NAND gate, the realization method is: using the threshold voltages V th1 and V th2 of the two parallel MOS tubes as inputs Variable, take the drain current of the two MOS transistors in parallel as the output variable, and take the gate voltages VR1 and VR2 of the two parallel MOS transistors to keep the high level input as the reference, when both V th1 and V th2 keep the high level Usually, the drain current is low level, when V th1 is high level, V th2 is low level or when V th1 is low level, V th2 is high level, one of the two MOS transistors connected in parallel is turned on, One is cut off, because it is in parallel, the drain current is high level, when both V th1 and V th2 are kept low level, both MOS transistors are turned on, and the drain current is high level. 11.根据权利要求1所述的逻辑门的构建方法,其特征在于:使用两个并联的MOS管实现与非门,实现方式为:将两个并联MOS管的栅极电压VR1、VR2作为输入变量,以两个MOS管并联后的漏极电流作为输出变量,将两个MOS管的阈值电压 Vth1和Vth2保持高电平不变,即以大阈值电压作为基准,当VR1、VR2同时输入高电平时,漏极电流为低电平,当VR1是高电平、VR2是低电平时或者当VR1是低电平、VR2是高电平时,漏极电流为低电平,当VR1、VR2都保持低电平时,漏极电流为高电平。11. The method for constructing a logic gate according to claim 1, characterized in that: using two parallel MOS transistors to realize a NAND gate, the implementation mode is: connecting the gate voltages VR1 and VR2 of the two parallel MOS transistors As the input variable, the drain current of the two MOS transistors in parallel is used as the output variable, and the threshold voltages V th1 and V th2 of the two MOS transistors are kept at a high level, that is, the large threshold voltage is used as the reference. When V R1 When VR1 and VR2 input high level at the same time, the drain current is low level, when VR1 is high level, VR2 is low level or when VR1 is low level, VR2 is high level, the drain current is For low level, when both VR1 and VR2 keep low level, the drain current is high level.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114024546A (en) * 2022-01-10 2022-02-08 之江实验室 Boolean logic implementation method, unit and circuit based on integrated storage and calculation transistor
US12166481B2 (en) 2022-01-10 2024-12-10 Zhejiang Lab Method, unit and circuit for implementing Boolean logic based on computing-in-memory transistor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120426A (en) * 1984-07-09 1986-01-29 Hitachi Ltd Logical gate circuit
CN102113114A (en) * 2008-07-25 2011-06-29 国立大学法人东北大学 Complementary logical gate device
CN102332907A (en) * 2011-07-26 2012-01-25 华南理工大学 Anti-NBTI effect hardening method based on CMOS digital logic gate circuit
CN110932542A (en) * 2019-11-15 2020-03-27 锐捷网络股份有限公司 MOS tube power supply circuit, control method, electronic device and storage medium
CN111628006A (en) * 2020-05-26 2020-09-04 山东大学 Data retrieval storage array

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120426A (en) * 1984-07-09 1986-01-29 Hitachi Ltd Logical gate circuit
CN102113114A (en) * 2008-07-25 2011-06-29 国立大学法人东北大学 Complementary logical gate device
CN102332907A (en) * 2011-07-26 2012-01-25 华南理工大学 Anti-NBTI effect hardening method based on CMOS digital logic gate circuit
CN110932542A (en) * 2019-11-15 2020-03-27 锐捷网络股份有限公司 MOS tube power supply circuit, control method, electronic device and storage medium
CN111628006A (en) * 2020-05-26 2020-09-04 山东大学 Data retrieval storage array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114024546A (en) * 2022-01-10 2022-02-08 之江实验室 Boolean logic implementation method, unit and circuit based on integrated storage and calculation transistor
US12166481B2 (en) 2022-01-10 2024-12-10 Zhejiang Lab Method, unit and circuit for implementing Boolean logic based on computing-in-memory transistor

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