CN113345490A

CN113345490A - Arbitration sense amplifier

Info

Publication number: CN113345490A
Application number: CN202110201889.XA
Authority: CN
Inventors: H·T·武; F·贝代斯基; S·B·塔塔普迪; 李贤见; A·S·埃尔曼苏里
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-03-02
Filing date: 2021-02-23
Publication date: 2021-09-03
Anticipated expiration: 2041-02-23
Also published as: CN113345490B; US11074956B1; US11514969B2; US20220020415A1

Abstract

The application relates to arbitrating sense amplifiers. The memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. The memory device may couple the second node and a third node if a voltage at the second node is associated with a first logic value stored at the memory cell, and the third node may be charged according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node to a reference voltage and may generate a signal indicative of a logical value stored by the memory cell.

Description

Arbitration sense amplifier

Cross referencing

Priority is claimed for united states patent application No. 16/806,942 entitled "ARBITRATED sense amplifier (ARBITRATED SENSE AMPLIFIER)" filed by wu (Vo) et al on 3/2 2020, which is assigned to its assignee and is expressly incorporated herein by reference in its entirety.

Technical Field

The technical field relates to arbitrating sense amplifiers.

Background

The following generally relates to one or more memory systems, and more particularly, to arbitrating sense amplifiers.

Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell can be programmed to one of two support states, typically designated by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, either of which may be stored. To access the stored information, components of the device may read or sense at least one stored state in the memory device. To access information, components of the device may write or program a state in the memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), and others. The memory devices may be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) may store its stored logic values for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAMs) may lose their stored state when disconnected from an external power source. FeRAM may be capable of achieving densities similar to volatile memory but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

In some cases, the memory device may perform a read operation on the memory cells. Performing a read operation may involve comparing a voltage generated based on a signal from a memory cell to a reference voltage using a sense amplifier. By performing the comparison, the memory device may be able to determine the logical value stored at the memory cell and may transmit the determined logical value to the host device.

Disclosure of Invention

An apparatus is described. The apparatus may include: a memory cell operable to store a logical value as one of a set of at least two logical values; a first node operable to selectively couple with the memory cell, wherein a voltage of the first node when coupled with the memory cell is based at least in part on the logical value and is associated with a first voltage swing; a signal generating component operable to selectively couple a second node with the first node, wherein a voltage of the second node when coupled with the first node is based at least in part on the voltage of the first node and is associated with a second voltage swing that is greater than the first voltage swing; a coupling component operable to selectively couple a third node with the second node based at least in part on whether the voltage of the second node is below a voltage threshold; and a comparison component operable to generate a signal indicative of the logical value based at least in part on a comparison of a voltage at the third node to a reference voltage.

An apparatus is described. The apparatus may include: a first gain component coupled with a first node and a second node, wherein the first node is operable to be coupled with a memory cell, and wherein the first gain component is operable to adjust a voltage of the second node based at least in part on a voltage of the first node; a precharge component operable to set a voltage of the third node to a first voltage; and a second gain component coupled with the second node and the third node and operable to: adjusting the voltage of the third node to a second voltage when the voltage of the second node is below a voltage threshold; maintaining the voltage of the third node at the first voltage when the voltage of the second node is greater than or equal to the voltage threshold; and a comparison component operable to indicate a logical value associated with the memory cell based at least in part on a comparison of the voltage of the third node to a reference voltage, wherein the reference voltage is between the first voltage and the second voltage.

A method is described. The method may include: coupling a memory cell with a first node, wherein a voltage at the first node is based at least in part on a logic value the memory cell is coupled with and stored by the first node; coupling the first node and a second node after the memory cell is coupled with the first node, wherein a voltage at the second node is based at least in part on the first node being coupled with the second node and the voltage at the first node; after the first node is coupled with the second node, coupling the second node with a third node based at least in part on the voltage at the second node and a voltage threshold; comparing a voltage at the third node to a reference voltage after the third node is coupled with the second node; and generating a signal indicative of the logical value stored by the memory cell based at least in part on the comparison.

Drawings

FIG. 1 illustrates an example of a system supporting arbitrated sense amplifiers in accordance with examples disclosed herein.

FIG. 2 illustrates an example of a memory die supporting arbitrated sense amplifiers in accordance with examples disclosed herein.

FIG. 3A illustrates an example of an arbitrated sense circuit supporting arbitrated sense amplifiers according to an example disclosed herein.

FIG. 3B illustrates an example of a timing diagram supporting an arbitrated sense amplifier according to an example disclosed herein.

FIG. 4 shows a block diagram of a memory device supporting arbitrated sense amplifiers, according to an example disclosed herein.

FIGS. 5-7 show flow diagrams illustrating one or more methods of supporting arbitrating sense amplifiers in accordance with examples disclosed herein.

Detailed Description

Some sensing schemes for reading a memory cell may involve generating a voltage that depends on the state of the memory cell and then comparing the generated voltage to a reference voltage. The greater the difference between the generated voltages associated with different states of a memory cell, which may be referred to as a read window or read budget in some cases, the greater the accuracy and reliability of the sensing scheme may also be. The following disclosure describes methods and apparatus that may be configured to increase the difference between voltage levels associated with different states of a memory cell.

In one example, a memory device may couple a memory cell with a first node via a digit line. The voltage of the first node may represent a logical value (logical state) stored by the memory cell, and thus may be at a first value if the memory cell stores a first logical value and may be at a second value if the memory cell stores a second logical value. The first node, in turn, may be coupled with a second node, where a difference between a voltage of the second node associated with the first logical value (e.g., when the memory cell stores the first logical value) and a voltage of the second node associated with the second logical value (e.g., when the memory cell stores the second logical value) is greater than a difference between corresponding voltages of the first node (e.g., a voltage swing at the second node, which may be considered to be a difference between voltages at the second node when the memory cell stores the first logical value versus the second logical value, may be amplified or otherwise increased relative to the voltage swing at the first node).

Once the first node and the second node are coupled, the memory device may selectively couple the second node and the third node-e.g., based on whether the voltage at the second node is above or below a threshold level (voltage threshold). For example, if the voltage of the second node is associated with a first logic value, a transistor, which may be referred to as an arbiter or gatekeeper (gatekeeper) transistor, may couple the second node with a third node, and the voltage of the third node may change (adjust) accordingly. However, if the voltage of the second node is associated with the second logic value, the transistor may not couple the second node and the third node, and the voltage of the third node may not change (adjust) -e.g., the voltage of the third node may instead remain at some other voltage to which the third node was previously biased (e.g., precharged).

By setting (e.g., precharging or otherwise biasing) the third node to an initial voltage and then adjusting the voltage of the third node if the memory cell stores a first logical value (and bringing the third node to the initial voltage if the memory cell stores a second logical value), the difference between the voltage at the third node associated with the first logical value and the voltage at the third node associated with the second logical value may be increased (e.g., based on setting the initial voltage of the third node to a desired difference relative to the adjusted voltage associated with the first logical value), thereby enabling an amplified read window and voltage swing at the third node relative to the voltage swing at the second node. After the time when selective coupling would potentially occur, the memory device may compare the voltage at the third node to a reference voltage and may generate a signal indicative of a logical value stored by the memory cell based on the comparison.

The features of the present invention are first described in the context of the memory system and die described with reference to FIGS. 1-2. Features of the present invention are described in the context of the arbitration sensing circuit and timing diagrams described with reference to fig. 3A and 3B. These and other features of the present invention are further illustrated by and described with reference to apparatus and flow diagrams associated with the arbitrated sense amplifier described with reference to FIGS. 4-7.

FIG. 1 illustrates an example of a system 100 supporting arbitrated sense amplifiers in accordance with examples disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, although aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

The system 100 may comprise part of an electronic device, such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, the system 100 may illustrate aspects of a computer, laptop, tablet, smart phone, cellular phone, wearable device, internet connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

At least part of the system 100 may be an instance of the host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform a process, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an internet connected device, a vehicle controller, or some other stationary or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof, that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

Memory device 110 may be a stand-alone device or component operable to provide physical memory addresses/space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to work with at least one or more different types of host devices. Signaling between the host device 105 and the memory device 110 is operable to support one or more of: modulation schemes used to modulate signals, different pin configurations used to pass signals, various form factors of the physical packaging of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may function as a slave to host device 105 (e.g., in response to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input/output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input/output controllers. Components of the host device may be coupled to each other using a bus 135.

The processor 125 is operable to provide control or other functionality for at least part of the system 100 or at least part of the host device 105. The processor 125 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 may be an example of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a general purpose GPU (gpgpu), or a system on a chip (SoC), among other examples. In some examples, the external memory controller 120 may be implemented by the processor 125 or may be part of the processor 125.

The BIOS component 130 may be a software component that includes a BIOS operating as firmware that may initialize and run various hardware components of the system 100 or the host device 105. The BIOS component 130 may also manage the flow of data between the processor 125 and various components of the system 100 or host device 105. The BIOS component 130 may include programs or software stored in one or more of Read Only Memory (ROM), flash memory, or other non-volatile memory.

Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support data storage of a desired or specified capacity. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more blocks, one or more sectors) where each memory cell is capable of storing at least one bit of data. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or multi-die package or a multi-chip memory or multi-chip package.

Device memory controller 155 may include circuitry, logic, or components operable to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions that enable memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to components of memory device 110. The device memory controller 155 is operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, device memory controller 155 can control the operations of memory device 110 described herein in connection with local memory controller 165 of memory die 160.

In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store data for host device 105 or a read command indicating that memory device 110 is to provide data stored in memory die 160 to host device 105.

The local memory controller 165 (e.g., local to the memory die 160) is operable to control the operation of the memory die 160. In some examples, local memory controller 165 is operable to communicate (e.g., receive or transmit data or commands or both) with device memory controller 155. In some examples, memory device 110 may not include device memory controller 155, and local memory controller 165 or external memory controller 120 may perform the various functions described herein. Thus, local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, or processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165, or both, may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of device memory controller 155 or local memory controller 165, or both.

The external memory controller 120 is operable to enable transfer of one or more of information, data, or commands between components of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may translate, or translate, communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105 or functions thereof described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some examples, external memory controller 120 or its functions described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channel 115 is operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and a memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, the channel 115 may include a first terminal including one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. The pins may be examples of conductive input or output points of devices of the system 100, and the pins may be operable to serve as part of a channel.

Channels 115 (and associated signal paths and terminals) may be dedicated to transferring one or more types of information. For example, the channels 115 may include one or more Command and Address (CA) channels 186, one or more clock signal (CK) channels 188, one or more Data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling may be communicated over channel 115 using Single Data Rate (SDR) signaling or Double Data Rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

In one example, memory device 110 may couple a memory cell to be read with a first node (e.g., by coupling the memory cell with a digit line and coupling the digit line with the first node). After the memory cell is coupled with the first node, the voltage of the first node may be at a first value if the memory cell stores a first logical value (in a first state) and may be at a second value if the memory cell contains a second logical value (in a second state). The memory device 110 may couple a first node and a second node, and the second node may be configured such that the difference between the voltage of the second node when the memory cell stores a first logical value and the voltage of the second node when the memory cell stores a second logical value is greater than the difference between the corresponding voltages of the first node-thus, the voltage swing or read window may be greater (amplified) at the second node relative to at the first node.

Memory device 110 may also selectively couple the second node and the third node depending on the logical value stored by the memory cell. For example, the transistor may be configured to couple the second node and the third node based on how the voltage at the second node compares to the voltage threshold level (e.g., whether the voltage at the second node is below the voltage threshold level). For example, if the voltage at the second node is associated with a first logic value (e.g., below a threshold level), a transistor may couple the second node and a third node and may charge or otherwise adjust the voltage of the third node accordingly. However, if the voltage is associated with a second logic value, the transistor may not couple the second node and the third node, and the third node may not be charged or otherwise adjust its voltage — the third node may instead remain at some other voltage to which the third node may be previously set. Thus, a difference between a voltage at a third node associated with the first logical value and a voltage at a third node associated with the second logical value may be greater than a corresponding voltage at the second node, thereby implementing an amplified read window at the third node. The memory device 110 may compare the voltage at the third node to a reference voltage and may generate a signal indicative of a logical value stored by the memory cell based on the comparison.

FIG. 2 illustrates an example of a memory die 200 supporting arbitrated sense amplifiers in accordance with examples disclosed herein. The memory die 200 may be an example of the memory die 160 described with reference to FIG. 1. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205 that can each be programmed to store a different logic value (e.g., a programmed one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information (e.g., a logic 0 or a logic 1) at a time. In some examples, memory cell 205 (e.g., a multi-level memory cell) is operable to store more than one bit of information (e.g., logic 00, logic 01, logic 10, logic 11) at a time. In some examples, memory cells 205 may be arranged in an array, such as memory array 170 described with reference to fig. 1.

Memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) in a capacitor that represents a programmable state. In a FeRAM architecture, memory cell 205 may include a capacitor 240 comprising a ferroelectric material to store a charge and/or polarization representing a programmable state. Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 can be coupled with switching component 245 and a second node of capacitor 240 can be coupled with plate line 220. The switch component 245 may be an example of a transistor or any other type of switching device that selectively establishes or releases electronic communication between the two components.

The memory die 200 can include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a pattern, such as a grid-like pattern. The access line may be a conductive line coupled with the memory cell 205 and may be used to perform access operations on the memory cell 205. In some examples, word lines 210 may be referred to as row lines. In some examples, the digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or the like, are interchangeable without losing understanding or operation. Memory cells 205 may be positioned at intersections of word lines 210, digit lines 215, and/or plate lines 220.

Operations (e.g., reads and writes) may be performed on memory cells 205 by activating or selecting access lines (e.g., word lines 210, digit lines 215, and/or plate lines 220). By biasing the word line 210, digit line 215, and plate line 220 (e.g., applying a voltage to the word line 210, digit line 215, or plate line 220), a single memory cell 205 can be accessed at its intersection. Activating or selecting a word line 210, digit line 215, or plate line 220 can include applying a voltage to the respective line.

Access to memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from the local memory controller 265 and activate the wordline 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digit lines 215 based on the received column address. Plate driver 235 may receive a plate address from local memory controller 265 and activate plate line 220 based on the received plate address.

Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switch component 245. The capacitor 240 may be in electronic communication with the digit line 215 using a switching assembly 245. For example, the capacitor 240 may be isolated from the digit line 215 when the switch component 245 is deactivated, and the capacitor 240 may be coupled with the digit line 215 when the switch component 245 is activated.

The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing an access operation on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of the switch component 245 of the memory cell 205 and operable to control the switch component 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

The digit line 215 can be a conductive line connecting the memory cell 205 and the sense component 250. In some architectures, memory cells 205 may be selectively coupled with digit lines 215 during portions of an access operation. For example, the word line 210 and the switch component 245 of the memory cell 205 may operate to selectively couple and/or isolate the capacitor 240 and the digit line 215 of the memory cell 205. In some architectures, memory unit 205 may be in electronic communication (e.g., constant) with digit line 215.

The plate line 220 can be a conductive line in electronic communication with the memory cells 205 for performing access operations on the memory cells 205. The plate line 220 can be in electronic communication with a node of a capacitor 240 (e.g., the bottom of the cell). The plate lines 220 may cooperate with the digit lines 215 to bias the capacitors 240 during an access operation of the memory cells 205.

The sensing component 250 can determine a state (e.g., a polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine a logical value of the memory cell 205 based on the detected state. The sensing component 250 may include one or more components configured to amplify the difference between the voltage at the node when the memory cell 205 stores the first logical value and the voltage at the node when the memory cell 205 stores the second logical value (e.g., to increase the read window at the node). Such components may be described in more detail with reference to fig. 3. The detected logic value of the memory cell 205 may be provided as an output of the sensing component 250 (e.g., to the input/output 260) and may indicate the detected logic value to another component of the memory device 110 including the memory die 200.

Local memory controller 265 may control the operation of memory cells 205 through various components, such as row decoder 225, column decoder 230, plate driver 235, and sense component 250. Local memory controller 265 may be an example of local memory controller 165 described with reference to FIG. 1. In some examples, one or more of row decoder 225, column decoder 230, and plate driver 235 and sense component 250 may be co-located with local memory controller 265. The local memory controller 265 is operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 265 may generate row and column address signals to activate the target word line 210, target digit line 215, and target plate line 220. The local memory controller 265 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can vary and can differ for the various operations discussed in operating the memory die 200.

The local memory controller 265 is operable to perform one or more access operations to one or more memory units 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed or otherwise coordinated by local memory controller 265 in response to various access commands (e.g., from host device 105). The local memory controller 265 may be operable to perform other access operations not listed herein or other operations related to operations of the memory die 200 that are not directly related to accessing the memory units 205.

The local memory controller 265 is operable to perform read operations (e.g., sense operations) on one or more memory cells 205 of the memory die 200. During a read operation, the logic value stored in memory cells 205 of memory die 200 may be determined. Local memory controller 265 may identify the target memory cell 205 on which to perform a read operation. Local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled with a target memory cell 205. Local memory controller 265 can activate target word line 210, target digit line 215, and target plate line 220 (e.g., apply a voltage to word line 210, digit line 215, or plate line 220) to access target memory cell 205.

The target memory cell 205 may communicate a signal to the sense component 250 in response to biasing the associated access line. In the first phase, the sensing component 250 may amplify the signal (e.g., may amplify a difference between a voltage of the signal when the target memory cell 205 stores a first logic state and a voltage of the signal when the target memory cell 205 stores a second logic state). In the second stage, the sensing component may selectively pass the amplified signal (and thereby amplify the signal again) based on whether the voltage level of the amplified signal meets (e.g., is below) a threshold level. Passing the amplified signal may alter the voltage of the sensing node, and not passing the amplified signal may maintain the voltage of the sensing node at a previous voltage level. Thus, the second amplification stage may occur for a subset (e.g., one) of a set of logical values that may be stored by the target memory cell 205. In the third stage, the voltage of the sense node, which may or may not have been changed from the previously set (configured, biased, pre-charged) voltage (depending on the voltage level of the amplified signal generated in the first stage), may be compared to a reference 255 (which may be a reference voltage). May be compared to reference 255. Based on the comparison, the sensing component 250 can determine a logical value stored on the memory cell 205.

FIG. 3A illustrates an example of an arbitrated sense circuit 300-a supporting arbitrated sense amplifiers according to an example disclosed herein. The arbitration sensing circuit 300-a may be included in or coupled with the sensing component 250 described with reference to FIG. 2. Digit line 215-a may be an example of digit line 215 described with reference to figure 2.

Digit line 215-a may be selectively coupled with a memory cell 205 to be read, which memory cell 205 to be read may be referred to as a target memory cell 205 and may be operable to store a logic value as one of two or more logic values, as described with reference to FIG. 2. The SENa node 302, in turn, can be selectively coupled with the digit line 215-a, such as via a transistor (not shown). The SENa node 302 may be selectively coupled with ground via the ARDL2VSS transistor 304 (e.g., the SENa node 302 may be coupled with the drain of the ARDL2VSS transistor 304, and the source of the ARDL2VSS transistor 304 may be coupled with ground). The SENa node 302 may also be selectively coupled with a terminal of a cascode transistor 308 via an arispoff transistor 306 (e.g., the SENa node 302 may be coupled with a source of the arispoff transistor 306, and a drain of the arispoff transistor 306 may be coupled with a source of the cascode transistor). The SENa node 302 is labeled SENa in fig. 3A, but it should be understood that the SENa node 302 may alternatively be referenced by any other name.

Cascode transistor 308 (e.g., the drain of cascode transistor 308) may be coupled with SINa node 310. SINa node 310 may be selectively coupled with a first voltage source via an ARDL2VSS1 transistor 312 and may be selectively coupled with a second voltage source via an ARDLChF transistor 314. For example, SINa node 310 may be coupled with the source of ARDL2VDD1 transistor 312 (and the drain of ARDL2VDD1 transistor 312 may be coupled with a first voltage source), and SINa node 310 may be coupled with the drain of ARDLChF transistor 314 (and the source of ARDLChF transistor 314 may be coupled with a second voltage source), where ARDLChF transistor 314 may be a PMOS device in some cases. The SINa node 310 may also be coupled with a VBOOST capacitor 316. SINa node 310 may be selectively coupled with QV node 320 via arissoa transistor 318. For example, the SINa node 310 may be coupled with the source of an ARISOa transistor 318, and the QV node 320 may be coupled with the drain of the ARISOa transistor 318, where the ARISOa transistor 318 may be an NMOS device in some cases. It is understood that the aristoa transistor 318 may in some cases be a PMOS device or include more than one transistor or other switching component. It should also be understood that the aristoa transistor 318 may be replaced in some examples by a non-switching component, such as one or more diodes, configured to provide functionality attributed to the aristoa transistor 318 herein. The SINa node 310, first voltage source, and second voltage source are labeled SINa, VDD1, and VHSA, respectively, in fig. 3A, but it is understood that SINa node 310, first voltage source, and second voltage source may alternatively be referenced by any other name.

The QV node 320 may be selectively coupled with a second voltage source via an ARDLChF transistor 322. (e.g., QV node 320 may be coupled with the drain of ARDLC ChF transistor 322, and the source of ARDLC ChF transistor 322 may be coupled with a second voltage source, where ARDLC ChF transistor 322 may be a PMOS device.) QV node 320 may also be coupled with VSHIFT capacitor 324. The QV node 320 can also be coupled with a comparison component 325. The QV node 320 is labeled QV in fig. 3A, but it should be understood that the QV node 320 may alternatively be referenced by any other name.

The arbitrated sense circuit 300-a may contain a line coupled with a reference 255-a, which may be a reference voltage. The line coupled with the reference 255-a may be selectively coupled to the QR node 332 via the ARISOb transistor 328 (e.g., the QR node 332 may be coupled with the drain of the ARISOb transistor 328, and the source of the ARISOb transistor 328 may be coupled with the reference 255-a). QR node 332 may be coupled with VSHIFT capacitor 330, which is coupled to ground. In some cases, VSHIFT capacitor 330 and VSHIFT capacitor 324 may have the same capacitance. QR node 332 may also be coupled with comparison component 325. QR node 332 is labeled as QR in fig. 3A, but it should be understood that QR node 332 may alternatively be referenced by any other name.

Comparison component 325 may be configured to compare the voltage at QV node 320 with the voltage at QR node 332. The voltage at the QR node 332 may be equal to or otherwise based on the voltage of the reference 255-a (e.g., offset by the threshold voltage of the ARISOb transistor 328), and thus the voltage at the QR node 332 may likewise be referred to as the reference voltage. Comparison component 325 may generate output signal 326 indicating whether the voltage at QV node 320 is greater than or less than the voltage at QR node 332 based on comparing the voltage at QV node 320 with the voltage at QR node 332. Output signal 326 may thus indicate the logic state stored by memory cell 205 coupled with digit line 215. It should be understood that the output signal 326 may be single-ended or differential, and thus may be carried by any number of output lines coupled with the comparison component 325.

FIG. 3B illustrates an example of a timing diagram 300-B supporting an arbitrated sense amplifier according to an example disclosed herein. The ARDL2VSS signal 352 may be the voltage at the gate of the ARDL2VSS transistor 304; the ARDL2VDD1 signal 354 may be the voltage at the gate of the ARDL2VDD1 transistor 312; the ARDLChF signal 356 may be the voltage at the gates of transistors 314 and/or 322; word line signal 358 may be a voltage at a word line coupled with a memory cell selectively coupled with the digit line 215-a; the arispoff signal 360 may be the voltage at the gate of the arispoff transistor 306; the VBOOST signal 362 may be the voltage at the VBOOST capacitor 316; the aristoa signal 364 may be the voltage at the gate of the aristoa transistor 318; the ARISOb signal 366 may be the voltage at the gate of the ARISOb transistor 328; the SENa signal 368 may be the voltage at the SENa node 302; SINa signal 370 may be the voltage at SINa node 310; the QV signal 372 may be the voltage at the QV node 320; the output signal 374 may be the voltage at the gates of the transistors 336 and 338; signal 376 may be the voltage at the gate of transistor 344; and the signal 378 may be the voltage of the output signal 326.

The signals illustrated in FIG. 3B have various names, and these names may be present at respective nodes as corresponding labels in the arbitration sensing circuit 300-a of FIG. 3A. It is to be understood that these designations are exemplary only, and are not limiting. The signals corresponding to the gates of the transistors and the signals to the

capacitors

316, 324, and 330 illustrated in fig. 3B may be referred to as control signals.

At an initial time (e.g., prior to time 350-a), the SENa node 302 may be coupled to ground via the ARDL2VSS transistors 304, the ARDL2VSS transistors 304 may be activated because the ARDL2VSS signal 352 is at a high value. The SENa node 302 may be coupled with the digit line 215-a at an initial time (e.g., through a transistor, which may be included in the column decoder 230 or coupled with the column decoder 230). The SENa node 302, which is coupled to ground, may discharge the digit line 215-a (ground, release any charge stored in parasitic capacitance associated with the digit line 215-a). Additionally, at an initial time, the SENa node 302 may be isolated from the SINa node 310 because the arispoff transistor 306 may be deactivated because the arispoff signal 360 is at a low value.

At time 350-a, the ARDL2VSS transistor 304 may be deactivated (e.g., due to the transition of the ARDL2VSS signal 352 from a high voltage to a low voltage). Additionally, at or after time 350-a, the ARDL2VDD1 transistor 312, which may be referred to as a first precharge component, may be activated (e.g., due to the ARDL2VDD1 signal 354 transitioning from a low voltage to a high voltage). Activating ARDL2VDD1 transistor 312 may couple SINa node 310 with a first voltage source, which may begin biasing (e.g., precharging) SINa node 310 to a voltage supplied by the first voltage source, as illustrated in fig. 3B by an increase in the voltage of SINa signal 370 (which may correspond to the voltage of SINa node 310).

At time 350-b, the ARDL2VDD1 transistor 312 may be deactivated (e.g., due to the ARDL2VDD1 signal 354 transitioning from a high voltage to a low voltage). Additionally, at time 350-b, the ARDLC HF transistor 314, which may be referred to as a second precharge component, may be activated (e.g., due to the ARDLC HF signal 356 transitioning from a high voltage to a low voltage). Deactivating ARDL2VDD1 transistor 312 and activating ARDLChF transistor 314 may couple SINa node 310 with a second voltage source, which may begin biasing SINa node 310 to the voltage supplied by the second voltage source, as illustrated in FIG. 3B by a further increase in the voltage of SINa signal 370 starting at time 350-B.

Additionally, at or after time 350-b, the ARISOWF transistor 306 may be activated (e.g., due to the ARISOWF signal 360 transitioning from a low voltage to a high voltage). Activating arispoff transistor 306 may couple SENa node 302 and SINa node 310. When the SENa node 302 and the SINa node 310 are coupled, charge sharing between the SENa node 302 and the SINa node 310 may occur, which may result in an increase in the voltage of a SENa signal 368 (which may correspond to the voltage of the SENa node 302), as shown in FIG. 3B. Thus, the voltage of the SINa node 310 may stabilize at a certain voltage (reach a steady state voltage) based on the voltage supplied by the second voltage source, and the SENa node 302 may stabilize at a certain voltage (reach a steady state voltage) relative to the predefined value of the SINa node 310 (e.g., the voltage of the SINa node 310 minus the threshold voltage of the cascode transistor 308). Alternatively, in some cases, the ARISOWF transistor 306 may be activated at time 350-a (e.g., due to the ARISOWF signal 360 transitioning from a low voltage to a high voltage), in which case the voltage of the SENa signal 368 begins to increase at time 350-a.

Additionally, at time 350-B, the ARDLC HF transistor 322, which may be referred to as a third pre-charge component, may be activated (e.g., due to the ARDLC HF signal 356 transitioning from a high voltage to a low voltage), which may couple the QV node 320 with a second voltage source, which may begin to bias the QV node 320 to the voltage supplied by the second voltage source, as illustrated in FIG. 3B by the increase in the voltage of the QV signal 372 (which may correspond to the voltage of the QV node 320) beginning at time 350-B. As described herein, the steady state voltage reached by the QV node 320 between time 350-b and time 350-c can be considered (e.g., can be interpreted by the comparison component 325) to correspond to a first logical value stored at a memory cell of a set of logical values-e.g., as described in more detail elsewhere herein, the QV signal 372 can then change voltage if the memory cell stores a second logical value of a set of logical values. Performing operations at 350-a and 350-b may precharge the SENa node 302, the SINa node 310, and the QV node 320. In some cases,

transistors

312, 314, and 322 may be considered to include any number (e.g., three or one) of precharge components.

At 350-c,

transistors

314 and 322 may be deactivated (e.g., due to the ARDLChF signal 356 transitioning from a low voltage to a high voltage). The ARISOWF transistor 306 may also be deactivated at 350-c (or alternatively before time 350-c, or alternatively after time 350-c but before time 350-d) (e.g., due to the ARISOWF signal 360 transitioning from a high voltage to a low voltage).

After time 350-d, the word line 210 coupled with the target memory cell (e.g., the switching element 245 therein) may be activated, which may couple the target memory cell (e.g., the ferroelectric capacitor 240 therein) with the digit line 215-a, and thus the SENa node 302. If the word line 210 is positioned within the memory array such that the word line 210 is relatively close to the driver supplying the voltage to the word line 210, the word line 210 may have a voltage curve shown by curve 359-a. If the word line 210 is positioned within the memory array such that the word line 210 is relatively far from the driver, the word line 210 may have a voltage profile shown by the profile 359-b.

If the target memory cell stores a first logical value (e.g., a logical 1), then the SENa signal 368 may change according to the curve 369-a, and if the target memory cell stores a second logical value (e.g., a logical 0), then the SENa signal 368 may change according to the curve 369-b. The range or difference between the curve associated with the first logical value (e.g., 369-a) and the curve associated with the second logical value (e.g., 369-b) may be referred to as a voltage swing or read window associated with the SENa signal 368 and, thus, the SENa node 302. The curve with the higher voltage value of the two curves at a particular time (e.g., curve 369-a between 350-d and 350-e) may be referred to as the upper limit of the voltage swing at that particular time, and the curve with the lower voltage value at a particular time (e.g., curve 369-b between 350-d and 350-e) may be referred to as the lower limit of the voltage swing at that particular time.

At time 350-e, ARISOWF transistor 306, which may also be referred to as a signal generating component, may be activated (e.g., ARISOWF signal 360 may transition from a low voltage to a high voltage). Activating the arispoff transistor 306 may couple the SENa node 302 and the SINa node 310 and may enable charge sharing to occur between the SENa node 302 and the SINa node 310. Since the capacitance of SENa node 302, which may include the capacitance of digit line 215-a, is greater than the capacitance of SINa node 310, the magnitude of the voltage swing between curves 371-1 and 371-b may be greater than the voltage swing between curves 369-a and 369-b.

Additionally, at or after time 350-e, the VBOOST capacitor 316 may have a VBOOST signal 362 (e.g., a control signal) applied to one of its terminals. Applying VBSOOT signal 362 in this manner may increase the absolute voltage level of SINa node 310, as shown by the increase of SINa signal 370 after time 350-e, which may support the generation of a larger read window at SINa node 310, as well as other benefits that may be appreciated by one of ordinary skill in the art. It should be noted that in some examples, the VBOOST capacitor 316 may not be included in the arbitration sensing circuit 300-a and/or the VBOOST signal 362 may not be applied to the VBOOST capacitor 316 (e.g., a node of the VBOOST capacitor 316 coupled with the VBOOST signal 362 may alternatively be grounded). The combination of arispoff transistor 306 and cascode transistor 308 may be referred to as a first gain component. Furthermore, the charge sharing between the SENa node 302 and the SINa node 310 at or after time 350-e, which may occur via the ARISOWF transistor 306 and the cascode transistor 308 in some cases, may be a first amplification or gain phase due to the difference in voltage swing between the SINa signal 370 and the SENa signal 368.

At time 350-f, aristoa transistor 318, which may be referred to as an arbiter or a watchdog component and may additionally or alternatively be referred to as a coupling component or a second gain component, may be selectively activated or deactivated based on the voltage of the SINa node 310 (of the SINa signal 370) at time 350-f and based on the voltage of an aristoa signal 364, which may be applied to the gate of aristoa transistor 318. For example, at time 350-f, the ARISOa signal 364 may transition from a low voltage (low state) to a high voltage (high state).

If SINa signal 370 is at a voltage associated with the first logic value at time 350-f (e.g., at an upper limit of the voltage swing, such as following curve 371-a or otherwise above a voltage threshold), ARISOa transistor 318 may not be activated (may remain deactivated) or may otherwise isolate SINa node 310 from QV node 320 (e.g., because the voltage difference between ARISOa signal 364 and SINa signal 370 is too low, such as below the threshold voltage of ARISOa transistor 318; because the voltage of SINa signal 370 is greater than or equal to a voltage threshold level). In such cases, the voltage of the QV node 320 (the QV signal 372) may remain the same after time 350-f as before time 350-f (e.g., as shown in curve 373-a).

However, if the SINa signal 370 is at a voltage associated with the second logic value at time 350-f (e.g., at a lower limit of the voltage swing, such as following curve 371-b or otherwise below a voltage threshold), the ARISOa transistor 318 may be activated (e.g., because the voltage difference between the ARISOa signal 364 and the SINa signal 370 is sufficiently high, such as greater than a threshold voltage of the ARISOa transistor 318; because the voltage of the SINa signal 370 is below a voltage threshold level). In such cases, the voltage of the QV node 320 may begin to change at time 350-f according to the SENa signal 368 (e.g., as shown by curve 373-b). In some cases, the voltage swing between curves 373-a and 373-b at time 350-g may be greater than the voltage swing between curves 371-a and 371-b at time 350-g. In some cases, in the case where the aristoa transistor 318 is activated, charge sharing may occur between the QV node 320 and the SINa node 310 after time 350-f (e.g., beginning at time 350-f), and the difference between the voltage swing between curves 373-a and 373-b and the voltage swing between curves 371-a and 371-b may be based on the capacitance of the QV node 320 being less than the capacitance of the SINa node 310. In some cases, the charge sharing between the QV node 320 and the SINa node 310 that may occur via the arissoa transistor 318 may be a second amplification or gain stage due to the difference in voltage swing between the QV signal 372 and the SINa signal 370. The second amplification stage may be arbitrated and selectively occur if the target memory cell 205 stores the second logic value instead of the first logic value.

The level to which the aristoa signal 364 is adjusted (i.e., the upper limit of the aristoa signal 364) may be configurable (e.g., as a trimming parameter; based on fuse settings). In some cases, the upper limit of the arissoa signal 364 can be dynamically configured (adjusted) based on the temperature of the memory device or other system that includes the sensing circuit 300-a (e.g., configured by a memory controller, such as the local memory controller 265). For example, if the temperature of a device containing the sensing circuit 300-a (e.g., the memory device 110) is above a threshold temperature, the ARISOa signal 364 may be adjusted to a higher or lower level than devices below or at the threshold temperature. The gate of the aristoa transistor 318 is thus operable to be biased between time 350-a and time 350-g at a bias voltage that is greater than or equal to an amount greater than a lower limit of the voltage swing at the SINa node 310 (e.g., a minimum point of a curve 371-b between 350-f and 350-g) by a threshold voltage of the aristoa transistor 318, such that the aristoa transistor 318 may be activated when the voltage at the SINa node 310 is associated with the curve 371-b and thus a second logic state. Additionally or alternatively, the gate of the aristoa transistor 318 may be operable to bias between time 350-a and time 350-g a bias voltage that is less than the sum of the upper limit of the voltage swing at the SINa node 310 (e.g., a maximum point greater than the curve 371-a between 350-f and 350-g) and the threshold voltage of the aristoa transistor 318, such that the aristoa transistor 318 may remain deactivated when the voltage at the SINa node 310 is associated with the curve 371-a and thus the first logic state. Although the present example refers to aristoa transistor 318 being illustrated as an NMOS device, it should be noted that a diode may be substituted for aristoa transistor 318 without departing from the scope of the present invention. Additionally or alternatively, the aristoa transistor 318 may be replaced with a PMOS device, or with any number and combination of multiple types of transistors or other switching components.

In some cases, at or after 350-f, the voltages at VSHIFT capacitors 324 and 330 (e.g., the control signal applied to the second node of VSHIFT capacitor 324 (where the first node of VSHIFT capacitor 324 is coupled with QV node 320) and also applied to the second node of VSHIFT capacitor 330 (where the first node of VSHIFT capacitor 330 is coupled with QR node 332)) may be shifted, which may shift signal 372 at QV node 320 up or down. For example, the voltages at

VSHIFT capacitors

324 and 330, labeled VSHIFT in fig. 3A, may be shifted down, which may reduce the absolute voltages at QV node 320 and QR node 332, which may support the use of lower voltage tolerance components within comparison component 325, as well as other benefits as may be appreciated by one of ordinary skill in the art. In some examples,

capacitors

324 and 330 may not be included in the arbitrated sensing circuit 300-a, and/or the voltages applied to the second node of VSHIFT capacitor 324 and the second node of VSHIFT capacitor 330 may not be shifted (e.g., the second node of VSHIFT capacitor 324 and the second node of VSHIFT capacitor 330 may alternatively be grounded).

At time 350-g,

transistors

318 and 328 may be deactivated (e.g., ARISOa signal 364 and ARISOb signal 366 may transition from high to low). The voltage at QR node 332 may be at a value equal to or otherwise based on the voltage of reference 255-a, which may be based on QR node 332 having been previously coupled with reference 255-a. The voltage at QR node 332 at times 305-f may have a value between the voltage of signal 372 at time 350-g when associated with a first logical value (e.g., following curve 373-a) and the voltage of signal 372 at time 350-g when associated with a second logical value (e.g., following curve 373-b). In some cases, VSHIFT capacitor 330 may be operable to adjust based on a voltage or control signal applied to one of its terminals. The voltage or control signal applied to the terminals of VSHIFT capacitor 330 may be the same as the voltage or control signal applied to the terminals of VSHIFT capacitor 324.

At time 350-g, the comparison component 325 may generate an output signal 374 at output 326 indicative of the logical value stored at the memory cell based on comparing the voltage at the QV node 320 to the reference voltage at the QR node 332 at time 350-g. Thus, the difference between curves 373-a and 373-b at time 350-g may correspond to the read window at QV node 320 and thus the read window of sensing circuit 300-a. If the signal 372 at the QV node 320 at time 350-g is associated with a first logical value (e.g., follows the curve 373-a), the first output 326 may output an output signal 374 that follows the curve 375-a. If the signal 372 at the QV node 320 at time 350-g is associated with a second logic value (e.g., follows the curve 373-b), the first output 326 may output an output signal 374 that follows the curve 375-b.

FIG. 4 shows a block diagram 400 of a memory device 405 supporting arbitrated sense amplifiers according to an example disclosed herein. Memory device 405 may be an example of an aspect of the memory device described with reference to fig. 1-3. The memory device 405 may include a cell coupling component 410, a voltage comparison component 415, a signal generator 420, a node coupling component 425, a node precharge component 430, a gate bias component 435, and a node voltage adjustment component 440. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

The cell coupling component 410 may couple the memory cell with a first node, where a voltage at the first node is based on a logic value that the memory cell is coupled with and stored by the first node.

The node coupling component 425 may couple the first node and the second node after the memory cell is coupled with the first node, where a voltage at the second node is based on the first node and the second node coupling and the voltage at the first node. In some examples, the node coupling component 425 may couple the second node and the third node based on a voltage at the second node and a voltage threshold after the first node and the second node are coupled.

The voltage comparison component 415 may compare the voltage at the third node to a reference voltage after the third node is coupled to the second node.

The signal generator 420 may generate a signal indicative of a logical value stored by the memory cell based on the comparison.

In some examples, the node coupling component 425 may couple the second node and the third node based on the voltage at the second node being below a voltage threshold. In some examples, the node coupling component 425 may decouple the third node from the second node prior to the comparison. In some cases, after the first node is coupled with the second node, the voltage at the second node is based at least in part on a first capacitance associated with the first node, a second capacitance associated with the second node, and a charge sharing between the first node and the second node. In some cases, after the second node is coupled with the third node, the voltage at the second node is based at least in part on a first capacitance associated with the second node, a second capacitance associated with the third node, and a charge sharing between the second node and the third node.

The node precharge component 430 may precharge the third node to a voltage associated with the first logic value prior to the first node being coupled with the second node. In some cases, the voltage at the third node changes to a second voltage associated with a second logical value based on the second node coupling with the third node.

The gate biasing component 435 may bias the gate of the transistor at a bias voltage, wherein the second node is coupled with the third node via the transistor based on a difference between the bias voltage and the second voltage satisfying a voltage threshold. In some examples, gate bias component 435 may adjust the voltage of the gate of the transistor to a bias voltage after the first node is coupled with the second node. In some examples, gate bias component 435 may adjust the bias voltage based on a temperature of a device including the memory cell. In some cases, the transistor is operable to isolate the third node from the second node if a difference between the bias voltage and the second voltage is below a voltage threshold. In some cases, the bias voltage is based on configurable parameters.

The node voltage adjustment component 440 can adjust the voltage of the second node prior to coupling the second node with the third node.

FIG. 5 shows a flow diagram illustrating one or more methods 500 that support arbitrating sense amplifiers in accordance with examples disclosed herein. The operations of method 500 may be implemented by a memory device described herein or components thereof. For example, the operations of method 500 may be performed by the memory device described with reference to FIG. 4. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 505, the memory device may couple the memory cell with a first node, where a voltage at the first node is based on a logic value the memory cell is coupled with and stored by the first node. Operation 505 may be performed according to the methods described herein. In some examples, aspects of operation 505 may be performed by the cell coupling component described with reference to fig. 4.

At 510, the memory device may couple the first node and the second node after the memory cell is coupled with the first node, wherein a voltage at the second node is based on the first node and the second node coupling and the voltage at the first node. Operation 510 may be performed according to the methods described herein. In some examples, aspects of operation 510 may be performed by the node coupling component described with reference to fig. 4.

At 515, the memory device may couple the second node and the third node based on the voltage at the second node and the voltage threshold after the first node and the second node are coupled. Operation 515 may be performed according to the methods described herein. In some examples, aspects of operation 515 may be performed by the node coupling component described with reference to fig. 4.

At 520, the memory device may compare the voltage at the third node to a reference voltage after the third node is coupled with the second node. Operation 520 may be performed according to the methods described herein. In some examples, aspects of operation 520 may be performed by the voltage comparison component described with reference to fig. 4.

At 525, the memory device may generate a signal indicative of a logical value stored by the memory cell based on the comparison. Operation 525 may be performed according to the methods described herein. In some examples, aspects of operation 525 may be performed by a signal generator as described with reference to fig. 4.

In some examples, an apparatus described herein may perform one or more methods, such as method 500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: coupling a memory cell with a first node, wherein a voltage at the first node is based on a logical value the memory cell is coupled with and stored by the first node; coupling the first node and a second node after the memory cell is coupled with the first node, wherein a voltage at the second node is based on the first node and the second node coupling and the voltage at the first node; after the first node is coupled with the second node, coupling the second node with a third node based at least in part on the voltage at the second node and a voltage threshold; comparing a voltage at the third node to a reference voltage after the third node is coupled with the second node; and based on the comparison, generating a signal indicative of the logical value stored by the memory cell.

In some examples of the method 500 and apparatus described herein, coupling a second node and a third node may include operations, features, means, or instructions for coupling the second node and the third node based on the voltage at the second node being below the voltage threshold.

Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for decoupling the third node from the second node prior to the comparing.

In some examples of the method 500 and apparatus described herein, the logical value stored by the memory cell may be a second logical value, and the method 500 and apparatus may further include an operation, feature, means, or instruction for precharging the third node to a voltage associated with the first logical value before the first node may be coupled with the second node.

In some examples of the method 500 and apparatus described herein, the voltage at the third node changes to a second voltage associated with the second logic value based on the second node being coupled with the third node.

Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for biasing a gate of a transistor at a bias voltage, wherein the second node may be coupled with the third node via the transistor based on a difference between the bias voltage and the voltage at the second node satisfying the voltage threshold.

In some examples of the method 500 and apparatus described herein, the transistor is operable to isolate the third node from the second node if the difference between the bias voltage and the voltage at the second node can be below the voltage threshold.

In some examples of the method 500 and apparatus described herein, biasing the gate of the transistor to the bias voltage may include operations, features, means, or instructions for adjusting a voltage of the gate of the transistor to the bias voltage after the first node may be coupled with the second node.

In some examples of the method 500 and apparatus described herein, the bias voltage may be based on a configurable parameter.

Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for adjusting the bias voltage based on a temperature of a device including the memory cell.

In some examples of the method 500 and apparatus described herein, after the first node may be coupled with the second node, the voltage at the second node may be based on a first capacitance associated with the first node, a second capacitance associated with the second node, and charge sharing between the first node and the second node.

In some examples of the method 500 and apparatus described herein, after the second node may be coupled with the third node, the voltage at the second node may be based on a second capacitance associated with the second node, a third capacitance associated with the third node, and a charge sharing between the second node and the third node.

Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for adjusting the voltage of the second node prior to coupling the second node and the third node.

FIG. 6 shows a flow diagram illustrating one or more methods 600 that support arbitrating sense amplifiers in accordance with examples disclosed herein. The operations of method 600 may be implemented by a memory device described herein or components thereof. For example, the operations of method 600 may be performed by the memory device described with reference to FIG. 4. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 605, the memory device may couple the memory cell with a first node, where a voltage at the first node is based on a logic value the memory cell is coupled with and stored by the first node. Operation 605 may be performed according to the methods described herein. In some examples, aspects of operation 605 may be performed by the unit coupling component described with reference to fig. 4.

At 610, the memory device may couple the first node and the second node after the memory cell is coupled with the first node, where a voltage at the second node is based on the first node and the second node coupling and the voltage at the first node. Operation 610 may be performed according to the methods described herein. In some examples, aspects of operation 610 may be performed by the node coupling component described with reference to fig. 4.

At 615, the memory device may couple the second node and the third node based on the voltage at the second node being below a voltage threshold after the first node and the second node are coupled. Operation 615 may be performed according to the methods described herein. In some examples, aspects of operation 615 may be performed by the node coupling component described with reference to fig. 4.

At 620, the memory device may decouple the third node from the second node. Operation 620 may be performed according to the methods described herein. In some examples, aspects of operation 620 may be performed by the node coupling component described with reference to fig. 4.

At 625, the memory device may compare the voltage at the third node to the reference voltage after the third node is coupled with the second node. Operation 625 may be performed according to the methods described herein. In some examples, aspects of operation 625 may be performed by the voltage comparison component described with reference to fig. 4.

At 630, the memory device may generate a signal indicative of a logical value stored by the memory cell based on the comparison. Operation 630 may be performed according to the methods described herein. In some examples, aspects of operation 630 may be performed by the signal generator described with reference to fig. 4.

FIG. 7 shows a flow diagram illustrating one or more methods 700 that support arbitrating sense amplifiers in accordance with examples disclosed herein. The operations of method 700 may be implemented by a memory device described herein or components thereof. For example, the operations of method 700 may be performed by the memory device described with reference to FIG. 4. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 705, the memory device may couple the memory cell with a first node, wherein a voltage at the first node is based on the logic value that the memory cell is coupled with the first node and stored by the memory cell, and wherein the logic value stored by the memory cell is the first logic value. Operation 705 may be performed in accordance with the methods described herein. In some examples, aspects of operation 705 may be performed by the cell coupling component described with reference to fig. 4.

At 710, the memory device may precharge the second node to a voltage associated with a second logic value. Operation 710 may be performed according to the methods described herein. In some examples, aspects of operation 710 may be performed by the node precharge component described with reference to fig. 4.

At 715, the memory device may couple the first node and the third node after the memory cell is coupled with the first node, wherein a voltage at the third node is based on the first node and the third node coupling and a voltage at the first node. Operation 715 may be performed according to the methods described herein. In some examples, aspects of operation 715 may be performed by the node coupling component described with reference to fig. 4.

At 720, the memory device may couple the third node to the second node based on the voltage at the third node and the voltage threshold after the first node is coupled with the third node, wherein the voltage at the second node changes to a second voltage associated with the first logic value based on the third node being coupled with the second node. Operation 720 may be performed according to the methods described herein. In some examples, aspects of operation 720 may be performed by the node coupling component described with reference to fig. 4.

At 725, the memory device may compare the voltage at the second node to the reference voltage after the third node is coupled with the second node. Operation 725 may be performed according to the methods described herein. In some examples, aspects of operation 725 may be performed by the voltage comparison component described with reference to fig. 4.

At 730, the memory device may generate a signal indicative of a logical value stored by the memory cell based on the comparison. Operation 730 may be performed according to the methods described herein. In some examples, aspects of operation 730 may be performed by the signal generator described with reference to fig. 4.

It should be noted that the methods described herein are possible implementations, and that the operations and steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

An apparatus is described. The apparatus may include: a memory cell operable to store a logical value as one of a set of at least two logical values; a first node operable to selectively couple with the memory cell, wherein a voltage of the first node when coupled with the memory cell is based on the logical value and is associated with a first voltage swing; a signal generating component operable to selectively couple a second node with the first node, wherein a voltage of the second node when coupled with the first node is based on the voltage of the first node and is associated with a second voltage swing that is greater than the first voltage swing; a coupling component operable to selectively couple a third node with the second node based on whether the voltage of the second node is below a voltage threshold; and a comparison component operable to generate a signal indicative of the logical value based on a comparison of a voltage at the third node to a reference voltage.

In some examples, the coupling component is operable to couple the third node and the second node when the voltage of the second node may be below the voltage threshold and to isolate the third node from the second node when the voltage of the second node may be greater than or equal to the voltage threshold.

In some examples, the coupling component includes a transistor having a gate operable to bias at a bias voltage that is greater than a lower limit of the second voltage swing by an amount greater than or equal to a threshold voltage of the transistor; and less than the sum of the upper limit of the second voltage swing and the threshold voltage of the transistor.

In some examples, the coupling component is operable to couple the third node and the second node when the voltage of the second node may be at a first limit of the second voltage swing and to isolate the third node from the second node when the voltage of the second node may be at a second limit of the second voltage swing.

Some examples of the apparatus may include a precharge component operable to adjust the voltage of the third node to a first voltage corresponding to a first logical value of the set, wherein the coupling component is operable to adjust the voltage of the third node toward a second voltage corresponding to a second logical value of the set when the third node is coupleable with the second node.

In some examples, the voltage of the third node may be associated with a third voltage swing that may be greater than the second voltage swing; and a difference between the third voltage swing and the second voltage swing may be based on a first capacitance associated with the second node and a second capacitance associated with the third node, the second capacitance being less than the first capacitance.

In some examples, a difference between the second voltage swing and the first voltage swing may be based on a first capacitance associated with the first node and a second capacitance associated with the second node, the second capacitance being less than the first capacitance.

Some examples of the apparatus may include a capacitor coupled with the second node and a control signal, and wherein the voltage of the second node is operable to be adjusted based on the control signal.

Some examples of the apparatus may include: a second capacitor coupled with the third node and a second control signal, and wherein the voltage of the third node is operable to be adjusted based on the second control signal; and a third capacitor coupled with a reference node and the second control signal, wherein the voltage of the third node is operable to be adjusted based on the second control signal.

In some examples, the memory cell includes a ferroelectric capacitor.

An apparatus is described. The apparatus may include: a first gain component coupled with a first node and a second node, wherein the first node is operable to be coupled with a memory cell, and wherein the first gain component is operable to adjust a voltage of the second node based on a voltage of the first node; a precharge component operable to set a voltage of the third node to a first voltage; and a second gain component coupled with the second node and the third node and operable to: adjusting the voltage of the third node to a second voltage when the voltage of the second node is below a voltage threshold; maintaining the voltage of the third node at the first voltage when the voltage of the second node is greater than or equal to the voltage threshold; and a comparison component operable to indicate a logical value associated with the memory cell based on a comparison of the voltage of the third node to a reference voltage, wherein the reference voltage is between the first voltage and the second voltage.

In some examples, the second gain component may include operations, features, means, or instructions for a transistor operable to selectively couple the second node and the third node based on a difference between the voltage of the second node and a voltage of a gate of the transistor.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, it should be understood by one of ordinary skill in the art that the signals may represent a signal bus, where the bus may have a variety of bit widths.

The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication with each other (either in conductive contact with each other or connected or coupled to each other) if there are any conductive paths between the components that can support signal flow between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other or connected or coupled to each other) may be open or closed circuits based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some examples, signal flow between connected components may be interrupted over a time, such as using one or more intermediate components (e.g., switches or transistors).

The term "coupled" refers to a state that moves from an open circuit relationship between components (where signals cannot presently be transmitted between components through conductive paths) to a closed circuit relationship between components (where signals can be transmitted between components through conductive paths). When a component, such as a controller, couples other components together, the component initiates a change that allows a signal to flow between the other components through a conductive path that previously did not allow the signal to flow.

The term "isolated" refers to a relationship between components in which signals cannot currently flow between components. The components are isolated from each other if there is an open circuit therebetween. For example, when a switch is open, two components separated by a switch positioned between the components are isolated from each other. When the controller isolates two components, the controller affects changes that prevent signals from flowing between the components using the conductive path that previously permitted the signal to flow.

As used herein, the term "substantially" means that a modified property (e.g., a verb or adjective substantially modified by the term) need not be absolute, but sufficiently close to achieve the benefit of the property.

As used herein, the term "electrode" may refer to an electrical conductor, and in some examples, may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, lines, conductive layers, or the like that provide a conductive path between elements or components of the memory array.

The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-sapphire (SOS) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. The doping may be performed during initial formation or growth of the substrate by ion implantation or by any other doping method.

The switch elements or transistors discussed herein may represent Field Effect Transistors (FETs), and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components through conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerated) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and is not intended to represent all examples that may be practiced or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other examples. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dashed line and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, that description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement a function may also be physically located at various locations, including being distributed such that portions of the function are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (e.g., a list of items prefaced by a phrase such as "at least one of …" or "one or more of …") indicates an inclusive list, such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a set of closed conditions. For example, an exemplary step described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the disclosure. In other words, the phrase "based on" as used herein should be interpreted in the same manner as the phrase "based at least in part on".

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising:

a memory cell operable to store a logical value as one of a set of at least two logical values;

a first node operable to selectively couple with the memory cell, wherein a voltage of the first node when coupled with the memory cell is based at least in part on the logical value and is associated with a first voltage swing;

a signal generating component operable to selectively couple a second node with the first node, wherein a voltage of the second node when coupled with the first node is based at least in part on the voltage of the first node and is associated with a second voltage swing that is greater than the first voltage swing;

a coupling component operable to selectively couple a third node with the second node based at least in part on whether the voltage of the second node is below a voltage threshold; and

a comparison component operable to generate a signal indicative of the logical value based at least in part on a comparison of a voltage at the third node to a reference voltage.

2. The apparatus of claim 1, wherein the coupling component is operable to couple the third node and the second node when the voltage of the second node is below the voltage threshold and to isolate the third node and the second node when the voltage of the second node is greater than or equal to the voltage threshold.

3. The apparatus of claim 1, wherein the coupling component comprises a transistor having a gate operable to bias at a bias voltage that:

greater than or equal to an amount of a threshold voltage of the transistor than a lower limit of the second voltage swing; and is

Less than a sum of the upper limit of the second voltage swing and the threshold voltage of the transistor.

4. The apparatus of claim 1, wherein the coupling component is operable to couple the third node and the second node when the voltage of the second node is at a first bound of the second voltage swing and to isolate the third node and the second node when the voltage of the second node is at a second bound of the second voltage swing.

5. The apparatus of claim 1, further comprising:

a precharge component operable to adjust the voltage of the third node to a first voltage corresponding to a first logical value of the group, wherein the coupling component is operable to adjust the voltage of the third node toward a second voltage when the third node is coupled with the second node, the second voltage corresponding to a second logical value of the group.

6. The apparatus of claim 1, wherein:

the voltage of the third node is associated with a third voltage swing that is greater than the second voltage swing; and is

A difference between the third voltage swing and the second voltage swing is based at least in part on a first capacitance associated with the second node and a second capacitance associated with the third node, the second capacitance being less than the first capacitance.

7. The apparatus of claim 1, wherein a difference between the second voltage swing and the first voltage swing is based at least in part on a first capacitance associated with the first node and a second capacitance associated with the second node, the second capacitance being less than the first capacitance.

8. The apparatus of claim 1, further comprising:

a capacitor coupled with the second node and a control signal, and wherein the voltage of the second node is operable to be adjusted based at least in part on the control signal.

9. The apparatus of claim 8, further comprising:

a second capacitor coupled with the third node and a second control signal, and wherein the voltage of the third node is operable to be adjusted based at least in part on the second control signal; and

a third capacitor coupled with a reference node and the second control signal, wherein the voltage of the third node is operable to be adjusted based at least in part on the second control signal.

10. The apparatus of claim 1, wherein the memory cell comprises a ferroelectric capacitor.

11. An apparatus, comprising:

a first gain component coupled with a first node and a second node, wherein the first node is operable to be coupled with a memory cell, and wherein the first gain component is operable to adjust a voltage of the second node based at least in part on a voltage of the first node,

a precharge component operable to set a voltage of the third node to a first voltage, an

A second gain component coupled with the second node and the third node and operable to:

adjusting the voltage of the third node to a second voltage when the voltage of the second node is below a voltage threshold; and

maintaining the voltage of the third node at the first voltage when the voltage of the second node is greater than or equal to the voltage threshold; and

a comparison component operable to indicate a logical value associated with the memory cell based at least in part on a comparison of the voltage of the third node to a reference voltage, wherein the reference voltage is between the first voltage and the second voltage.

12. The apparatus of claim 11, wherein the second gain component comprises:

a transistor operable to selectively couple the second node and the third node based at least in part on a difference between the voltage of the second node and a voltage of a gate of the transistor.

13. A method, comprising:

coupling a memory cell with a first node, wherein a voltage at the first node is based at least in part on a logic value the memory cell is coupled with and stored by the first node;

coupling the first node and a second node after the memory cell is coupled with the first node, wherein a voltage at the second node is based at least in part on the first node being coupled with the second node and the voltage at the first node;

after the first node is coupled with the second node, coupling the second node with a third node based at least in part on the voltage at the second node and a voltage threshold;

comparing a voltage at the third node to a reference voltage after the third node is coupled with the second node; and

generating a signal indicative of the logical value stored by the memory cell based at least in part on the comparison.

14. The method of claim 13, wherein coupling the second node with the third node comprises:

coupling the second node and the third node based at least in part on the voltage at the second node being below the voltage threshold.

15. The method of claim 14, further comprising:

decoupling the third node from the second node prior to the comparing.

16. The method of claim 13, wherein the logical value stored by the memory cell comprises a second logical value, further comprising:

precharging the third node to a first voltage associated with a first logic value before the first node is coupled with the second node.

17. The method of claim 16, wherein the voltage at the third node changes to a second voltage associated with the second logic value based at least in part on the second node coupling with the third node.

18. The method of claim 13, further comprising:

biasing a gate of a transistor at a bias voltage, wherein the second node is coupled with the third node via the transistor based at least in part on a difference between the bias voltage and the voltage at the second node satisfying the voltage threshold.

19. The method of claim 18, wherein the transistor is operable to isolate the third node from the second node if the difference between the bias voltage and the voltage at the second node is below the voltage threshold.

20. The method of claim 18, wherein biasing the gate of the transistor to the bias voltage comprises:

adjusting a voltage of the gate of the transistor to the bias voltage after the first node and the second node are coupled.

21. The method of claim 18, wherein the bias voltage is based at least in part on a configurable parameter.

22. The method of claim 18, further comprising:

adjusting the bias voltage based at least in part on a temperature of a device including the memory cell.

23. The method of claim 13, wherein the voltage at the second node after the first node and the second node are coupled is based at least in part on a first capacitance associated with the first node, a second capacitance associated with the second node, and a charge sharing between the first node and the second node.

24. The method of claim 13, wherein the voltage at the second node after the second node is coupled with the third node is based at least in part on a first capacitance associated with the second node, a second capacitance associated with the third node, and a charge sharing between the second node and the third node.

25. The method of claim 13, further comprising:

adjusting the voltage of the second node prior to coupling the second node and the third node.