CN113296594A - System and method for recording power failure time and times of electronic equipment - Google Patents
System and method for recording power failure time and times of electronic equipment Download PDFInfo
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- CN113296594A CN113296594A CN202110473089.3A CN202110473089A CN113296594A CN 113296594 A CN113296594 A CN 113296594A CN 202110473089 A CN202110473089 A CN 202110473089A CN 113296594 A CN113296594 A CN 113296594A
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- 238000000034 method Methods 0.000 title description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000004590 computer program Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B31/00—Arrangements for the associated working of recording or reproducing apparatus with related apparatus
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Abstract
The invention discloses a system for recording power-down time and times of electronic equipment, which is characterized in that a timing unit, a power control switch and a storage unit are added on the basis of an existing master control system, an auxiliary management system and a real-time clock RTC of the equipment to realize the recording of the power-down times and the corresponding time length of the equipment. The timing unit is used for recording the power-down time; the power control switch is used for controlling the power supply and the zero clearing timer of the timer. By utilizing the characteristics of quick start and small load of the auxiliary management unit, the power failure information is read and stored in the storage unit for the CPU to read in a relatively idle state, and the load of the CPU is not increased to influence the start of the system. The storage unit can adopt devices such as EEPROM or FLASH, etc., the information is not lost before the CPU reads the information, and all the power failure times and time information before the CPU reads the information can be recorded.
Description
Technical Field
The invention relates to the field of electronic equipment management, in particular to a system and a method for recording power failure time and times of electronic equipment.
Background
Due to the need for electronic device maintenance and monitoring, logging of power loss is being applied in more and more devices. The prior art is mainly realized by adopting a terminal-to-terminal legacy mode of equipment, namely, a power failure event is detected when the equipment is powered down, and the event is ensured to be recorded within a few milliseconds or dozens of milliseconds by means of electric energy stored on a single board. The method has the disadvantages that the method is difficult to realize on equipment with larger power consumption, and the enough time for the system to record logs is difficult to maintain after the power failure event occurs; and secondly, when the CPU system is in an abnormal state or in a starting process during power failure, the recording of the power failure event cannot be finished.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a system for recording the power-down time and times of electronic equipment.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a system for recording power failure time and times of electronic equipment comprises a main control system, an auxiliary management unit, a real-time clock unit, a storage unit, a timing unit and a control switch;
the main control system is connected to the storage unit through the auxiliary management unit and connected to the real-time clock unit;
the timing unit is connected to the real-time clock unit through a control switch, and the auxiliary control unit is connected to the control switch;
when the system is powered off, the auxiliary management unit sends a control signal to control the control switch to be conducted, and the timing unit starts timing and records the power-off time;
the storage unit is used for storing the power-down time and the power-down times of the system.
The scheme has the beneficial effects that on the basis that the equipment is provided with the main control system, the auxiliary management system and the real-time clock RTC, the recording of the power-down times and the corresponding time length of the equipment is realized by adding the timing unit, the power control switch and the storage unit. The timing unit is used for recording the power-down time; the power control switch is used for controlling the power supply and the zero clearing timer of the timer. By utilizing the characteristics of quick start and small load of the auxiliary management unit, the power failure information is read and stored in the storage unit for the CPU to read in a relatively idle state, and the load of the CPU is not increased to influence the start of the system. The storage unit can adopt devices such as EEPROM or FLASH, etc., the information is not lost before the CPU reads the information, and all the power failure times and time information before the CPU reads the information can be recorded.
Furthermore, the timing unit comprises an RTC real-time clock chip and a chip battery, and the timing unit is connected to the chip battery through a control switch.
The beneficial effect of the above further scheme is that the RTC real-time clock chip is used for providing accurate time for the system.
Further, when the master control system works normally, the auxiliary management unit turns off the timing unit through a control signal to be connected with the chip battery, and the time of the timing unit is set to zero.
The beneficial effect of the above further scheme is that when the system works normally, the timing unit is closed to reduce the workload of the main control system, and the timing unit is set to zero time to facilitate the timing after the system is powered off.
Further, the storage unit includes a data space and a flag space, the data space is used for storing the power-down time information of the master control system, and the flag space is used for storing the power-down times information of the master control system.
The power failure information is classified and stored in the storage unit for the main control system to read in a relatively idle state, and the load of the main control system is not increased to influence the starting of the system.
Further, when the system is powered on again, the auxiliary management unit reads the power-down time recorded by the timing unit through the bus, writes the power-down time into the data space of the storage unit through the bus, changes the address of the data space into a base address + N, and changes the address of the mark space in the storage unit into N +1, wherein N is the power-down times of the system from the last power-down to the successful start at the time.
The beneficial effect of the above further scheme is that the characteristic of fast start of the auxiliary management unit is utilized, when the system is abnormal in power failure, the recorded power failure time and power failure interval time point of the timing unit are read, and the data are written into the storage unit for reading and accessing after the system is normally started.
Furthermore, the auxiliary management unit controls the access of the main control system to the storage unit through a flag bit, when the flag bit is 1, the auxiliary management unit shuts off the access between the main control system and the storage unit, and when the flag bit is 0, the auxiliary management unit configures the auxiliary management unit, the main control system and the bus of the storage unit as gating to allow the access between the main control system and the storage unit.
The beneficial effect of the above further scheme is that the main control system and the auxiliary management unit are prevented from accessing the storage unit at the same time.
Further, the master control system calculates the duration of each power failure by reading the difference between the time interval point in the storage unit and the actual time of the real-time clock unit.
The main control system can calculate the current power-down time and the power-down times within the time only by accessing the storage data of the storage unit.
Further, after the main control system is successfully started, the power failure times from last power failure to current successful start and the corresponding power failure time data are written into a system log of the main control system, and the data in the mark space of the storage unit are cleared.
Preferably, the auxiliary management unit adopts any one of a single chip microcomputer, an FPGA or a CPLD.
Preferably, the storage unit adopts Flash or EEPROM.
The advantageous effect of the above preferred solution is that a flexible system assembly is provided.
Drawings
Fig. 1 is a schematic structural diagram of a system for recording power-down time and times of an electronic device according to the present invention.
FIG. 2 is a schematic flow chart of the system of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
A system for recording power-down time and times of electronic equipment is shown in figure 1 and comprises a main control system, an auxiliary management unit, a real-time clock unit, a storage unit, a timing unit and a control switch;
the main control system is connected to the storage unit through the auxiliary management unit and connected to the real-time clock unit;
the timing unit is connected to the real-time clock unit through a control switch, and the auxiliary control unit is connected to the control switch;
when the system is powered off, the auxiliary management unit sends a control signal to control the control switch to be conducted, and the timing unit starts timing and records the power-off time;
the storage unit is used for storing the power-down time and the power-down times of the system.
In this embodiment, the main control system is configured as a CPU, the auxiliary management unit is configured as an FPGA, and the storage unit is configured as an EEPROM.
When the timing unit normally works, the FPGA turns off the power supply of the timing unit through the control signal e, the timing unit does not work at the moment, meanwhile, the FPGA sets the identification position of the FPGA to be 1, and when the CPU reads that the identification position is 1, the FPGA cannot access the storage unit through the bus a, so that the FPGA and the CPU are prevented from simultaneously accessing the storage unit, and the access conflict of the bus a is avoided.
When the CPU system is powered off, the auxiliary management unit is powered off, the control signal e of the auxiliary management unit is released to be in a default state in an uncontrolled manner, the control switch is turned on, and at the moment, the timing unit starts timing.
When the device is started next time, the FPGA is started faster and has smaller load, so that the FPGA reads the time T in the timing unit through the bus b and writes the time T into the data space of the storage unit through the bus a, the written data space address is the base address + N, wherein N is the power failure frequency recorded in the storage unit mark space.
At the moment, the FPGA changes the data N of the mark space of the FPGA into N +1, namely, the power failure is increased once, when the power failure occurs for a plurality of times due to the failure of starting in the starting process, the data are sequentially superposed upwards, and the process of changing the address is executed again once each time the power failure occurs.
After the FPGA records the power-down time and the power-down frequency data, the zone bit of the FPGA is changed to 0, at the moment, the bus a and the bus c are configured to be in a gating state, and the CPU can access the storage unit under the condition. After the CPU is started successfully, the FPGA sends out a control signal e again to close the control switch, the timing unit is powered off, and the time of the timing unit is cleared.
After the CPU system is successfully started, when a flag bit of the FPGA is read to be 0, reading data in N in a flag space and a space base address + N of an address section in a data space in a storage unit through a bus a and a bus c, wherein N is the power failure times of the system from last power failure to the successful start, the data of the base address + N in the corresponding data space is the corresponding power failure time interval, if N is read to be 2, the power failure occurs twice, and the data corresponding to the address space of the base address +0 and the base address +1 is the power failure time of 2 times.
And the CPU system performs difference calculation through the read time and the real-time clock unit, so that the duration of each power failure can be obtained. The CPU writes the calculated data into a system log, and sets N in a mark space to zero through a bus c and a, so that all power failure times and time before the CPU reads power failure information and writes N into 0 can be recorded, namely all the power failure times and corresponding power failure time of the CPU system from one normal operation to the next normal operation time are recorded. The work flow is shown in fig. 2.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (10)
1. A system for recording power-down time and times of electronic equipment is characterized by comprising a main control system, an auxiliary management unit, a real-time clock unit, a storage unit, a timing unit and a control switch;
the main control system is connected to the storage unit through the auxiliary management unit and connected to the real-time clock unit;
the timing unit is connected to the real-time clock unit through a control switch, and the auxiliary control unit is connected to the control switch;
when the system is powered off, the auxiliary management unit sends a control signal to control the control switch to be conducted, and the timing unit starts timing and records the power-off time;
the storage unit is used for storing the power-down time and the power-down times of the system.
2. The system for recording power-down time and times of electronic equipment according to claim 1, wherein the timing unit comprises an RTC real-time clock chip and a chip battery, and the timing unit is connected to the chip battery through a control switch.
3. The system for recording power-down time and times of electronic equipment according to claim 2, wherein when the main control system works normally, the auxiliary management unit turns off a timing unit through a control signal to be connected with the chip battery, and sets the timing unit to zero.
4. The system according to claim 3, wherein the storage unit comprises a data space and a flag space, the data space is used for storing power-down time information of the master control system, and the flag space is used for storing power-down time information of the master control system.
5. The system according to claim 4, wherein when the system is powered on, the auxiliary management unit reads the power-down time recorded by the timing unit through the bus, writes the power-down time into the data space of the storage unit through the bus, changes the address of the data space to a base address + N, and changes the address of the flag space in the storage unit to N +1, where N is the number of times the system has been powered down from the last power-down to the current power-up.
6. The system according to claim 5, wherein the auxiliary management unit controls access to the storage unit from the main control system through a flag bit, when the flag bit is 1, the auxiliary management unit shuts off access between the main control system and the storage unit, and when the flag bit is 0, the auxiliary management unit configures buses of the auxiliary management unit, the main control system and the storage unit as gating to allow access between the main control system and the storage unit.
7. The system for recording power-down time and times of electronic equipment according to claim 6, wherein the master control system calculates the duration of each power-down by reading the difference between the time interval point in the storage unit and the actual time of the real-time clock unit.
8. The system for recording power-down time and times of electronic equipment according to any one of claims 1 to 7, wherein after the main control system is successfully started, the power-down times from last power-down to current successful start and the corresponding power-down time data are written into a system log of the main control system, and the data in the flag space of the storage unit are cleared.
9. The system for recording the power-down time and times of the electronic equipment according to any one of claims 1 to 7, wherein the auxiliary management unit adopts any one of a single chip microcomputer, an FPGA or a CPLD.
10. The system for recording the power-down time and times of the electronic equipment according to any one of claims 1-7, wherein the storage unit adopts Flash or EEPROM.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110473089.3A CN113296594A (en) | 2021-04-29 | 2021-04-29 | System and method for recording power failure time and times of electronic equipment |
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| CN202110473089.3A CN113296594A (en) | 2021-04-29 | 2021-04-29 | System and method for recording power failure time and times of electronic equipment |
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| CN113296594A true CN113296594A (en) | 2021-08-24 |
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| CN202110473089.3A Pending CN113296594A (en) | 2021-04-29 | 2021-04-29 | System and method for recording power failure time and times of electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113687710A (en) * | 2021-10-26 | 2021-11-23 | 西安羚控电子科技有限公司 | Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle |
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| CN112269725A (en) * | 2020-10-16 | 2021-01-26 | 苏州浪潮智能科技有限公司 | Recording device and method for storing power-on and power-off time of controller |
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2021
- 2021-04-29 CN CN202110473089.3A patent/CN113296594A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101419727A (en) * | 2008-11-26 | 2009-04-29 | 朱鸽 | Timer and counter |
| CN102081573A (en) * | 2010-02-01 | 2011-06-01 | 杭州华三通信技术有限公司 | Device and method for recording equipment restart reason |
| CN103559053A (en) * | 2013-10-30 | 2014-02-05 | 迈普通信技术股份有限公司 | Board system and FPGA (Field Programmable Logic Array) online update method of communication interface cards |
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| CN113687710A (en) * | 2021-10-26 | 2021-11-23 | 西安羚控电子科技有限公司 | Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle |
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Application publication date: 20210824 |