CN113285699A - Novel grid driving circuit - Google Patents
Novel grid driving circuit Download PDFInfo
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- CN113285699A CN113285699A CN202110635123.2A CN202110635123A CN113285699A CN 113285699 A CN113285699 A CN 113285699A CN 202110635123 A CN202110635123 A CN 202110635123A CN 113285699 A CN113285699 A CN 113285699A
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- 238000010586 diagram Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention discloses a novel grid driving circuit, which belongs to the field of integrated circuits and comprises a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate, an AND gate and a control logic circuit; the first input end of the AND gate is connected with the output end of the NOT gate, the second input end of the AND gate is connected with the output end of the comparator I0, and the output end of the AND gate is connected with the grid of the NMOS tube M3; the first input end of the NAND gate is connected with the input end of the NOT gate, the second input end of the NAND gate is connected with the output end of the comparator I0, and the output end of the NAND gate is connected with the grid electrode of the PMOS tube M2; the source of the PMOS transistor M2 is connected to the positive input terminal of the comparator I0, and the drain is connected to the gate of the NMOS transistor M5. The invention can selectively adjust the driving capability and reduce the conduction loss.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a novel gate driving circuit.
Background
In various applications based on switching operations, efficiency is closely related to the losses of the switching devices. The power loss of the switching element is mainly composed of two parts, namely "switching loss" and "conduction loss". "switching losses" are related to switching speed, i.e., refer to losses that occur when the switching element "goes from an on-state to an off-state" or "goes from an off-state to an on-state"; the "conduction loss" refers to a loss caused by "impedance of the switch in the energized state" and "current flowing through the switch".
In the half-bridge switch-driven inductive load circuit shown in fig. 1, the power loss at the time of switching between the on state and the off state is as shown in fig. 2(a) and 2(b), and generally, the switching loss is reduced by increasing the switching speed. I.e., by reducing Tr and Tf to reduce power loss. However, the switching operation changes the current flow path, which often causes high frequency resonance (ringing) due to the presence of parasitic parameters in the wiring. Decreasing Tr and Tf by increasing the driving capability can increase the rate of change of current (di/dt), thereby increasing the amplitude of ringing. This not only "increases the stress of the switching element", but also "causes electromagnetic wave emission, which affects the operation of peripheral circuits, and high frequency emission causes energy loss".
Therefore, it is necessary to reduce the influence of parasitic parameters by optimizing the current flow path. However, there is a limit to reducing the parasitic parameters, and thus there is a limit to improving the driving capability. This limited drive capability also affects conduction losses. This is because the time required for the switch to be fully on or off also depends on the driving capability. Generally, a switch has a threshold voltage that goes from an off state to an on state. That is, when the magnitude of the voltage (control voltage) at the relevant node of the control switch is larger than the threshold voltage, a current may flow in the switch, and as the magnitude of the voltage increases, the on-resistance of the switch decreases. Therefore, until the switch control voltage is sufficiently high, the value of the on-resistance of the switch is higher than the expected value, so that the on-loss is also high.
Disclosure of Invention
The present invention is directed to a novel gate driving circuit to solve the problems of the related art.
In order to solve the above technical problems, the present invention provides a novel gate driving circuit, which includes a comparator I0, a PMOS transistor M0, a PMOS transistor M2, an NMOS transistor M1, an NMOS transistor M3, an NMOS transistor M5, a nor gate, an and gate, and a control logic circuit;
the first input end of the AND gate is connected with the output end of the NOT gate, the second input end of the AND gate is connected with the output end of the comparator I0, and the output end of the AND gate is connected with the grid of the NMOS tube M3;
the first input end of the NAND gate is connected with the input end of the NOT gate, the second input end of the NAND gate is connected with the output end of the comparator I0, and the output end of the NAND gate is connected with the grid electrode of the PMOS tube M2;
the source electrode of the PMOS tube M2 is connected with the positive input end of the comparator I0, and the drain electrode is connected with the grid electrode of the NMOS tube M5;
the drain electrode of the NMOS tube M3 is connected with the grid electrode of the NMOS tube M5, and the SOURCE electrode is connected with a SOURCE electrode SOURCE;
the drain of the NMOS transistor M5 is connected to the negative input terminal of the comparator I0, and the SOURCE is connected to the SOURCE terminal SOURCE.
Optionally, the gates of the PMOS transistor M0 and the NMOS transistor M1 are both connected to a control logic circuit.
Optionally, the source of the PMOS transistor M0 is connected to the positive input terminal of the comparator I0.
Optionally, the drain of the PMOS transistor M0 is connected to the gate of the NMOS transistor M5, and the drain of the NMOS transistor M1 is connected to the gate of the NMOS transistor M5.
Optionally, the comparator I0 includes an NMOS transistor M6, a resistor R0, and a flip-flop I1;
the source end of the NMOS tube M6 is connected with a resistor R0, the drain end of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M2, and the grid electrode of the NMOS tube M6 is connected with the source electrode of the PMOS tube M2;
the input end of the flip-flop I1 is connected with the source electrode of the NMOS tube M6, and the output end of the flip-flop I1 is used as the output end of the comparator I0.
The novel gate drive circuit provided by the invention comprises a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate, an AND gate and a control logic circuit; the first input end of the AND gate is connected with the output end of the NOT gate, the second input end of the AND gate is connected with the output end of the comparator I0, and the output end of the AND gate is connected with the grid of the NMOS tube M3; the first input end of the NAND gate is connected with the input end of the NOT gate, the second input end of the NAND gate is connected with the output end of the comparator I0, and the output end of the NAND gate is connected with the grid electrode of the PMOS tube M2; the source of the PMOS transistor M2 is connected to the positive input terminal of the comparator I0, and the drain is connected to the gate of the NMOS transistor M5. The invention can selectively adjust the driving capability and reduce the conduction loss.
Drawings
FIG. 1 is a schematic diagram of a half-bridge switch driven inductive load circuit;
FIGS. 2(a) and 2(b) are schematic diagrams of power loss when the switch is switched on/off;
FIG. 3 is a schematic diagram of a novel gate driving circuit according to the present invention;
FIG. 4 is a schematic diagram of a novel gate driving circuit according to the present invention;
fig. 5(a) and 5(b) are schematic diagrams of reducing conduction loss without changing Tr/Tf.
Detailed Description
The novel gate driving circuit provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a novel gate drive circuit, the structure of which is shown in fig. 3, and the novel gate drive circuit comprises a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate, an AND gate and a control logic circuit; the first input end of the AND gate is connected with the output end of the NOT gate, the second input end of the AND gate is connected with the output end of the comparator I0, and the output end of the AND gate is connected with the grid of the NMOS tube M3; the first input end of the NAND gate is connected with the input end of the NOT gate, the second input end of the NAND gate is connected with the output end of the comparator I0, and the output end of the NAND gate is connected with the grid electrode of the PMOS tube M2; the source electrode of the PMOS tube M2 is connected with the positive input end of the comparator I0, and the drain electrode is connected with the grid electrode of the NMOS tube M5; the drain electrode of the NMOS tube M3 is connected with the grid electrode of the NMOS tube M5, and the SOURCE electrode is connected with a SOURCE electrode SOURCE; the drain electrode of the NMOS tube M5 is connected with the negative input end of the comparator I0, and the SOURCE end is connected with the SOURCE end SOURCE; the grid electrode of the PMOS tube M0 and the grid electrode of the NMOS tube M1 are both connected with a control logic circuit; the source electrode of the PMOS tube M0 is connected with the positive input end of a comparator I0; the drain of the PMOS transistor M0 is connected to the gate of the NMOS transistor M5, and the drain of the NMOS transistor M1 is connected to the gate of the NMOS transistor M5.
Further, as shown in fig. 4, the comparator I0 includes an NMOS transistor M6, a resistor R0, and a flip-flop I1; the source end of the NMOS tube M6 is connected with a resistor R0, the drain end of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M2, and the grid electrode of the NMOS tube M6 is connected with the source electrode of the PMOS tube M2; the input end of the flip-flop I1 is connected with the source electrode of the NMOS tube M6, and the output end of the flip-flop I1 is used as the output end of the comparator I0.
The source voltage of the NMOS transistor M6 follows the drain voltage of the NMOS transistor M5 and is clamped (within the allowed input voltage range of the flip-flop I1). That is, the voltage at the drain of the NMOS transistor M5 is induced to the source of the NMOS transistor M6 through the NMOS transistor M6. The voltage at the source of the NMOS transistor M6 is compared with the trigger voltage of the trigger I1, (the trigger voltage is between the "M5 source voltage" and "V _ DRV"). Although the trigger voltage of flip-flop I1 is different from the "voltage of V _ DRV", this is not important, since the trigger voltage is related to the "voltage of V _ DRV", the switch transition is usually very fast and the response time of flip-flop I1 is rather short, so the Vcomp voltage reflects the result of the comparison of the "voltage of V _ DRV" and the "voltage of M5 drain" by comparator I0 in fig. 3. The novel gate driving circuit according to fig. 3 selectively adjusts the driving capability, which can reduce conduction loss, as shown in fig. 5(a) and 5 (b).
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (5)
1. A novel gate drive circuit is characterized by comprising a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate, an AND gate and a control logic circuit;
the first input end of the AND gate is connected with the output end of the NOT gate, the second input end of the AND gate is connected with the output end of the comparator I0, and the output end of the AND gate is connected with the grid of the NMOS tube M3;
the first input end of the NAND gate is connected with the input end of the NOT gate, the second input end of the NAND gate is connected with the output end of the comparator I0, and the output end of the NAND gate is connected with the grid electrode of the PMOS tube M2;
the source electrode of the PMOS tube M2 is connected with the positive input end of the comparator I0, and the drain electrode is connected with the grid electrode of the NMOS tube M5;
the drain electrode of the NMOS tube M3 is connected with the grid electrode of the NMOS tube M5, and the SOURCE electrode is connected with a SOURCE electrode SOURCE;
the drain of the NMOS transistor M5 is connected to the negative input terminal of the comparator I0, and the SOURCE is connected to the SOURCE terminal SOURCE.
2. The novel gate drive circuit as claimed in claim 1, wherein the gate of the PMOS transistor M0 and the gate of the NMOS transistor M1 are both connected to a control logic circuit.
3. The novel gate drive circuit as claimed in claim 2, wherein the source of the PMOS transistor M0 is connected to the positive input of a comparator I0.
4. The novel gate drive circuit as claimed in claim 3, wherein the drain of the PMOS transistor M0 is connected to the gate of the NMOS transistor M5, and the drain of the NMOS transistor M1 is connected to the gate of the NMOS transistor M5.
5. The novel gate drive circuit as claimed in claim 4, wherein the comparator I0 comprises an NMOS transistor M6, a resistor R0 and a flip-flop I1;
the source end of the NMOS tube M6 is connected with a resistor R0, the drain end of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M2, and the grid electrode of the NMOS tube M6 is connected with the source electrode of the PMOS tube M2;
the input end of the flip-flop I1 is connected with the source electrode of the NMOS tube M6, and the output end of the flip-flop I1 is used as the output end of the comparator I0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110635123.2A CN113285699A (en) | 2021-06-08 | 2021-06-08 | Novel grid driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110635123.2A CN113285699A (en) | 2021-06-08 | 2021-06-08 | Novel grid driving circuit |
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| CN113285699A true CN113285699A (en) | 2021-08-20 |
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| CN202110635123.2A Pending CN113285699A (en) | 2021-06-08 | 2021-06-08 | Novel grid driving circuit |
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-
2021
- 2021-06-08 CN CN202110635123.2A patent/CN113285699A/en active Pending
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