CN113255904A - Voltage margin enhanced capacitive coupling storage integrated unit, subarray and device - Google Patents

Abstract

The invention relates to a voltage margin enhanced capacitive coupling storage and calculation integrated unit, a subarray and a device, wherein the unit comprises a 6T storage unit and a calculation unit; the calculation unit includes: a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, and a coupling capacitance C. The voltage margin enhancement type capacitive coupling and storage integrated unit disclosed by the invention charges the coupling capacitor, saves 50% of charging time compared with a single-ended charging mode, and accelerates the calculation process; if the charging time is the same, the voltage value at the two ends of the coupling capacitor is 2 times of that of the single-end charging mode, so that the voltage quantization range on the read bit line in the ADC quantization process is theoretically improved by 2 times. In the same discharging process, two discharging channels are provided, the discharging speed is theoretically twice of that of single-end discharging, and the calculating process is further accelerated.

Description

Voltage margin enhanced capacitive coupling storage integrated unit, subarray and device

Technical Field

The invention relates to the technical field of memory computing, in particular to a voltage margin enhanced capacitive coupling memory integrated unit, a voltage margin enhanced capacitive coupling memory integrated sub-array and a voltage margin enhanced capacitive coupling memory integrated device.

Background

The unprecedented growth in the size of Deep Neural Networks (DNNs) has resulted in a large amount of data being moved from off-chip memory to on-chip processing cores in modern Machine Learning (ML) accelerators. Computing in memory arrays (CIM) designs, as well as peripheral mixed signal circuits, are currently being explored by the industry to alleviate such memory wall bottlenecks, including memory latency and energy overhead. The static random access memory bitcell is monolithically integrated with high performance logic transistors and interconnects, allowing for custom CIM designs.

The traditional calculation mode of multiplying single-bit input by single-bit weight has low efficiency and no relative advantage in calculation throughput; although the transistor number can be saved by using the DRAM 1T1C structure for weight storage, the characteristic that the DRAM needs to be refreshed due to leakage needs to consume large power consumption; in the process of charging and discharging by using the coupling capacitor, the charging and discharging time of a single end is long, which is not beneficial to quick calculation; in addition, the multiplication and accumulation calculation voltage accumulated on the reading bit line has a small quantization range, is not beneficial to ADC quantization, and has larger memory calculation power consumption.

Disclosure of Invention

The invention aims to provide a voltage margin enhanced capacitive coupling storage integral unit, a subarray and a device, so as to optimize a calculation process and save ADC quantization time.

To achieve the above object, the present invention provides a voltage margin enhanced capacitive coupling storage integrated unit, comprising:

the 6T-SRAM storage unit is used for reading, writing and storing the weight value;

the computing unit is connected with the 6T-SRAM storage unit and is used for multiplying input data by a weight value;

the word line end of the 6T-SRAM storage unit is connected with a word line, the bit line end of the 6T-SRAM storage unit is connected with a bit line, and the bit bar end of the 6T-SRAM storage unit is connected with a bit bar line;

the input line end of the computing unit is connected with an input line, and the column line selection end of the computing unit is connected with a column line selection; the reading bit line end of the computing unit is connected with a reading bit line; the input line is used for transmitting input data;

the calculation unit includes: a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, and a coupling capacitance C;

the drain of the transistor T7, the source of the transistor T10, and the other end of the coupling capacitor C are all connected to a common terminal VSS, the gate of the transistor T7 and the gate of the transistor T8 are all connected to a point Q on the 6T-SRAM memory cell, the source of the transistor T7, the source of the transistor T8, the drain of the transistor T9, and the drain of the transistor T10 are all connected to the source of the transistor T11, the gate of the transistor T9 and the gate of the transistor T10 are all connected to a point QB on the 6T-SRAM memory cell, the gate of the transistor T11 and the gate of the transistor T12 are all connected to a column select line, and the drain of the transistor T11 and the drain of the transistor T12 are all connected to one end of the coupling capacitor C.

Optionally, the 6T-SRAM memory cell comprises:

a transistor T1, a transistor T2, a transistor T3, a transistor T14, a transistor T5, and a transistor T6;

a source of the transistor T1 and a source of the transistor T2 are connected to a power supply VDD, a gate of the transistor T1, a gate of the transistor T3, a drain of the transistor T2, and a drain of the transistor T4 are connected to a point Q, a gate of the transistor T2, a gate of the transistor T4, a drain of the transistor T1, and a drain of the transistor T3 are connected to a point QB, a source of the transistor T3 and a source of the transistor T4 are connected to a common terminal VSS, a gate of the transistor T5 and a gate of the transistor T6 are connected to a word line, a drain of the transistor T5 is connected to a point QB, a source of the transistor T5 is connected to a bit line, a source of the transistor T6 is connected to a point Q, and a drain of the transistor T6 is connected to an inverted bit line.

Alternatively, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T8, the transistor T10, and the transistor T11 are all NMOS, and the transistor T1, the transistor T2, the transistor T7, the transistor T9, and the transistor T12 are all PMOS.

Optionally, when Q =0V, QB = VDD, the weight value is 0; when Q = VDD, QB =0V, the weight value at this time is + 1; wherein VDD = 1V;

when the weight value is +1 and the input data is 1, charging the coupling capacitor C; when the weight value is +1 and the input data is 0, discharging the coupling capacitor C; when the weight value is 0 and the input data is 1 or 0, the coupling capacitor C discharges; when the column selection signal input by the column selection line is 0V, the coupling capacitor C is precharged to 0.5V through the read bit line; when the column selection signal input by the column selection line is VDD and the weight value is 0, the coupling capacitor C discharges.

The invention also provides a voltage margin enhanced capacitive coupling storage integral sub-array, comprising:

k of the above units; k is a positive integer greater than or equal to 2;

each cell is connected with a word line, a bit line, an inversion line, an input line and a column selection line, a read bit line is connected with a source of a transistor T12 in a first existing calculation cell, a source of a transistor T12 in the first existing calculation cell is connected, and a drain of a transistor T12 in a kth existing calculation cell is connected with a source of a transistor T12 in a kth +1 existing calculation cell, wherein K is a positive integer greater than or equal to 1 and less than K.

The invention also provides a voltage margin enhanced capacitive coupling storage and calculation integrated device, which comprises:

the device comprises a first input module, a second input module, a third input module and a computing unit array; the first input module is a word line decoding and driving module; the second input module is a row decoding module, a bit line driving module and a prestoring module; the third input module is an input decoding and driving module; the computing unit array comprises the subarrays arranged by M × N arrays, wherein M is a positive integer larger than 1, and N is a positive integer larger than 1;

the M word line ends of the first input module are respectively connected with the M word lines;

the N column line selection ends of the second input module are respectively connected with the N column line selection ends, the bit line end of the second input module is connected with the bit line, and the bit bar end of the second input module is connected with the bit bar; the N reading bit line ends of the second input module are respectively connected with the N reading bit lines;

the M input line ends of the third input module are respectively connected with M input lines;

bit line ends of the M multiplied by N sub-arrays are all connected with bit lines, bit bar ends of the M multiplied by N sub-arrays are all connected with bit bars, column selection ends of the M sub-arrays in the j +1 th column are all connected with the jth column selection line, bit reading end ends of the M sub-arrays in the j +1 th column are all connected with the jth bit reading line, calculation word line ends of the N sub-arrays in the i +1 th row are all connected with the ith word line, input line ends of the N sub-arrays in the i +1 th row are all connected with the ith input line, wherein i is a positive integer larger than or equal to 0 and smaller than M, and j is a positive integer larger than or equal to 0 and smaller than N.

Optionally, the apparatus further comprises:

n analog-to-digital converters; one end of the (j + 1) th analog-digital converter inputs a reference voltage, the other end of the (j + 1) th analog-digital converter is connected with the jth reading bit line, and the output end of the (j + 1) th analog-digital converter outputs an accumulation result; and the accumulation result is obtained by accumulating the data output by the M sub-arrays in the j +1 th column to the j-th reading bit line.

Optionally, the computing unit array comprises: 256 × 32 sub-arrays.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

when the voltage margin enhancement type capacitive coupling and calculation integrated unit disclosed by the invention realizes multiplication with the weight value of 1 and the input data of 1,1 multiplied by 1=1, two channels charge the coupling capacitor, and compared with a common calculation circuit only with single-ended charging, if the coupling capacitor is charged to a rated voltage value, only 50% of charging time of a single-ended charging mode is needed, so that the calculation process is accelerated to a great extent; if the charging time is the same, the voltage value at the two ends of the coupling capacitor is 2 times of that of the single-end charging mode, so that the voltage quantization range on the read bit line in the ADC quantization process is theoretically improved by 2 times. Similarly, in the discharging process, when 0 × 1=0,0 × 0=0, and 1 × 0=0 is calculated, that is, when discharging, there are two discharging channels, and the discharging speed is theoretically twice of that of single-ended discharging, so that the calculating process is accelerated, and the power consumption for implementing the internal calculation is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a block diagram of an enhanced voltage margin capacitively coupled storage integral unit according to the present invention;

FIG. 2 is a schematic diagram of a read bit line precharge scheme according to the present invention;

FIG. 3 is a schematic diagram illustrating the charging principle of the coupling capacitor according to the present invention;

FIG. 4 is a first schematic diagram of the capacitor-coupled capacitor discharge principle of the present invention;

FIG. 5 is a second schematic diagram of the capacitor-coupled capacitor discharge principle of the present invention;

FIG. 6 is a diagram of a voltage margin enhanced capacitively coupled storage integral sub-array structure in accordance with the present invention;

FIG. 7 is a schematic diagram of the pressure equalization of the present invention;

FIG. 8 is a diagram of a voltage margin enhanced capacitively coupled storage integrated device according to the present invention.

Description of the symbols:

word line decoding and driving module, column decoding, bit line driving and pre-charging module, subarray, input decoding and driving module, and A/D converter.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a voltage margin enhanced capacitive coupling storage integral unit, a subarray and a device, so as to optimize a calculation process and save ADC quantization time.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Example 1

As shown in fig. 1, the present invention discloses a voltage margin enhanced capacitive coupling storage integrated unit, comprising: a 6T-SRAM storage unit and a calculation unit; the computing unit is connected with the 6T-SRAM storage unit; the word line end of the 6T-SRAM storage unit is connected with a word line, the bit line end of the 6T-SRAM storage unit is connected with a bit line, and the bit bar end of the 6T-SRAM storage unit is connected with a bit bar line; the input line end of the computing unit is connected with an input line, and the column line selection end of the computing unit is connected with a column line selection; the reading bit line end of the computing unit is connected with a reading bit line; the input line is used for transmitting input data; the 6T-SRAM storage unit is used for reading, writing and storing weight values; the calculation unit is used for multiplying the input data and the weight value.

The calculation unit includes: a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, and a coupling capacitance C; the drain of the transistor T7, the source of the transistor T10, and the other end of the coupling capacitor C are all connected to a common terminal VSS, the gate of the transistor T7 and the gate of the transistor T8 are all connected to a point Q on the 6T-SRAM memory cell, the source of the transistor T7, the source of the transistor T8, the drain of the transistor T9, and the drain of the transistor T10 are all connected to the source of the transistor T11, the gate of the transistor T9 and the gate of the transistor T10 are all connected to a point QB on the 6T-SRAM memory cell, the gate of the transistor T11 and the gate of the transistor T12 are all connected to a column select line, and the drain of the transistor T11 and the drain of the transistor T12 are all connected to one end of the coupling capacitor C.

As an optional implementation mode, the 6T-SRAM memory cell comprises: a transistor T1, a transistor T2, a transistor T3, a transistor T14, a transistor T5, and a transistor T6; a source of the transistor T1 and a source of the transistor T2 are connected to a power supply VDD, a gate of the transistor T1, a gate of the transistor T3, a drain of the transistor T2, and a drain of the transistor T4 are connected to a point Q, a gate of the transistor T2, a gate of the transistor T4, a drain of the transistor T1, and a drain of the transistor T3 are connected to a point QB, a source of the transistor T3 and a source of the transistor T4 are connected to a common terminal VSS, a gate of the transistor T5 and a gate of the transistor T6 are connected to a word line, a drain of the transistor T5 is connected to a point QB, a source of the transistor T5 is connected to a bit line, a source of the transistor T6 is connected to a point Q, and a drain of the transistor T6 is connected to an inverted bit line. In this embodiment, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T8, the transistor T10, and the transistor T11 are all NMOS, and the transistor T1, the transistor T2, the transistor T7, the transistor T9, and the transistor T12 are all PMOS.

In fig. 1, transistor T1-transistor T6 constitute a classic 6T-SRAM memory cell for storing weight values. Wherein, the differential weight values are respectively stored in the Q point and the QB point. The word line is connected to the gate of the transistor T5 and the gate of the transistor T6, the on/off of the transistor T5 and the transistor T6 is controlled, the bit line and the bit bar line are respectively connected to the source and drain of the transistor T5 and the source and drain of the transistor T6, the bit line of the current column is precharged to a high level (i.e., VDD) by the column decoding, bit line driving and precharging module in fig. 8, the bit line is inverted to a low level (i.e., 0V), after the word line of the current row is set to a high level by the word line decoding and driving module, the transistor T5 and the transistor T6 are turned on, the bit line is turned on with the QB point, the QB point is charged to a high level, and after passing through the inverter formed by the transistor T2 and the transistor T4, the Q point value becomes a low level, and the discharging speed of the Q point is accelerated because the bit bar line is a low level. This process completes the weight writing of the Q point high level and the QB point low level.

The transistor T7, the transistor T8, the transistor T9 and the transistor T10 form a data selector MUX, a Q point is connected with a grid electrode of the transistor T7 and a grid electrode of the transistor T8, which transistor is conducted is determined by the Q point value, a drain electrode of the transistor T7 is connected with a common terminal VSS, a drain electrode of the transistor T8 is connected with an input line, a source electrode of the transistor T9 is connected with the input line, and a source electrode of the transistor T10 is connected with the common terminal VSS; the column select signal is connected to the gate of the transistor T11 and the gate of the transistor T12, respectively, i.e., when the column select signal is at a high level, the transistor T11 is turned on, the transistor T12 is turned off, and when the column select signal is at a low level, the transistor T12 is turned on, and the transistor T11 is turned off.

The calculation principle is detailed in table 1:

TABLE 1 calculation principle operation table

As shown in table 1, Q =1V, QB =0V indicates that the weight is +1, Q =0V, QB =1V indicates that the weight is 0, input data is at a high level indicating +1, and input data is at a low level indicating 0; the weight values are multiplied by the input data, i.e., 1 × 1=1,1 × 0=0,0 × 1=0,0 × 0= 0; when the weight value is +1 and the input data is 1, charging the coupling capacitor C; when the weight value is +1 and the input data is 0, discharging the coupling capacitor C; when the weight value is 0 and the input data is 1 or 0, the coupling capacitor C discharges; when the column selection signal input by the column selection line is 0V, the coupling capacitor C is precharged to 0.5V through the read bit line; when the column selection signal input by the column selection line is VDD and the weight value is 0, the coupling capacitor C discharges. Therefore, the implementation process of the specific circuit is divided into the steps of reading bit line pre-charging, coupling capacitor discharging and the like, and the following steps are specifically discussed by combining the calculation principle:

(1) reading bit line pre-charging:

as shown in fig. 2, before the selected current column starts to count, the column select signal is low, the transistor T12 is turned on, the transistor T12 precharges the coupling capacitor C via the read bit line through the column decode, bit line drive and precharge block in fig. 8, and the voltage at point a is precharged to 0.5V.

(2) And the charging principle of the coupling capacitor:

as shown in fig. 3, when the current column is selected, the column select signal input to the column select line is set to high level, the transistor T11 is turned on, and when the input data is at high level (i.e. 1V) and the weight =1 (expressed as Q =1 and QB =0), 1 × 1= +1 is completed, and in the circuit, when the transistor T8 and the transistor T9 are turned on, the input data charges the coupling capacitor C through the turned-on transistor T8 and the turned-on transistor T9, and the voltage at the point a increases with the charging of the two charging channels.

(3) The first principle of the discharge of the coupling capacitor is as follows:

as shown in fig. 4, when the current column is selected, the column select signal inputted to the column select line is set to high level, the transistor T11 is turned on, and when the input data is low level (i.e. 0V) and the weight =1 (expressed as Q =1, QB =0), 0 × 1=0 is completed, and in the circuit, in the case where the transistor T8 and the transistor T9 are turned on, since the input data is low level, the voltage at the a end of the coupling capacitor C pulls down the inputted low level through the turned-on transistor T8 and the turned-on transistor T9, and the circuit is expressed as discharge.

(4) And the second principle of coupling capacitor discharge:

as shown in fig. 5, when the current column is selected, the column select signal input to the column select line is set to high level, the transistor T11 is turned on, and when the weight value =0 (expressed as Q =0, QB =1), the transistor T8 is turned off and off, the transistor T7 is turned on, the transistor T9 is turned off and off, and the transistor T10 is turned on, and since the transistor T8 and the transistor T9 connected to the input are both turned off, the input cannot charge the coupling capacitor C regardless of 0 or 1; since both transistor T7 and transistor T10 are turned on and connected to common VSS, the coupling capacitor C will discharge to common VSS through both transistor T7 and transistor T10, which simplifies the inefficient multiply-accumulate calculation since any input data multiplied by a weight value of 0 is 0. The solid bold lines in fig. 2-5 represent the conductive path segments in the circuit and the solid gray lines represent the non-conductive path segments in the circuit.

Example 2

As shown in FIG. 6, the present invention discloses a voltage margin enhanced capacitively coupled storage bulk sub-array, comprising: k units as described in example 1; k is a positive integer greater than or equal to 2; each cell is connected with a word line, a bit line, an inversion line, an input line and a column selection line, a read bit line is connected with a source of a transistor T12 in a first existing calculation cell, a source of a transistor T12 in the first existing calculation cell is connected, and a drain of a transistor T12 in a kth existing calculation cell is connected with a source of a transistor T12 in a kth +1 existing calculation cell, wherein K is a positive integer greater than or equal to 1 and less than K. In this example, K is 4.

The pressure equalizing principle is as follows: as shown in fig. 7, after the input data is multiplied by the weight value, the calculation results are respectively expressed as voltages across the coupling capacitors in the sub-arrays, and the addition of the multiplied results can be performed by voltage equalization. When the column selection signal is set low, namely PMOS connected with the column selection signal in the subarray is conducted, the voltage equalizing result at two ends of the coupling capacitor is connected to a read bit line, and the read bit line is connected to an analog-digital converter (ADC) to digitize the multiplication and accumulation result. In fig. 7, a bold solid line indicates a conductive path section in the circuit, and a gray solid line indicates a non-conductive path section in the circuit.

Example 3

As shown in fig. 8, the present invention also discloses a voltage margin enhanced capacitive coupling storage integrated device, which comprises: the device comprises a first input module, a second input module, a third input module and a computing unit array; the first input module is a word line decoding and driving module I; the second input module is a column decoding, bit line driving and prestoring module II; the third input module is an input decoding and driving module; the computing unit array includes M × N sub-arrays ((M is a positive integer greater than 1)) set in embodiment 2, where N is a positive integer greater than 1.

The M word line ends of the first input module are respectively connected with the M word lines; the N column line selection ends of the second input module are respectively connected with the N column line selection ends, the bit line end of the second input module is connected with the bit line, and the bit bar end of the second input module is connected with the bit bar; the N reading bit line ends of the second input module are respectively connected with the N reading bit lines; and M input line ends of the third input module are respectively connected with M input lines.

Bit line ends of the M multiplied by N sub-arrays are all connected with bit lines, bit bar ends of the M multiplied by N sub-arrays are all connected with bit bars, column selection ends of the M sub-arrays in the j +1 th column are all connected with the jth column selection line, bit reading end ends of the M sub-arrays in the j +1 th column are all connected with the jth bit reading line, calculation word line ends of the N sub-arrays in the i +1 th row are all connected with the ith word line, input line ends of the N sub-arrays in the i +1 th row are all connected with the ith input line, wherein i is a positive integer larger than or equal to 0 and smaller than M, and j is a positive integer larger than or equal to 0 and smaller than N.

As an optional implementation, the apparatus of the present invention further comprises: n analog-to-digital converters; one end of the (j + 1) th analog-digital converter inputs a reference voltage, the other end of the (j + 1) th analog-digital converter is connected with the jth reading bit line, and the output end of the (j + 1) th analog-digital converter outputs an accumulation result; and the accumulation result is obtained by accumulating the data output by the M sub-arrays in the j +1 th column to the j-th reading bit line. In this embodiment, the computing unit array includes: 256 × 32 sub-arrays, i.e., M is 256 and N is 32.

As shown in FIG. 8, the 0 th word line is word line [0] in FIG. 8, and so on; the first input line is input line [0] in FIG. 8, and so on; the 0 th column selection line is the column selection line [0] in fig. 8, and so on in the following; the 0 th read bit line is read bit line [0] in FIG. 8, and so on; the first analog-to-digital converter is Q [0] in FIG. 8, and so on.

The voltage margin enhancement type capacitive coupling storage and calculation integrated unit disclosed by the invention has the following advantages:

1. compared with a storage weight method of DRAM 1T1C, the storage part of the voltage margin enhancement type capacitive coupling storage integrated unit disclosed by the invention adopts a classic 6T-SRAM storage unit as a weight value storage, so that the weight value has no leakage and does not need periodic refreshing to keep the weight, and the power consumption is greatly saved. And the weighted value is connected to the grid of the transistor, so that no read-write interference exists on the weighted value in the calculation process.

2. The invention discloses an operation part in a voltage margin enhancement type capacitive coupling and storage integrated unit, which simplifies 75% of multiplication and accumulation operation amount, wherein four multiplication combinations are realized by traditional memory calculation, namely 1 multiplied by 1=1,1 multiplied by 0=0,0 multiplied by 1=0 and 0 multiplied by 0=0, in the invention, only when the weight value and the input data are both 1, the calculation result contributes to the voltage rise at two ends of a coupling capacitor, namely 1 multiplied by 1=1, and for the input data of 0,0 multiplied by 1=0 or the weight value of 0,1 multiplied by 0=0 and 0 multiplied by 0=0, the voltage-sharing time of the voltage at two ends of a reading bit line can be reduced by the calculation without effective contribution to the voltage at two ends of the coupling capacitor C, and the voltage-sharing time of the voltage at both power consumption and calculation speed is greatly improved.

3. When the memory calculation basic unit calculation circuit disclosed by the invention realizes multiplication with the weight value of 1 and the input data of 1,1 multiplied by 1=1, two channels charge the coupling capacitor C, and compared with a common calculation circuit with single-ended charging, if the coupling capacitor C is charged to a rated voltage value, only 50% of charging time of a single-ended charging mode is needed, so that the calculation process is greatly accelerated; if the charging time is the same, the voltage value at the two ends of the coupling capacitor C is 2 times that of the single-end charging mode, so that the voltage quantization range on the read bit line in the ADC quantization process is theoretically improved by 2 times. Similarly, in the same manner, when 0 × 1=0,0 × 0=0, and 1 × 0=0 is calculated, that is, when discharging, there are two discharge channels, and the discharge speed is theoretically twice as fast as that of single-ended discharge, which accelerates the calculation process.

4. The invention discloses an SRAM (memory storage) calculation circuit structure realized by easily-quantized multi-bit weights based on an SRAM (static random access memory), which can realize the multiplication of single-bit input data and four-bit weight values in a single period, and accumulate the multiplication and accumulation results on a read bit line through voltage. In addition, only effective calculation results are accumulated in the calculation process, the calculation process is optimized, the ADC quantization time is saved, and the power consumption for realizing the internal calculation is reduced to a certain extent.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (8)

1. A voltage margin enhanced capacitively coupled storage all-in-one unit, the unit comprising:

the 6T-SRAM storage unit is used for reading, writing and storing the weight value;

the computing unit is connected with the 6T-SRAM storage unit and is used for multiplying input data by a weight value;

the word line end of the 6T-SRAM storage unit is connected with a word line, the bit line end of the 6T-SRAM storage unit is connected with a bit line, and the bit bar end of the 6T-SRAM storage unit is connected with a bit bar line;

the input line end of the computing unit is connected with an input line, and the column line selection end of the computing unit is connected with a column line selection; the reading bit line end of the computing unit is connected with a reading bit line; the input line is used for transmitting input data;

the calculation unit includes: a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, and a coupling capacitance C;

the drain of the transistor T7, the source of the transistor T10, and the other end of the coupling capacitor C are all connected to a common terminal VSS, the gate of the transistor T7 and the gate of the transistor T8 are all connected to a point Q on the 6T-SRAM memory cell, the source of the transistor T7, the source of the transistor T8, the drain of the transistor T9, and the drain of the transistor T10 are all connected to the source of the transistor T11, the gate of the transistor T9 and the gate of the transistor T10 are all connected to a point QB on the 6T-SRAM memory cell, the gate of the transistor T11 and the gate of the transistor T12 are all connected to a column select line, and the drain of the transistor T11 and the drain of the transistor T12 are all connected to one end of the coupling capacitor C.

2. The voltage margin-enhanced capacitively coupled memory integrated unit of claim 1, wherein the 6T-SRAM memory cell comprises:

a transistor T1, a transistor T2, a transistor T3, a transistor T14, a transistor T5, and a transistor T6;

a source of the transistor T1 and a source of the transistor T2 are connected to a power supply VDD, a gate of the transistor T1, a gate of the transistor T3, a drain of the transistor T2, and a drain of the transistor T4 are connected to a point Q, a gate of the transistor T2, a gate of the transistor T4, a drain of the transistor T1, and a drain of the transistor T3 are connected to a point QB, a source of the transistor T3 and a source of the transistor T4 are connected to a common terminal VSS, a gate of the transistor T5 and a gate of the transistor T6 are connected to a word line, a drain of the transistor T5 is connected to a point QB, a source of the transistor T5 is connected to a bit line, a source of the transistor T6 is connected to a point Q, and a drain of the transistor T6 is connected to an inverted bit line.

3. The voltage margin-enhanced capacitively coupled memory integrated unit of claim 1, wherein the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T8, the transistor T10, and the transistor T11 are all NMOS, and the transistor T1, the transistor T2, the transistor T7, the transistor T9, and the transistor T12 are all PMOS.

4. The voltage margin-enhanced capacitively coupled memory integrated unit of claim 1, wherein when Q =0V, QB = VDD, the weight value is 0; when Q = VDD, QB =0V, the weight value at this time is + 1; wherein VDD = 1V;

when the weight value is +1 and the input data is 1, charging the coupling capacitor C; when the weight value is +1 and the input data is 0, discharging the coupling capacitor C; when the weight value is 0 and the input data is 1 or 0, the coupling capacitor C discharges; when the column selection signal input by the column selection line is 0V, the coupling capacitor C is precharged to 0.5V through the read bit line; when the column selection signal input by the column selection line is VDD and the weight value is 0, the coupling capacitor C discharges.

5. A voltage margin enhanced capacitively coupled storage integral sub-array, the sub-array comprising:

k units according to any one of claims 1 to 4; k is a positive integer greater than or equal to 2;

each cell is connected with a word line, a bit line, an inversion line, an input line and a column selection line, a read bit line is connected with a source of a transistor T12 in a first existing calculation cell, a source of a transistor T12 in the first existing calculation cell is connected, and a drain of a transistor T12 in a kth existing calculation cell is connected with a source of a transistor T12 in a kth +1 existing calculation cell, wherein K is a positive integer greater than or equal to 1 and less than K.

6. A voltage margin enhanced capacitively coupled storage integrated apparatus, the apparatus comprising:

the device comprises a first input module, a second input module, a third input module and a computing unit array; the first input module is a word line decoding and driving module; the second input module is a row decoding module, a bit line driving module and a prestoring module; the third input module is an input decoding and driving module; the array of compute units comprises the subarray of claim 5 arranged in M x N arrays, where M is a positive integer greater than 1 and N is a positive integer greater than 1;

the M word line ends of the first input module are respectively connected with the M word lines;

the N column line selection ends of the second input module are respectively connected with the N column line selection ends, the bit line end of the second input module is connected with the bit line, and the bit bar end of the second input module is connected with the bit bar; the N reading bit line ends of the second input module are respectively connected with the N reading bit lines;

the M input line ends of the third input module are respectively connected with M input lines;

bit line ends of the M multiplied by N sub-arrays are all connected with bit lines, bit bar ends of the M multiplied by N sub-arrays are all connected with bit bars, column selection ends of the M sub-arrays in the j +1 th column are all connected with the jth column selection line, bit reading end ends of the M sub-arrays in the j +1 th column are all connected with the jth bit reading line, calculation word line ends of the N sub-arrays in the i +1 th row are all connected with the ith word line, input line ends of the N sub-arrays in the i +1 th row are all connected with the ith input line, wherein i is a positive integer larger than or equal to 0 and smaller than M, and j is a positive integer larger than or equal to 0 and smaller than N.

7. The voltage margin-enhanced capacitively coupled memory integrated apparatus of claim 6, further comprising:

n analog-to-digital converters; one end of the (j + 1) th analog-digital converter inputs a reference voltage, the other end of the (j + 1) th analog-digital converter is connected with the jth reading bit line, and the output end of the (j + 1) th analog-digital converter outputs an accumulation result; and the accumulation result is obtained by accumulating the data output by the M sub-arrays in the j +1 th column to the j-th reading bit line.

8. The voltage margin-enhanced capacitively coupled storage all-in-one device of claim 6, wherein the compute unit array comprises: 256 × 32 sub-arrays.

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