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CN113241946B - Direct current/direct current conversion circuit and direct current/direct current converter - Google Patents

Direct current/direct current conversion circuit and direct current/direct current converter Download PDF

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Publication number
CN113241946B
CN113241946B CN202110432839.2A CN202110432839A CN113241946B CN 113241946 B CN113241946 B CN 113241946B CN 202110432839 A CN202110432839 A CN 202110432839A CN 113241946 B CN113241946 B CN 113241946B
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output voltage
signal
output
transistor
voltage
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CN113241946A (en
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赵猛
闫桂珍
陈中建
鲁文高
张雅聪
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides a direct current/direct current conversion circuit and a direct current/direct current converter, and relates to the technical field of integrated circuits. The circuit comprises: the device comprises an output unit, a rectifying unit and a detection control unit; the output unit receives an input voltage and outputs a first output voltage to the rectifying unit and the detection control unit; the rectification unit rectifies and filters the first output voltage, outputs a second output voltage, generates a first signal and transmits the first signal to the detection control unit; the detection control unit receives the first signal and the first output voltage and generates a control signal to control the DC/DC conversion circuit to work in an accelerated charging mode, a normal charging mode or a sleep mode. The direct current/direct current conversion circuit of the embodiment of the invention shortens the establishment time of the output voltage of the direct current/direct current converter while reducing the output voltage ripple, and has higher practical value.

Description

Direct current/direct current conversion circuit and direct current/direct current converter
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a dc/dc converter circuit and a dc/dc converter.
Background
At present, the direct current/direct current converter has important application in MEMS accelerometer and MEMS gyroscope interface integrated circuits. In particular, the boost-type dc/dc converter provides a sufficiently high drive voltage for the closed-loop MEMS inertial sensor to generate a sufficiently high electrostatic force to perform the closed-loop feedback function. The closed-loop MEMS inertial sensor system has high requirements on the establishment time and the ripple amplitude of the driving voltage, and a DC/DC (direct current/direct current) converter with a traditional structure usually adopts a boosting scheme of charging current which is fixed or in proportion to the difference value of the reference voltage and the output voltage, so that the requirements of low ripple and quick establishment are difficult to meet under the condition of keeping low static power consumption.
The charging current of the boost type direct current/direct current converter with the traditional structure is inversely proportional to the voltage establishment time and is directly proportional to the ripple size and the static power consumption, the direct current/direct current converter with the traditional structure is difficult to realize the rapid establishment of the voltage in order to ensure low static power consumption, the voltage establishment time is usually in the order of tens of milliseconds, and the requirement that the voltage establishment time of the MEMS inertial sensor is lower than 10 milliseconds cannot be met. Even if dynamic charging current is adopted, the charging current is in direct proportion to the difference value of the reference voltage and the output voltage, when the output voltage is close to the reference voltage, the charging current becomes smaller, so that the stabilization time of the output voltage rising to a preset value is increased, and the requirement of completely and stably establishing the driving voltage of the MEMS inertial sensor in a short time still cannot be met. In addition, the high-precision MEMS inertial sensor requires that the ripple of the driving voltage is lower than 1mV, and the ripple is difficult to be limited below 1mV by the DC/DC converter with the traditional structure. Therefore, it is an urgent problem to reduce the output voltage ripple and shorten the settling time of the output voltage of the boost dc/dc converter.
Disclosure of Invention
The invention provides a direct current/direct current conversion circuit and a direct current/direct current converter, and provides a technical scheme for reducing output voltage ripples and shortening the establishment time of the output voltage of a boost direct current/direct current converter.
A first aspect of an embodiment of the present invention provides a dc/dc conversion circuit, where the circuit includes: the device comprises an output unit, a rectifying unit and a detection control unit;
the output unit receives an input voltage and outputs a first output voltage to the rectifying unit and the detection control unit, wherein the first output voltage is higher than the input voltage;
the rectification unit rectifies and filters the first output voltage, outputs a second output voltage, generates a first signal and transmits the first signal to the detection control unit, and the first signal represents whether the second output voltage is established or not;
the detection control unit receives the first signal and the first output voltage and generates a control signal to control the direct current/direct current conversion circuit to work in an accelerated charging mode, a normal charging mode or a sleep mode;
wherein the accelerated charging mode is: a mode of boosting the first output voltage with a highest allowable charging current;
the normal charging mode is as follows: a mode of boosting the first output voltage with a preset charging current;
the sleep mode is as follows: a mode of stopping boosting the first output voltage until the first output voltage drops below a reference voltage.
Optionally, the output unit includes: an inductor, a first power transistor and a second power transistor;
the first end of the inductor receives the input voltage, and the second end of the inductor is respectively connected with the drain electrode of the first power transistor and the drain electrode of the second power transistor;
the grid electrode of the first power transistor is connected with a driving module in the detection control unit;
the source electrode of the first power transistor is grounded;
the grid electrode of the second power transistor is connected with the driving module;
the source electrode of the second power transistor is connected with the rectifying unit, and the source electrode of the second power transistor outputs the first output voltage.
Optionally, the rectifying unit includes: the power amplifier comprises a third power transistor, a first resistor, a second resistor, a first inverter and an operational amplifier;
the source electrode of the third power transistor is connected with the source electrode of the second power transistor;
the grid electrode of the third power transistor is respectively connected with the output end of the operational amplifier and the input end of the first inverter;
the drain electrode of the third power transistor is connected with the first end of the first resistor, and the drain electrode of the third power transistor outputs the second output voltage;
the second end of the first resistor is connected with the first end of the second resistor and the non-inverting end of the operational amplifier;
the second end of the second resistor is grounded;
the inverting terminal of the operational amplifier receives the reference voltage;
the output end of the first phase inverter is connected with a first pulse generation module in the detection control unit, and the output end of the first phase inverter outputs the first signal.
Optionally, the detection control unit includes: the circuit comprises a third resistor, a fourth resistor, a first comparator, a second pulse generation module, a logic control module and a second inverter;
the first end of the third resistor is connected with the in-phase end of the first comparator, and the first end of the third resistor receives the first output voltage;
the second end of the third resistor is respectively connected with the first end of the fourth resistor and the in-phase end of the second comparator;
a second end of the fourth resistor is grounded;
the inverting terminal of the first comparator receives the voltage of the second terminal of the inductor;
the output end of the first comparator is connected with the input end of the logic control module, the output end of the first comparator outputs a third signal, and the third signal represents the current flowing direction between the second end of the inductor and the source electrode of the second power transistor;
the inverting terminal of the second comparator receives the reference voltage;
the output end of the second comparator is connected with the input end of the logic control module, the output end of the second comparator outputs a second signal, and the second signal represents the magnitude relation between the first output voltage and the reference voltage;
the output end of the logic control module is connected with the input end of the driving module;
the output end of the driving module is respectively connected with the grid electrode of the first power transistor, the grid electrode of the second power transistor, the input end of the second inverter and the input end of the second pulse generating module, and the driving module outputs the control signal;
the output end of the second pulse generation module is connected with the logic control module;
and the output end of the second inverter is connected with the first pulse generation module.
Optionally, the method comprises: the first pulse generating module includes: the energy storage capacitor array, the first common transistor and the third comparator;
the first end of the energy storage capacitor array is respectively connected with a charging current source, the in-phase end of the third comparator and the drain electrode of the first common transistor;
the second end of the energy storage capacitor array receives the first signal and an external digital control signal;
the third end of the energy storage capacitor array is connected with the source electrode of the first common transistor and is grounded;
the grid electrode of the first common transistor is connected with the output end of the second inverter;
the inverting terminal of the third comparator receives the reference voltage;
the output end of the third comparator is connected with the logic control module, and the output end of the third comparator outputs the first pulse signal.
Optionally, the energy storage capacitor array includes: a second common transistor, a third common transistor, a fourth common transistor, a fifth common transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first or gate, a second or gate, and a third or gate;
and respective drains of the second common transistor, the third common transistor, the fourth common transistor and the fifth common transistor are respectively connected with the charging current source, the in-phase end of the third comparator, the drain of the first common transistor and the first end of the fifth capacitor.
The grid electrode of the second common transistor is respectively connected with the first input end of the first OR gate, the first input end of the second OR gate, the first input end of the third OR gate and the output end of the first reverser;
the source electrode of the second common transistor is connected with the first end of the first capacitor;
a second end of the first capacitor, a second end of the second capacitor, a second end of the third capacitor, a second end of the fourth capacitor, a second end of the fifth capacitor and a source electrode of the first common transistor are respectively connected and grounded;
the grid electrode of the third common transistor is connected with the output end of the first OR gate;
the grid of the fourth common transistor is connected with the output end of the second OR gate;
the grid of the fifth common transistor is connected with the output end of the third OR gate;
a second input end of the first OR gate receives a first digital control signal in the external digital control signals;
a second input end of the second OR gate receives a second digital control signal in the external digital control signals;
a second input of the third or-gate receives a third digital control signal of the external digital control signals.
Optionally, the first signal is at a high level to indicate that the second output voltage is completely established, and the first signal is at a low level to indicate that the second output voltage is not completely established;
the third signal represents the second end of the inductor for high level, and the current flowing direction between the source electrode of the second power transistor is as follows: flowing from a source of the second power transistor to a second terminal of the inductor;
the third signal represents the second end of the inductor for low level, and the current flowing direction between the source electrode of the second power transistor is as follows: flowing from a second terminal of the inductor to a source of the second power transistor;
the second signal is high level indicating that the first output voltage is higher than the reference voltage, and the second signal is low level indicating that the first output voltage is lower than the reference voltage.
Optionally, the criteria for completing the establishment of the second output voltage are: the magnitude of the second output voltage is equal to the product of the reference voltage and a first proportion;
the standard that the second output voltage is not established is as follows: the magnitude of the second output voltage is less than the product of the reference voltage and the first proportion;
the criterion that the first output voltage is higher than the reference voltage is: the magnitude of the first output voltage is greater than the product of the reference voltage and a second proportion, wherein the second proportion is greater than the first proportion;
the criterion that the first output voltage is lower than the reference voltage is: the magnitude of the first output voltage is not greater than the product of the reference voltage and the second ratio.
Optionally, when the first signal is at a high level, the second common transistor, the third common transistor, the fourth common transistor, and the fifth common transistor are all turned on, a capacitance value of the energy storage capacitor array is a preset maximum capacitance value, and a duration of the first pulse signal maintaining at a low level is longest;
when the first signal is at a low level, the second common transistor is turned off, the third common transistor, the fourth common transistor and the fifth common transistor are controlled by the external digital signal, a capacitance value of the energy storage capacitor array is determined by the external digital signal, and a duration of the first pulse signal at the low level is determined by the external digital signal.
A second aspect of an embodiment of the present invention provides a dc/dc converter, including: a circuit as claimed in any one of the first aspect.
The invention provides a direct current/direct current conversion circuit, wherein an output unit receives an input voltage, outputs a first output voltage higher than the input voltage to a rectifying unit and a detection control unit, the rectifying unit rectifies and filters the first output voltage, reduces ripples of the first output voltage and outputs a second output voltage with low ripples, meanwhile, the rectifying unit generates a first signal representing whether the second output voltage is established or not and transmits the first signal to the detection control unit, and the detection control unit generates a control signal after receiving the first signal and the first output voltage so as to control the direct current/direct current conversion circuit to work in an accelerated charging mode, or work in a normal charging mode, or work in a sleep mode. When the DC/DC conversion circuit works in the accelerated charging mode, the whole circuit increases the first output voltage by the highest allowable charging current, so that the first output voltage is quickly established, namely the second output voltage is quickly established. The detection control unit can switch between an acceleration charging mode and a normal charging mode based on the first signal and the first output voltage, the charging current is large in the acceleration charging mode to shorten the output voltage establishing time, and the proper output current is maintained and lower output ripples are guaranteed in the normal charging mode to improve the noise performance of the sensor. The direct current/direct current conversion circuit reduces output voltage ripples, shortens the establishment time of the output voltage of the direct current/direct current converter, and has high practical value.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a circuit configuration diagram of a boost type dc/dc converter of a conventional structure;
FIG. 2 is a block diagram of a DC/DC converter circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a preferred DC/DC converter circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a preferred rectifier circuit 200 according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a preferred first pulse generating module 340 according to an embodiment of the present invention;
fig. 6 is a waveform diagram of a dc/dc conversion circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The inventor finds that the current direct current/direct current converter with the traditional structure is difficult to limit the ripple at a low level, and meanwhile, the output voltage has a long establishing time, so that the working requirement of the MEMS inertial sensor is difficult to meet. The inventor further studied and found the cause of the above problem, and combined with the circuit structure diagram of the boost type dc/dc converter with the conventional structure shown in fig. 1, fig. 1 includes a P-type power transistor M1N-type power transistor M2Inductor L, resistance voltage-dividing circuit (formed by resistor R)1And R2Make up), a comparator CMP, a current detection module ISENSE, a PULSE generator PULSE, a LOGIC controller LOGIC, a DRIVER for the power transistors (M1 and M2).
When the circuit in FIG. 1 is in operation, the resistor divider circuit divides the voltage to obtain the output voltage VOUTProportional feedback voltage VFBAnd the voltage V of the second terminal of the inductor LSWComparing the comparison result by a comparator CMP to generate a judgment signal and outputting the judgment signal to a LOGIC control circuit LOGIC; the PULSE generator PULSE generates a PULSE signal for controlling the charging time of the inductor L so as to control the P-type power transistor M1Source output VOUTThe charging current of (1); the current detection module ISENSE detects the current flowing through the P-type power tube M1Whether the charging current is zero or not is judged, and the output V is judgedOUTWhether the charging is finished or not, and the P-type power tube M is turned off after the charging is finished1。
Since the charging current of the dc/dc converter is inversely proportional to the voltage setup time and directly proportional to the ripple size and the static power consumption, the dc/dc converter with the conventional structure in fig. 1 hardly achieves the fast setup of the voltage to ensure low static power consumption, and the voltage setup time is usually in the order of tens of milliseconds, which cannot meet the requirement that the voltage setup time of the MEMS inertial sensor is less than 10 milliseconds. Even if dynamic charging current is adopted, the charging current is in direct proportion to the difference value of the reference voltage and the output voltage, when the output voltage is close to the reference voltage, the charging current becomes smaller, so that the stabilization time of the output voltage rising to a preset value is increased, and the requirement of completely and stably establishing the driving voltage of the MEMS inertial sensor in a short time still cannot be met. In addition, the high-precision MEMS inertial sensor requires that the ripple of the driving voltage is lower than 1mV, and the dc/dc converter with the conventional structure shown in fig. 1 has a difficulty in limiting the ripple to less than 1mV due to the circuit structure and the characteristics of the components.
Based on the above problems, the inventors have made extensive research, practical tests, and simulations to inventively provide the dc/dc conversion circuit according to the embodiment of the present invention, and the dc/dc conversion circuit according to the embodiment of the present invention will be explained and explained in detail below.
Referring to fig. 2, a modular schematic diagram of a dc/dc converter circuit according to an embodiment of the present invention is shown. The DC/DC conversion circuit includes: the device comprises an output unit, a rectifying unit and a detection control unit; the output unit receives an input voltage and outputs a first output voltage higher than the input voltage to the rectifying unit and the detection control unit; the rectification unit rectifies and filters the first output voltage, outputs the second output voltage with reduced ripples, generates a first signal representing whether the second output voltage is established or not and transmits the first signal to the detection control unit; the detection control unit receives the first signal and the first output voltage and generates a control signal to control the DC/DC conversion circuit to work in an accelerated charging mode, a normal charging mode or a sleep mode. Wherein, the accelerating charging mode is as follows: the mode of raising the first output voltage with the highest allowable charging current thus ensures a fast build-up of the second output voltage; after the second output voltage is established, entering a normal charging mode, wherein the normal working mode is as follows: and raising the first output voltage by a preset charging current. The detection circuit unit switches between an acceleration charging mode and a normal charging mode based on the first signal and the first output voltage, the charging current is large in the acceleration charging mode to shorten the output voltage establishing time, and the proper output current is maintained and lower output ripples are guaranteed in the normal charging mode to improve the noise performance of the sensor. In addition, when the first output voltage is larger, a sleep mode is entered, and the sleep mode is as follows: and stopping increasing the first output voltage until the first output voltage drops below the reference voltage. Because only part of components work in the sleep mode, the static power consumption of the direct current/direct current conversion circuit is indirectly reduced.
Referring to fig. 3, a schematic diagram of a preferred dc/dc conversion circuit according to an embodiment of the present invention is shown, where fig. 3 includes: an output circuit 100, a rectifier circuit 200 and a detection control circuit 300. The output circuit 100 specifically includes: inductor L, first power transistor MN _ PW, and second power transistor MP _ PW. The specific structure of the rectifier circuit 200 is shown in fig. 4 and is not described in detail. The detection control circuit 300 includes: by a third resistor R3And a fourth resistor R4The circuit comprises a voltage division circuit 310, a first comparator 320, a second comparator 330, a first pulse generation module 340, a second pulse generation module 350, a logic control module 360 and a driving module 370. The specific structure of the first pulse generating module 340 is shown in fig. 5 and is not described in detail.
In FIG. 3, VinRepresenting the input voltage, VOUT1Representing a first output voltage, VSWThe voltage of the second terminal of the inductor L, i.e., the drain voltage of the first power transistor MN _ PW and the drain voltage of the second power transistor MP _ PW, is represented. SN denotes a gate control signal of the first power transistor MN _ PW, SP denotes a gate control signal of the second power transistor MP _ PW, which is sent by the driving block 370, and the driving block 370 receives a logic signal sent by the logic control block 360 to generate two control signals. TM1 denotes a first pulse signal, TM2 denotes a second pulse signal, D denotes an external digital control signal, NSN represents an inverted signal of the SN signal. H1 denotes a first signal, H2 denotes a second signal, H3 denotes a third signal, C0An output capacitor, R, representing a first output voltageLAnd CLRespectively representing the load resistance and the load capacitance of the second output voltage.
In fig. 3, the first terminal of the inductor L receives the input voltage VinThe second end of the inductor L is connected with the drain electrode of the first power transistor MN _ PW and the drain electrode of the second power transistor MP _ PW respectively; the gate of the first power transistor MN _ PW is connected to the driving module 370 in the detection control unit; the source electrode of the first power transistor MN _ PW is grounded; the gate of the second power transistor MP _ PW is connected to the driving module 370; a source of the second power transistor MP _ PW is connected to the rectifying unit 200, and the source of the second power transistor MP _ PW outputs the first output voltage VOUT1。
In the embodiment of the invention, the first power transistor MN _ PW and the second power transistor MP _ PW are controlled to be alternately turned on to realize voltage conversion. The first power transistor MN _ PW and the second power transistor MP _ PW are not turned on at the same time, but may be turned off at the same time. That is, when the first power transistor MN _ PW is turned on, the second power transistor MP _ PW is turned off, and when the second power transistor MP _ PW is turned on, the first power transistor MN _ PW is turned off, or the first power transistor MN _ PW and the second power transistor MP _ PW are simultaneously turned off.
In the embodiment of the present invention, as a preferable mode, the inductor L may be disposed outside the chip, and other circuit portions may be integrated inside the chip. In addition, in the embodiment of the present invention, the output circuit 100 in the dc/dc conversion circuit is a boost type, or the circuit in the embodiment of the present invention may be applied to a structure in which the output circuit 100 is a buck type, at this time, the connection relationship among the inductor L, the first power transistor MN _ PW, and the second power transistor MP _ PW in the output circuit 100 is adjusted, and the specific connection relationship belongs to the prior art, and is not described here again.
Referring to fig. 4, a schematic diagram of a preferred rectifier circuit 200 according to an embodiment of the present invention is shown. Fig. 4 includes: a first resistor R1A second resistor R2An operational amplifier 220,A third power transistor MP0, a first inverter INV1, wherein the first resistor R1And a second resistor R2A voltage sampling circuit 210 is constructed.
The source of the third power transistor MP0 is connected to the source of the second power transistor MN _ PW, which is equivalent to receiving the first output voltage VOUT1(ii) a The gate of the third power transistor MP0 is connected to the output terminal of the operational amplifier 220 and the input terminal of the first inverter INV 1; the drain of the third power transistor MP0 and the first resistor R1Is connected to the first terminal of the third power transistor MP0, the drain of the third power transistor MP0 outputs a second output voltage VOUT2(ii) a The second output voltage VOUT2And providing the load with the use. I.e. the second output voltage VOUT2Is the external output voltage of the DC/DC converter.
A first resistor R1Second terminal and second resistor R2Is connected to the non-inverting terminal of the operational amplifier 220, a first resistor R1And a second resistor R2The formed voltage division circuit is used for the second output voltage VOUT2Dividing the voltage to obtain a second feedback voltage VFB2Second feedback voltage VFB2As the non-inverting input of operational amplifier 220; a second resistor R2The second terminal of (1) is grounded; the inverting terminal of the operational amplifier 220 receives the reference voltage VREF(ii) a The output terminal of the first inverter 220 is connected to the first pulse generating module 340 in the detection control unit, and the output terminal of the first inverter 220 outputs the first signal H1 to the first pulse generating module 340.
In the embodiment of the present invention, the operational amplifier 220 is based on the second feedback voltage VFB2And a reference voltage VREFObtaining an error amplification voltage N1, controlling the gate of the third power transistor MP0 by the error amplification voltage N1, and adjusting the second output voltage VOUT2Suppressing the second output voltage VOUT2The ripple of (3). After simulation and actual measurement, the second output voltage V of the rectifying circuit 200OUT2The ripple amplitude is larger than the first output voltage VOUT1The ripple amplitude is attenuated by about 50 times, and compared with the conventional DC/DC converter, the second output voltage V is greatly reducedOUT2Ripple wave。
Meanwhile, the first inverter INV1 obtains the first signal H1 based on the error amplified voltage N1 output by the operational amplifier 220, the first signal H1 being high level indicates the second output voltage VOUT2Is equal to the reference voltage VREFProduct of the first ratio, the second output voltage VOUT2After the setup is completed, the first signal H1 is low to indicate that the second output voltage is lower than the reference voltage VREFProduct of the first ratio, the second output voltage VOUT2The setup is not yet complete. Wherein the first proportion is a design value according to a preset second output voltage VOUT2Magnitude and reference voltage VREFAnd the size is obtained through calculation.
Referring to fig. 3, the detection control unit 300 includes: third resistor R3A fourth resistor R4The pulse generator comprises a first comparator 330, a second comparator 320, a first pulse generation module 340, a second pulse generation module 350, a logic control module 360, a driving module 370 and a second inverter INV 2.
Wherein the third resistor R3Is connected to the non-inverting terminal of the first comparator 330, and a third resistor R3A first terminal of receives a first output voltage VOUT1(ii) a That is, the non-inverting terminal of the first comparator 330 receives the first output voltage VOUT1。
Third resistor R3Second terminal and fourth resistor R4The non-inverting terminal of the second comparator 320 and the inverting terminal of the first comparator are respectively connected; a fourth resistor R4The second terminal of (1) is grounded; third resistor R3A fourth resistor R4Form another divided voltage 310, which is also applied to the first output voltage VOUT1Dividing voltage to obtain a first feedback voltage VFB1. First feedback voltage VFB1As the non-inverting input of the second comparator 320.
The inverting terminal of the first comparator 330 receives the voltage of the second terminal of the inductor L (denoted by V in fig. 2)SWRepresents); the output terminal of the first comparator 330 is connected to the input terminal of the logic control module 360, the output terminal of the first comparator 330 outputs a third signal H3, the third signal H3 represents the second terminal of the inductor L, and is connected to the source of the second power transistor MP _ PWThe current flow direction of (2); that is, the third signal H3 represents VSWAnd VOUT1To flow of current in between. The third signal H3 characterizes V for a high levelSWAnd VOUT1The current flow direction therebetween is: from VOUT1Flow direction VSW(ii) a The third signal H3 represents V for low levelSWAnd VOUT1The current flow direction therebetween is: from VSWFlow direction VOUT1。
The inverting terminal of the second comparator 320 receives the reference voltage VREF(ii) a The output terminal of the second comparator 320 is connected to the input terminal of the logic control module 360, the output terminal of the second comparator 320 outputs a second signal H2, and the second signal H2 represents the first output voltage VOUT1And a reference voltage VREFThe magnitude relationship between them. The second signal H2 represents the first output voltage V for high levelOUT1Higher than reference voltage VREFMultiplied by the second ratio, the third signal H2 is low to represent the first output voltage VOUT1Below the reference voltage VREFAnd a product of a second ratio, wherein the second ratio is greater than the first ratio.
The output end of the logic control module 360 is connected with the input end of the driving module 370; an output end of the driving module 370 is connected to a gate of the first power transistor MN _ PW, a gate of the second power transistor MP _ PW, an input end of the second inverter INV2, and an input end of the second pulse generating module 350, respectively, and the driving module 370 outputs a gate control signal SN of the first power transistor MN _ PW and a gate control signal SP of the second power transistor MP _ PW based on the received logic signal of the logic control module 360.
The output end of the second pulse generating module 350 is connected with the logic control module 360; the output end of the second inverter INV2 is connected to the first pulse generating module 340, and it inverts the gate control signal SN of the first power transistor MN _ PW to obtain the NSN signal, which is output to the first pulse generating module 340.
Referring to fig. 5, a schematic diagram of a preferred first pulse generating module 340 according to an embodiment of the present invention is shown. Fig. 5 includes: an energy storage capacitor array 341, a first common transistor MN1, and a third comparator 342; the second of the energy storage capacitor array 341One end (V in FIG. 5)RAMP) And a charging current source (I in FIG. 5)B) The non-inverting terminal of the third comparator 342 and the drain of the first common transistor MN1 are connected respectively; the second terminal of the storage capacitor array 341 receives the first signal H1 and the external digital control signal D [2:0]](ii) a The third end of the energy storage capacitor array 341 is connected with the source of the first common transistor MN1 and grounded; the gate of the first normal transistor MN1 is connected to the output terminal of the second inverter INV2, i.e., the gate of the first normal transistor MN1 receives the NSN signal.
The inverting terminal of the third comparator 342 receives the reference voltage VREF(ii) a The output terminal of the third comparator 342 is connected to the logic control module 360, and the output terminal of the third comparator 342 outputs the first pulse signal TM 1.
Specifically, the energy storage capacitor array 341 includes: a second common transistor MN2, a third common transistor MN3, a fourth common transistor MN4, a fifth common transistor MN5, a first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4A fifth capacitor C5A first OR gate OR1, a second OR gate OR2, and a third OR gate OR 3.
The drains of the second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4 and the fifth common transistor MN5 are connected to the charging current source IBThe non-inverting terminal of the third comparator 342, the drain of the first common transistor MN1, and the fifth capacitor C5Are connected respectively. The drain voltages of the second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4 and the fifth common transistor MN5 are VRAMP。
A gate of the second common transistor MN2 is connected to a first input terminal of the first OR gate OR1, a first input terminal of the second OR gate OR2, a first input terminal of the third OR gate OR3, and an output terminal of the first inverter INV1, respectively, and receives the first signal H1; the source of the second common transistor MN2 and the first capacitor C1Is connected with the first end of the first connecting pipe; a first capacitor C1Second terminal, second capacitor C2Second terminal, third capacitor C3Second terminal, fourth capacitor C4Second terminal, fifth capacitor C5And the source of the first common transistor MN1 are connected to ground. The gate of the third common transistor MN3 is connected to the output terminal of the first OR gate OR 1; the gate of the fourth common transistor MN4 is connected to the output of the second OR gate OR 2; the gate of the fifth common transistor MN5 is connected to the output terminal of the third OR gate OR 3.
A second input of the first OR gate OR1 receives a first digital control signal D [2] of the external digital control signals D [2:0 ]; a second input of the second OR gate OR2 receives a second digital control signal D [1] of the external digital control signals D [2:0 ]; a second input of the third OR gate OR3 receives the third digital control signal D [0] of the external digital control signals D [2:0 ].
Referring to fig. 5, the width of the first pulse signal TM1 is the charging current source IBAnd the effective capacitance of the storage capacitor array 341, wherein the effective capacitance of the storage capacitor array 341 is controlled by the external digital control signal D [2:0]]And a first signal H1. The first pulse signal TM1 is used to control the on-time of the first power transistor MN _ PW, and further control the first output voltage VOUT1The charging current of (1). When the entire conversion current operates in the accelerated charging mode, the capacitance of the energy storage capacitor array 341 is configured to be the preset maximum value, and at this time, the pulse width of the first pulse signal TM1 output by the first pulse generating module 340 is the widest, the on-time of the first power transistor MN _ PW is the longest, and the first output voltage V is the longestOUT1The charging current being maximum, i.e. the first output voltage V is raised by the highest allowable charging currentOUT1. When the whole conversion current is in other modes, the capacitance of the storage capacitor array 341 is controlled by the external digital control signal D [2:0]]At this time, the width of the first pulse signal TM1 outputted by the first pulse generation module 340 is determined by the external digital control signal D [2:0]]Determining, with a corresponding current, a first output voltage VOUT1And (6) charging.
Charging current source IBProviding a reference current to charge the energy storage capacitor array 341; the first common transistor MN1 is configured to apply the upper plate voltage V of the energy storage capacitor array 341 at NSN high level according to the inverted signal NSN of the gate control signal SN of the first power transistor MN _ PWRAMP(i.e., the voltage at the first terminal of the energy storage capacitor array 341) quickly discharges to zero level; the third comparator 342 compares the voltage V of the upper electrode plate of the energy-storage capacitor arrayRAMPAnd a reference voltage VREFA first pulse signal TM1 is obtained. When the voltage V of the upper plate of the energy storage capacitor array 341RAMPGreater than a reference voltage VREFWhen the first pulse signal TM1 is at a high level, the first power transistor MN _ PW is turned off; when the voltage V of the upper plate of the energy storage capacitor array 341RAMPLess than reference voltage VREFWhen the first pulse signal TM1 is at a low level, the first power transistor MN _ PW is turned on.
In the embodiment of the present invention, the second pulse generating module 350 has a similar structure to the first pulse generating module 340, but the size of the energy storage capacitor in the energy storage capacitor array is fixed, and the energy storage capacitor array passes through the charging current source IBCharging the energy storage capacitor generates the second pulse signal TM2 with a specified width, which is not separately illustrated due to the similar structure.
The width of the second pulse signal TM2 is the charging current source IBAnd the storage capacitance. The second pulse generating module 350 is configured to limit a time when the first power transistor MN _ PW and the second power transistor MP _ PW are turned off simultaneously and a time when the second power transistor MP _ PW is turned on, and restart a switching operation of the current period after the time when the first power transistor MN _ PW and the second power transistor MP _ PW are turned off simultaneously or the time when the second power transistor MP _ PW is turned on exceeds a width of the second pulse signal TM2, so as to avoid a state lock of the entire dc/dc conversion circuit due to insufficient charging current or excessive load.
In the embodiment of the present invention, the logic control module 360 receives various signals to determine the operating state of the dc/dc converter. The various signals include: a third signal H3, a second signal H2, a first pulse signal TM1, and a second pulse signal TM 2. The logic control module 360 generates the control logic desired to be implemented by the detection control circuit 300 based on the various signals. Since the driving of the power transistor requires a higher voltage, a driving circuit 370 is designed, and the driving circuit 370 receives the logic signal generated by the logic control module 360, boosts the logic signal to generate the gate control signal SN of the first power transistor MN _ PW, and generates the gate control signal driving signal SP of the second power transistor MP _ PW. The second inverter is used to generate an inverted signal NSN for controlling the turning on and off of the first normal transistor MN1 in the first pulse generating module 340.
By combining the above structures and combining fig. 3, fig. 4, and fig. 5, the operating principle of the dc/dc conversion circuit according to the embodiment of the present invention is as follows:
when the duty cycle of the dc/dc conversion circuit starts, the first power transistor MN _ PW and the second power transistor MP _ PW are both turned off, and the second comparator 320 compares the first feedback voltage VFB1And a reference voltage VREFIf the first feedback voltage V isFB1Below the reference voltage VREFThe second signal H2 output by the second comparator 320 is low indicating the first output voltage VOUT1Not yet higher than the reference voltage VREFMultiplication by the second ratio requires continuous supply of the first output voltage VOUT1And (6) charging. At this time, the logic control module 360 controls the first common transistor MN1 of the first pulse generating module 340 to be turned off, and the charging current source IBTo the upper plate V of the energy storage capacitor array 341RAMPCharging when the voltage V of the upper plate of the energy storage capacitor array 341RAMPBelow the reference voltage VREFWhen the first pulse signal TM1 output by the third comparator 342 is at a low level, and the first pulse signal TM1 is at a low level, the first power transistor MN _ PW is turned on, and the second power transistor MP _ PW is turned off. The time for the first pulse signal TM1 to remain low is about:
Figure BDA0003032034530000151
wherein, CTIs the capacitance value of the storage capacitor array 341. When the second feedback voltage V in the rectifier circuit 200FB2Well below the reference voltage VREFAt this time, the potential of the output node N1 of the operational amplifier 220 is close to zero, the third power transistor MP0 is fully turned on, and the second output voltage V is setOUT2And a first output voltage VOUT1Approximately equal. The potential of the output node N1 of the operational amplifier 220 is lower than that of the first inverter INV1Threshold value VTThe first signal H1 output by the first inverter INV1 is at high level, and represents the second output voltage VOUT2Not yet higher than the reference voltage VREFMultiplication of the first ratio requires accelerated charging to shorten the second output voltage VOUT2The dc/dc conversion circuit operates in the boost charging mode. At this time, the second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 in the energy storage capacitor array 341 are all turned on, and the capacitance of the energy storage capacitor array 341 is the maximum capacitance CTmax：
CTmax＝C1+C2+C3+C4+C5
Wherein, C1、C2、C3、C4、C5Are respectively a first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4A fifth capacitor C5The respective capacitance value. The second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 are all turned on, and the duration of the first pulse signal TM1 at a low level is longest; when the second feedback voltage V of the rectifier circuit 200FB2Close to the reference voltage VREFWhen the voltage at the output node N1 of the operational amplifier 220 rises above the threshold V of the first inverter INV1TWhen the first signal H1 output from the first inverter INV1 changes from high to low, indicating the second output voltage VOUT2After the establishment is completed, the direct current/direct current conversion circuit enters a normal charging mode without accelerating charging. At this time, the second common transistor MN2 is turned off, and the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 are turned on or off by the external digital control signal D [2:0]]Determine the capacitance C of the storage capacitor array 341TAlso controlled by an external digital control signal D [2:0]]The turn-on time of the corresponding first power transistor MN _ PW is determined by the external digital control signal D [2:0]And (6) determining.
When the voltage V of the upper plate of the energy storage capacitor array 341RAMPHigher than VREFFirst output of the third comparator 342The pulse signal TM1 changes from low level to high level, at this time, the first power transistor MN _ PW and the second power transistor MP _ PW are both turned off, and the second pulse signal TM2 output by the second pulse generating module 350 changes from high level to low level. In a period in which the second pulse signal TM2 is at a low level, if the third signal H3 output from the first comparator 330 is at a high level, it indicates VSWThe voltage is lower than the first output voltage VOUT1Cannot output the voltage V to the first power transistor MP _ PWOUT1Charging, at which time the first power transistor MN _ PW and the second power transistor MP _ PW are both kept in an OFF state to wait for VSW(ii) is increased; when the second pulse signal TM2 changes from low level to high level, if the third signal H3 is still high level, which indicates that the conduction time of the first power transistor MN _ PW is too short to cause the charging current to be too small, the dc/dc conversion circuit will enter a continuous operation mode, and turn on the first power transistor MN _ PW again with the specified conduction time until V is reached when the first power transistor MN _ PW and the second power transistor MP _ PW are both kept offSWHigher than the first output voltage VOUT1。
While the second pulse signal TM2 is at low level, if the third signal H3 changes from high level to low level, it indicates VSWThe voltage is higher than the first output voltage VOUT1At this time, the first power transistor MN _ PW is turned off, the second power transistor MP _ PW is turned on, and VSWFor the first output voltage VOUT1And charging is carried out.
During the period that the second pulse signal TM2 is at low level, if the third signal H3 changes from low level to high level, it indicates that the first output voltage V is completedOUT1Charging, at this time, the first power transistor MN _ PW and the second power transistor MP _ PW are both turned off, the logic control module 360 controls the first common transistor MN1 in the first pulse generating module 340 to be turned on, and the upper plate V of the energy storage capacitor array 341RAMPThe node voltage is reset to zero, the working cycle of the direct current/direct current conversion circuit is finished, and the next working cycle is entered.
If the second pulse signal TM2 changes from low level to high level while the third signal H3 is at low level, it indicates that the load is heavy and the normal charging mode is already in progressWhen the heavy load cannot be driven, the dc/dc conversion circuit enters a continuous operation mode to forcibly turn off the first power transistor MN _ PW and the second power transistor MP _ PW, the logic control module 360 controls the first common transistor MN1 in the first pulse generating module 340 to be turned on, and the upper plate V of the energy storage capacitor array 341 is turned onRAMPThe node voltage is reset to zero, the working cycle of the direct current/direct current conversion circuit is finished, and the next working cycle is entered.
If the DC/DC converter circuit is at the beginning of a duty cycle, the first feedback voltage V in the rectifier circuit 200FB1Higher than reference voltage VREFThe second signal H2 output by the second comparator 320 is high, indicating the first output voltage VOUT1Has been higher than the reference voltage VREFMultiplication by the second ratio without applying the first output voltage VOUT1Charging, at which time the dc/dc conversion circuit enters the sleep mode, the first power transistor MN _ PW and the second power transistor MP _ PW are both kept in the off state until the second signal H2 output by the second comparator 320 jumps from the high level to the low level. In the sleep mode, only a few components in the second comparator 320 and the rectifying circuit 200 in fig. 2 are in operation, and the rest components are all turned off, so that the current of the dc/dc converting circuit in the sleep mode is very low, and the current of the whole dc/dc converting circuit can be as low as about 5uA after testing.
Referring to fig. 6, a waveform diagram of the dc/dc conversion circuit in the embodiment of the present invention is shown. When the second output voltage VOUT2Does not rise above the reference voltage VREFWhen the voltage is multiplied by the first ratio, the DC/DC conversion circuit enters an accelerated charging mode, the conduction time of the first power transistor MN _ PW is longest, and the charging current I flowing through the inductor LLMaximum, when inductor L charges current ILWhen the voltage drops to 0, the second power transistor MP _ PW is disconnected, the next working period is entered, and the first output voltage V under the accelerated charging modeOUT1The rising speed is high; when the second output voltage VOUT2Higher than reference voltage VREFMultiplication by the first ratio, but the first output voltage VOUT1Not higher than reference voltage VREFAnd a firstWhen the two ratios are multiplied, the DC/DC conversion circuit enters a normal charging mode, the conduction time of the first power transistor MN _ PW is determined by an external digital control signal, and the charging current I flowing through the inductor LLAlso determined by an external digital control signal, when the charging current I of the inductor L isLWhen the voltage drops to 0, the second power transistor MP _ PW is switched off, the next working period is entered, and the first output voltage V is in a normal charging modeOUT1And the voltage is increased at a set rate so as to avoid large voltage ripple in a steady state due to the fact that the boosting rate is too fast. When the first output voltage VOUT1Higher than reference voltage VREFWhen the voltage is multiplied by the second ratio, the DC/DC conversion circuit enters a sleep mode, the first power transistor MN _ PW and the second power transistor MP _ PW are both disconnected, and the inductor L charges a current ILIs zero, thereby reducing the static working current until the first output voltage VOUT1Down to a reference voltage VREFWhen the product of the first ratio and the second ratio is less than or equal to the first ratio, the DC/DC conversion circuit enters the normal charge mode again.
Based on the dc/dc conversion circuit, an embodiment of the present invention further provides a dc/dc converter, where the dc/dc converter includes: a dc/dc converter circuit as claimed in any preceding claim.
In summary, in the dc/dc converting circuit according to the embodiment of the invention, the output unit receives the input voltage, outputs the first output voltage higher than the input voltage to the rectifying unit and the detection control unit, the rectifying unit performs rectification filtering on the first output voltage, reduces ripples of the first output voltage, and outputs the second output voltage with low ripples, meanwhile, the rectifying unit generates the first signal indicating whether the second output voltage is established, and transmits the first signal to the detection control unit, and the detection control unit generates the control signal after receiving the first signal and the first output voltage, so as to control the dc/dc converting circuit to operate in the accelerated charging mode, or operate in the normal charging mode, or operate in the sleep mode. When the DC/DC conversion circuit works in the accelerated charging mode, the whole circuit increases the first output voltage by the highest allowable charging current, so that the first output voltage is quickly established, namely the second output voltage is quickly established. The detection control unit can switch between an accelerated charging mode and a normal charging mode based on the first signal and the first output voltage, the charging current is large in the accelerated charging mode to shorten the output voltage establishing time, the proper output current is maintained and lower output ripples are guaranteed in the normal charging mode, the noise performance of the sensor is improved, and the power consumption of the direct current/direct current conversion circuit is extremely low in the sleep mode. The direct current/direct current conversion circuit reduces output voltage ripples, shortens the establishment time of the output voltage of the direct current/direct current converter, and has high practical value.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A dc/dc conversion circuit, comprising: the device comprises an output unit, a rectifying unit and a detection control unit;
the output unit receives an input voltage and outputs a first output voltage to the rectifying unit and the detection control unit, wherein the first output voltage is higher than the input voltage;
the rectification unit rectifies and filters the first output voltage, outputs a second output voltage, generates a first signal and transmits the first signal to the detection control unit, and the first signal represents whether the second output voltage is established or not;
the detection control unit receives the first signal and the first output voltage and generates a control signal to control the direct current/direct current conversion circuit to work in an accelerated charging mode, a normal charging mode or a sleep mode;
wherein the accelerated charging mode is: a mode of boosting the first output voltage with a highest allowable charging current;
the normal charging mode is as follows: a mode of boosting the first output voltage with a preset charging current;
the sleep mode is as follows: a mode of stopping boosting the first output voltage until the first output voltage drops below a reference voltage.
2. The circuit of claim 1, wherein the output unit comprises: an inductor, a first power transistor and a second power transistor;
the first end of the inductor receives the input voltage, and the second end of the inductor is respectively connected with the drain electrode of the first power transistor and the drain electrode of the second power transistor;
the grid electrode of the first power transistor is connected with a driving module in the detection control unit;
the source electrode of the first power transistor is grounded;
the grid electrode of the second power transistor is connected with the driving module;
the source electrode of the second power transistor is connected with the rectifying unit, and the source electrode of the second power transistor outputs the first output voltage.
3. The circuit of claim 2, wherein the rectifying unit comprises: the power amplifier comprises a third power transistor, a first resistor, a second resistor, a first inverter and an operational amplifier;
the source electrode of the third power transistor is connected with the source electrode of the second power transistor;
the grid electrode of the third power transistor is respectively connected with the output end of the operational amplifier and the input end of the first inverter;
the drain electrode of the third power transistor is connected with the first end of the first resistor, and the drain electrode of the third power transistor outputs the second output voltage;
the second end of the first resistor is connected with the first end of the second resistor and the non-inverting end of the operational amplifier;
the second end of the second resistor is grounded;
the inverting terminal of the operational amplifier receives the reference voltage;
the output end of the first phase inverter is connected with a first pulse generation module in the detection control unit, and the output end of the first phase inverter outputs the first signal.
4. The circuit of claim 3, wherein the detection control unit comprises: the circuit comprises a third resistor, a fourth resistor, a first comparator, a second pulse generation module, a logic control module and a second inverter;
the first end of the third resistor is connected with the in-phase end of the first comparator, and the first end of the third resistor receives the first output voltage;
the second end of the third resistor is respectively connected with the first end of the fourth resistor and the in-phase end of the second comparator;
a second end of the fourth resistor is grounded;
the inverting terminal of the first comparator receives the voltage of the second terminal of the inductor;
the output end of the first comparator is connected with the input end of the logic control module, the output end of the first comparator outputs a third signal, and the third signal represents the current flowing direction between the second end of the inductor and the source electrode of the second power transistor;
the inverting terminal of the second comparator receives the reference voltage;
the output end of the second comparator is connected with the input end of the logic control module, the output end of the second comparator outputs a second signal, and the second signal represents the magnitude relation between the first output voltage and the reference voltage;
the output end of the logic control module is connected with the input end of the driving module;
the output end of the driving module is respectively connected with the grid electrode of the first power transistor, the grid electrode of the second power transistor, the input end of the second inverter and the input end of the second pulse generating module, and the driving module outputs the control signal;
the output end of the second pulse generation module is connected with the logic control module;
and the output end of the second inverter is connected with the first pulse generation module.
5. The circuit of claim 4, wherein the circuit comprises: the first pulse generating module includes: the energy storage capacitor array, the first common transistor and the third comparator;
the first end of the energy storage capacitor array is respectively connected with a charging current source, the in-phase end of the third comparator and the drain electrode of the first common transistor;
the second end of the energy storage capacitor array receives the first signal and an external digital control signal;
the third end of the energy storage capacitor array is connected with the source electrode of the first common transistor and is grounded;
the grid electrode of the first common transistor is connected with the output end of the second inverter;
the inverting terminal of the third comparator receives the reference voltage;
the output end of the third comparator is connected with the logic control module, and the output end of the third comparator outputs the first pulse signal.
6. The circuit of claim 5, wherein the array of energy storage capacitors comprises: a second common transistor, a third common transistor, a fourth common transistor, a fifth common transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first or gate, a second or gate, and a third or gate;
the drain of each of the second common transistor, the third common transistor, the fourth common transistor and the fifth common transistor is respectively connected with the charging current source, the in-phase end of the third comparator, the drain of the first common transistor and the first end of the fifth capacitor;
the grid electrode of the second common transistor is respectively connected with the first input end of the first OR gate, the first input end of the second OR gate, the first input end of the third OR gate and the output end of the first reverser;
the source electrode of the second common transistor is connected with the first end of the first capacitor;
a second end of the first capacitor, a second end of the second capacitor, a second end of the third capacitor, a second end of the fourth capacitor, a second end of the fifth capacitor and a source electrode of the first common transistor are respectively connected and grounded;
the grid electrode of the third common transistor is connected with the output end of the first OR gate;
the grid of the fourth common transistor is connected with the output end of the second OR gate;
the grid of the fifth common transistor is connected with the output end of the third OR gate;
a second input end of the first OR gate receives a first digital control signal in the external digital control signals;
a second input end of the second OR gate receives a second digital control signal in the external digital control signals;
a second input of the third or-gate receives a third digital control signal of the external digital control signals.
7. The circuit of claim 4, wherein the first signal being high indicates that the second output voltage is fully established, and the first signal being low indicates that the second output voltage is not fully established;
the third signal represents the second end of the inductor for high level, and the current flowing direction between the source electrode of the second power transistor is as follows: flowing from a source of the second power transistor to a second terminal of the inductor;
the third signal represents the second end of the inductor for low level, and the current flowing direction between the source electrode of the second power transistor is as follows: flowing from a second terminal of the inductor to a source of the second power transistor;
the second signal is high level indicating that the first output voltage is higher than the reference voltage, and the second signal is low level indicating that the first output voltage is lower than the reference voltage.
8. The circuit of claim 7, wherein the criteria for completion of the second output voltage establishment is: the magnitude of the second output voltage is equal to the product of the reference voltage and a first proportion;
the standard that the second output voltage is not established is as follows: the magnitude of the second output voltage is less than the product of the reference voltage and the first proportion;
the criterion that the first output voltage is higher than the reference voltage is: the magnitude of the first output voltage is greater than the product of the reference voltage and a second proportion, wherein the second proportion is greater than the first proportion;
the criterion that the first output voltage is lower than the reference voltage is: the magnitude of the first output voltage is not greater than the product of the reference voltage and the second ratio.
9. The circuit according to claim 6, wherein when the first signal is at a high level, the second common transistor, the third common transistor, the fourth common transistor, and the fifth common transistor are all turned on, the capacitance value of the energy storage capacitor array is a preset maximum capacitance value, and a duration of the first pulse signal being kept at a low level is longest;
when the first signal is at a low level, the second common transistor is turned off, the third common transistor, the fourth common transistor and the fifth common transistor are controlled by the external digital control signal, a capacitance value of the energy storage capacitor array is determined by the external digital control signal, and a duration of the first pulse signal at the low level is determined by the external digital control signal.
10. A dc/dc converter, comprising: a circuit as claimed in any one of claims 1 to 9.
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