CN113223593B - Method for optimizing reading voltage of memory cell, controller of 3D memory and operation method thereof - Google Patents
Method for optimizing reading voltage of memory cell, controller of 3D memory and operation method thereof Download PDFInfo
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Abstract
The invention discloses a reading voltage optimization method of a memory unit, wherein the memory unit is selected from a plurality of memory units corresponding to a selected physical page; the method for optimizing the reading voltage comprises the following steps: counting the number of the memory units with the first threshold voltage to obtain a first number; counting the number of the memory cells with the second threshold voltage to obtain a second number; setting an optimal read voltage based on the first number, the second number, and the adjustment parameter; setting different adjusting parameters according to different data storage time, read interference, cross temperature and programming/erasing times; according to the reading voltage optimization method of the storage unit, the controller of the 3D memory and the operation method of the controller of the 3D memory, provided by the invention, when the optimal reading voltage is set, only limited times are needed to be read, the time delay for determining the optimal reading voltage is effectively reduced, and the adjustment parameters are set based on parameters such as read interference, programming/erasing times and the like, so that the accuracy and the reliability of products are improved.
Description
Technical Field
The present invention relates to a memory technology, and more particularly, to a method for optimizing a read voltage of a memory cell, a controller of a 3D memory, and a method for operating the same.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.
The 3D memory device is mainly used as a nonvolatile flash memory. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The reading speed is slightly slower in the NAND memory device compared to the NOR memory device, but the writing speed is fast, the erasing operation is simple, and a smaller memory cell can be realized, thereby achieving a higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.
In an exemplary 3D memory device, a plurality of memory cell strings are arranged in a two-dimensional array, each memory cell string being connected between a source line and a bit line and including a plurality of memory cells stacked in a vertical direction, and thus, the plurality of memory cell strings collectively form a plurality of memory cells arranged in a three-dimensional array. Each memory cell includes a gate conductor, a channel region, and a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sandwiched therebetween. And reading data in the selected memory cell by adopting a reading method. The memory cell string includes a plurality of memory cells sharing a channel pillar. In a read operation, a read voltage is applied to the gate conductor of a selected memory cell to read data in the memory cell, and an on voltage is applied to the gate conductor of an unselected memory cell to inhibit reading.
In actual use, threshold voltage distribution in a memory cell is shifted or widened due to the influences of read disturb (read disturb), program/erase times (P/E), cross temperature (cross temperature), data retention time (data retention), and the like, and data are still easy to have errors when read by using an initial read voltage, so that the reliability of the read data is reduced, and an optimal read voltage needs to be determined according to the state of the current 3D memory to reduce the error probability. In the prior art, in order to determine the optimal read voltage, multiple times of voltage reading and calculation are required, so that the time delay is remarkably increased, and the reading speed of the 3D memory is reduced.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a method for optimizing a read voltage of a memory cell, a controller of a 3D memory and an operating method thereof, so as to determine an optimal read voltage quickly and accurately, and effectively reduce a time delay to improve a read speed and an accuracy of the 3D memory.
According to an aspect of the present invention, there is provided a read voltage optimization method of a memory cell selected from a plurality of memory cells corresponding to a selected physical page; the method for optimizing the reading voltage comprises the following steps: counting the number of memory cells having a first threshold voltage, resulting in a first number, wherein the first threshold voltage represents a threshold voltage included in a first threshold voltage range, the first threshold voltage range being defined by a first detection voltage and a second detection voltage; counting a number of the memory cells having a second threshold voltage, resulting in a second number, wherein the second threshold voltage represents a threshold voltage included in a second threshold voltage range defined by the second detection voltage and a third detection voltage; setting an optimal read voltage based on the first number, the second number, and an adjustment parameter; wherein the adjusting parameters are set differently according to the difference of data storage time, read disturb, cross temperature and program/erase times.
Optionally, the setting an optimal read voltage based on the first number, the second number, and an adjustment parameter includes: substituting the first number, the second number and the tangent value of the adjusting parameter into a second offset calculation function to obtain an offset voltage; and obtaining an optimal read voltage based on the initial read voltage and the offset voltage.
Optionally, the method for obtaining the adjustment parameter includes: obtaining the data retention time, the read disturb, the crossover temperature, and the program/erase times that affect threshold voltage distribution; substituting the data retention time, the read disturb, the crossover temperature, and the program/erase times into a coefficient function to obtain the tuning parameters.
Optionally, the method for obtaining the tangent value of the adjusting parameter comprises: and acquiring the data storage time, the read interference, the crossing temperature and the programming/erasing times which influence the threshold voltage distribution, and substituting the data storage time, the read interference, the crossing temperature and the programming/erasing times into a weighted sum function to obtain the tangent value of the adjusting parameter.
Optionally, the method for optimizing the read voltage of the memory cell further includes an initialization stage, in which the 3D memory is tested to obtain a plurality of sets of tangent values of the adjustment parameters corresponding to the data storage time, the read disturb, the cross temperature, and the program/erase times, and the set of tangent values is substituted into the weighting sum function to perform fitting to obtain coefficients of different parameters of the weighting sum function.
Optionally, the counting the number of memory cells having the first threshold voltage, and obtaining the first number includes: applying the first detection voltage to a selected physical page, marking the memory cells with the threshold voltages smaller than the first detection voltage as a first state, and marking the memory cells with the threshold voltages larger than the first detection voltage as a second state to obtain first data; applying the second detection voltage to the selected physical page, marking the memory cells with the threshold voltages smaller than the second detection voltage as a first state, and marking the memory cells with the threshold voltages larger than the second detection voltage as a second state to obtain second data; and carrying out exclusive OR operation on the first data and the second data, and counting the number of the storage units with the operation result of bit 1 to obtain a first number.
Optionally, the counting the number of memory cells having the second threshold voltage to obtain the second number includes: applying a third detection voltage to the selected physical page, marking the memory cell with the threshold voltage smaller than the third detection voltage as a first state, and marking the memory cell with the threshold voltage larger than the third detection voltage as a second state to obtain third data; and carrying out exclusive OR operation on the second data and the third data, and counting the number of the storage units with the operation result of bit 1 to obtain a second number.
Optionally, the first threshold voltage range and the second threshold voltage range are the same or different.
According to another aspect of the present invention, there is provided an operating method of a 3D memory, including: executing a read operation; detecting a raw bit-error rate of the read operation; if the original bit error rate is larger than a preset value, optimizing the reading voltage; wherein the read voltage is optimized using the read voltage optimization method for a memory cell as described above.
According to still another aspect of the present invention, there is provided a controller for a 3D memory, for generating a control signal, controlling the memory to perform an operation corresponding to the control signal; the controller counts a number of memory cells having a first threshold voltage in a selected physical page, resulting in a first number, wherein the first threshold voltage represents a threshold voltage included in a first threshold voltage range, the first threshold voltage range being defined by a first detection voltage and a second detection voltage; the controller counts a number of the memory cells having a second threshold voltage in the selected physical page, resulting in a second number, wherein the second threshold voltage represents a threshold voltage included in a second threshold voltage range, the second threshold voltage range being defined by the second detection voltage and a third detection voltage; the controller sets an optimal read voltage of a memory block where the selected physical page is located based on a difference between the first number and the second number and an adjustment parameter; wherein the adjusting parameters are set differently according to the difference of data storage time, read disturb, cross temperature and program/erase times.
Optionally, the controller of the 3D memory includes: a memory interface providing an interface of the controller with a 3D memory to program data to or read data from the memory; and the error correction decoding circuit is used for encoding and generating encoded data based on the original data and storing the encoded data into the memory in a data writing stage, and correcting a certain number of error data bits by using an error correction code to obtain the original data in a data reading stage.
Compared with the prior art that the optimal reading voltage needs to be read and calculated for multiple times when the optimal reading voltage is obtained, the reading voltage optimization method of the storage unit, the controller of the 3D memory and the operation method of the controller of the 3D memory provided by the invention only need to read for limited times (for example, read for 3 times), the time delay of reading data or determining the optimal reading voltage is effectively reduced, and the reliability of products is improved.
Optionally, when calculating an offset voltage of the optimal read voltage relative to the initial read voltage, the first number, the second number, and the adjustment parameter are used as dependent variables, wherein the adjustment parameter is related to data retention time, read disturb, cross temperature, and program/erase times, and the adjustment parameter is calculated by comprehensively considering a plurality of parameters affecting the optimal read voltage, so that the reliability and accuracy of the adjustment parameter and the offset voltage calculation result are higher, thereby improving the reliability and accuracy of the finally obtained optimal read voltage.
Optionally, in the initialization stage, a large number of tests are performed on the 3D memory to obtain a plurality of sets of tan α values corresponding to data storage time, read disturb, cross temperature, and program/erase times, and the sets are substituted into the weighted sum function to perform linear fitting, so that values of the coefficients w0 to w4 can be obtained and stored in the configuration block. In practical application, the tangent value of the corresponding adjusting parameter alpha can be quickly obtained by calculating the weighted sum of each parameter, and the calculation time delay is further reduced on the premise of ensuring the precision.
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The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows an exemplary block diagram of a memory system;
FIG. 2 illustrates an exemplary block diagram of the controller of FIG. 1;
FIG. 3 illustrates an exemplary block diagram of the memory of FIG. 1;
FIGS. 4 and 5 respectively illustrate threshold voltage distribution diagrams for an exemplary flash memory;
FIG. 6 illustrates a method of operation of a memory of an embodiment of the present invention;
FIG. 7 illustrates a read voltage optimization method for a memory cell of an embodiment of the present invention;
FIGS. 8a to 8c illustrate a method of counting the number of memory cells in FIG. 7;
FIG. 9 is a close-up view of the normal distribution valley voltage of FIG. 8c, which is approximately linear;
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.
Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
FIG. 1 illustrates an exemplary block diagram of a memory system. The memory system 100 includes a controller 110 and a memory 120. Illustratively, the memory 120 is selected from a 3D memory device. The memory 120 receives the control signal XCON from the controller 110 and performs an operation corresponding to the control signal XCON. The memory 120 transmits the execution result XRST of the operation corresponding to the control signal XCON to the controller 110. For example, in response to the control signal XCON, the memory 120 performs a read operation, a program operation, or an erase operation, or transmits read data, information on whether programming has been completed and whether erasing has been completed, to the controller 110.
For example, the control signal XCON is selected from the read command RCMD, and the memory 120 may set the optimal read voltage Vopt and transmit the set information and the read result according to the optimal read voltage Vopt to the controller 110 as the execution result XRST, and read data stored in the memory 120 using the optimal read voltage Vopt. Alternatively, the information about the optimal read voltage Vopt may not be transmitted to the controller 110.
For example, the control signal XCON is selected from the read command RCMD, the memory 120 performs a read operation, and calculates an error rate of the present read operation under the control of the controller 119, and if the error rate is greater than a predetermined value, sets the read voltage to the optimum read voltage Vopt again.
Fig. 2 illustrates an exemplary block diagram of the controller of fig. 1. The controller 110 includes a host interface 111, a memory interface 122, a local memory 113, a buffer 114, an error correction decoding circuit 115, and a processor 116, which are connected by a bus 117.
The HOST interface 111 provides an interface with the external HOST device HOST. For example, host interface 111 may provide an interface for a Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) protocol, but the embodiment is not limited thereto. In addition to SATA and SAS protocols, HOST interface 111 also provides an interface with HOST device HOST through various interface protocols, such as Universal Serial Bus (USB), human-Machine Communication (MC), peripheral component interconnect-express (PCI-E), parallel Advanced Technology Attachment (PATA), small Computer System Interface (SCSI), enhanced small device interface (ESD), and Intelligent Drive Electronics (IDE).
In response to a request from HOST device HOST, memory interface 122 provides an interface with memory 120 to program data to memory 120 or read data from memory 120. For example, the memory interface 122 provides the memory 120 with the result that the logical block address sent from the HOST device HOST has been converted into the physical address of the page of the memory.
The local memory 113 is controlled by the controller 110 so that a request of the HOST device HOST can be processed, and data, a control module, or a control program can be loaded or stored in the local memory 113. For example, the firmware may be stored in the local memory 113. The firmware is produced as hardware when software including commands and data for operating the memory system is stored in a specific storage unit, and performs one or more processes (such as machine language processing, data transfer, list processing, floating point operation, and channel control) for a request of the HOST device HOST to perform a request of the HOST device HOST to the memory system MSYS. The firmware may control the setting of the normal read command RCMD N, the soft decision command RCMD S, and the corresponding read voltage levels.
For example, the method for optimizing the read voltage of the memory cell according to the embodiment of the present invention may be stored in the local memory 113 in the form of a control program or a control module.
In addition, the mapping table and the operating system referred to in the address mapping process may be stored or loaded in the local memory 113. The local memory 113 may be implemented as a volatile memory (such as DRAM or SRAM), or a nonvolatile memory (such as MRAM, PRAM, FRAM, or flash memory). Local memory 113 may be implemented as one or more memories of the same type or different types.
The buffer 114 may be implemented as a volatile memory (such as DRAM or SRAM).
The error correction decoding circuit 115 is used for data recovery and error correction processing, and stores encoded data generated based on encoding of original data into the memory 120 in a data writing stage, and corrects a certain number of erroneous data bits using an Error Correction Code (ECC) to obtain original data in a data reading stage. The error rate of the 3D memory can be further reduced and the product yield can be improved through the error correction decoding circuit.
The processor 116 processes the request from the HOST device HOST by controlling the operation of each component of the controller 110 and analyzing and executing a control module or control program stored or loaded in the local memory 113.
FIG. 3 illustrates an exemplary block diagram of the memory of FIG. 1. The memory 120 includes a cell array 121, a row decoder 122, a page buffer 123, an input/output buffer 124, a control circuit 125, and a voltage generator 126.
The cell array 121 may be coupled with the row decoder 122 via word lines WL0 to WLn-1 and select lines SSL and GSL. The cell array 121 may be coupled with the page buffer 123 via bit lines BL0 to BLm-1. The cell array 121 may include a plurality of NAND cell strings NCS0 to NCSm-1. The NAND cell strings NCS0 to NCSm-1 may constitute the memory block BLK1. The channel of each NAND string can be formed in either the vertical or horizontal direction.
In a program operation, a memory cell may be selected in a page unit or a unit smaller than the page unit by controlling the word lines WL0 to WLn-1 and the selection lines SSL and GSL. In a read operation, the memory cell may be selected in a page unit or a unit smaller than the page unit. The threshold voltage distribution of the memory cells used for reading may be different from that used for programming.
The row decoder 122 may select one of the memory blocks of the cell array 121 in response to an address ADD. The row decoder 122 may select one of the word lines in the selected memory block. The row decoder 122 may transfer the voltage supplied from the voltage generator 126 to the selected word line. In a program operation, the row decoder 122 may transfer a program/verify voltage to a selected word line and a low voltage to unselected word lines. In a read operation, row decoder 122 may pass a read voltage to a selected word line and pass a turn-on voltage to unselected word lines.
The page buffer 123 may be operated as a write driver in a program operation and as a sense amplifier in a read operation. In a program operation, the page buffer 123 may supply a bit line voltage corresponding to data to be programmed to the bit lines of the cell array 110. In a read operation, the page buffer 123 may read out data stored in a selected memory cell via a bit line. The page buffer 123 may latch the read data to output the read data to an external device through the input/output buffer 124.
In a program operation, the input/output buffer 124 may transfer input write data to the page buffer 123. In a read operation, the input/output buffer 124 may transfer read data supplied from the page buffer 123 to an external device. The input/output buffer 124 may transmit the input address and command to the control circuit 125 and the row decoder 122, respectively.
The control circuit 125 may control the page buffer 123 and the row decoder 122 in response to a control signal XCON transmitted from the controller 110 via the input/output buffer 124. The control circuit 125 may control the page buffer 123 and the voltage generator 126 to read out the selected memory cell in response to a read command from the memory controller 110. For example, the control circuit 125 may control the page buffer 123 and the voltage generator 126 to read out data of the selected memory cell using the optimal read voltage Vopt specified by the memory controller 110.
Under the control of the control circuit 125, the voltage generator 126 may generate a word line voltage to be supplied to the word line and a voltage to be supplied to a body (e.g., a well region) in which the memory cell is formed. The word line voltages to be supplied to the word lines may include a program voltage, a low voltage, a turn-on voltage, a read voltage, and the like. In a read/program operation, the voltage generator 126 may generate a select line voltage to be supplied to the select lines SSL and GSL. Also, the voltage generator 126 may generate a specific read voltage to be supplied to the row decoder 122 under the control of the control circuit 125.
The memory 120 may sense, latch, and output data in the selected memory cell using the optimal read voltage Vopt specified by the memory controller 110.
Fig. 4 shows a threshold voltage distribution diagram of an exemplary flash memory, with the horizontal axis representing threshold voltage and the vertical axis representing the number of memory cells. Illustratively, the memory Cell is selected from an SLC (Single-level Cell). The memory Cell may also be selected from MLC (Multi-level Cell), TLC (Triple-level Cell).
Regions f11 and f21 surrounded by broken lines in fig. 4 respectively show threshold voltage distributions before the number of charges changes. When data reading is performed on the 3D memory device, an initial read voltage Vdef is applied to each memory cell. It is apparent that the initial read voltage Vdef is greater than the threshold voltage of the memory cell corresponding to f11 and less than the threshold voltage of the memory cell corresponding to f21, so that it is assumed that the memory cell corresponding to f11 is in the P1 state and the memory cell corresponding to f21 is in the P2 state. Therefore, data in the memory cell to be read can be easily distinguished before the number of charges in each memory cell changes.
However, as the memory is used, the read disturb, the program/erase times, the data retention capability, and the cross-over temperature change, and the threshold voltage of each memory cell changes accordingly. The solid line f12 and the table f22 in fig. 4 show the threshold voltage distribution after the change in the number of charges. The f12 and f22 in fig. 4 are shifted and broadened with respect to the morphology of f11 and f21, respectively. An overlap region of the two states occurs near the initial read voltage Vdef. When the initial read voltage Vdef is applied to each memory cell to read data, the P2 state in the region 2 is mistaken for the P1 state, the P1 state in the region 1 is mistaken for the P2 state, and when the threshold voltage is equal to the initial read voltage Vdef, the number of memory cells in the two regions, which are the P1 state or the P2 state, can not be correctly judged, and the number of memory cells in the two regions, which are the P1 state or the P2 state, is added to half of the number of memory cells in which the threshold voltage is equal to Vread, so that the number of erroneous memory cells in the read operation is the number of erroneous memory cells.
The Ratio of the Error count to the read data size (Raw Bit Error Ratio, RBER) is usually counted to reflect the Error level, and the calculation formula (1) of RBER is summarized as follows:
formula (1)
Fig. 5 shows a distribution of threshold voltages of memory cells, which are selected from SLC (Single-level Cell) and MLC (Multi-level Cell) and TLC (Triple-level Cell).
In fig. 5, three reading voltages Vr1, vr2, and Vr3 are provided in addition to the initial reading voltage Vdef, and it is intuitive that when the reading voltage Vr2 is selected, the area of the shaded portion is the smallest, and the portion having the same threshold voltage as the reading voltage Vr2 is also smaller, and it is verified through calculation and experiments that when the reading voltage is Vr2, that is, when the reading voltage is located at the intersection of the P1 state and the P2 state, RBEB is the smallest, the reading voltage Vr2 is the optimal reading voltage Vopt.
FIG. 6 illustrates a method of operation of a memory of an embodiment of the present invention.
Step S10, reading operation. In response to a control signal XCON of the controller 110, the memory 120 applies an initial read voltage Vdef to the selected word line and applies a turn-on voltage to the unselected word lines to read data in the memory cells on the selected physical page.
And step S20, detecting the error rate. And detecting the original bit error rate of the read data.
And step S30, judging whether the error rate is greater than a preset value. And judging whether the original bit error rate of the data read this time is greater than a preset value, and if so, executing the step S40.
And step S40, optimizing the reading voltage. Method for optimizing read voltage fig. 7 shows, and fig. 7 shows a method for optimizing read voltage of a memory cell according to an embodiment of the present invention, which includes:
step S41: the number of memory cells having the first threshold voltage is counted. Wherein the first threshold voltage represents a threshold voltage included in a first threshold voltage range, the memory cell being a corresponding memory cell on the selected one or more physical pages.
Referring to fig. 8a, fig. 8a illustrates a method of counting the number of memory cells in fig. 7. The first threshold voltage range is defined by a first detection voltage V1 and a second detection voltage V2, the first detection voltage V1 and the second detection voltage V2 having a first voltage difference. Applying a first detection voltage V1 to the selected physical page, marking the memory cell with the threshold voltage smaller than the first detection voltage V1 as bit 1, and marking the memory cell with the threshold voltage larger than the first detection voltage V1 as bit 0 to obtain first data; applying a second detection voltage V2 to the selected physical page, marking the memory cell with the threshold voltage smaller than the second detection voltage V2 as bit 1, and marking the memory cell with the threshold voltage larger than the second detection voltage V2 as bit 0 to obtain second data; the first data and the second data are subjected to exclusive or operation, and the portion with the operation result of bit 1 indicates the number of memory cells whose threshold voltages are included in the first detection voltage V1 and the second detection voltage V2, and the number thereof is denoted as a first number Y1.
The first data and the second data may be stored in a cache, which may be included in the controller 110 or the memory 120.
Step S42: the number of memory cells having the second threshold voltage is counted. Wherein the second threshold voltage represents a threshold voltage included in a second threshold voltage range, the memory cell being a corresponding memory cell on the selected one or more physical pages.
The second threshold voltage range is defined by the second detection voltage V2 and the third detection voltage V3, and the second detection voltage V2 and the third detection voltage V3 have a second voltage difference. Applying a third detection voltage V3 to the selected physical page, marking the memory cell with the threshold voltage smaller than the third detection voltage V3 as bit 1, and marking the memory cell with the threshold voltage larger than the third detection voltage V3 as bit 0 to obtain third data; the second data and the third data are subjected to an exclusive or operation, and the portion having the operation result of 1 indicates the number of memory cells whose threshold voltages are included in the second detection voltage V2 and the third detection voltage V3, and the number thereof is denoted as a second number Y2, whereby fig. 8b is obtained.
The third data may be stored in a cache, which may be included in the controller 110 or the memory 120.
In this embodiment, the first threshold voltage range is the same as the second threshold voltage range, and optionally, the first threshold voltage range is different from the second threshold voltage range.
Step S43: and obtaining the offset voltage delta Vopt according to the first quantity Y1 obtained in the step S41, the second quantity Y2 obtained in the step S42 and the adjusting parameter.
When the threshold distribution of the memory cells is not changed, the second detection voltage V2 corresponds to the valley of the crossing in fig. 8a and 8b, and the second detection voltage V2 is the optimal read voltage Vopt, and the first number Y1 is substantially equal to the second number Y2. However, in practical use, the second sensing voltage V2 is generally equal to the initial reading voltage Vdef, and the threshold distribution of the memory cells changes with the influence of parameters such as the program/erase times and the cross-over temperature, and the optimal reading voltage Vopt is shifted from the second sensing voltage V2 by the shift voltage Δ Vopt, as shown in fig. 8 c. To obtain the optimal read voltage Vopt, the offset voltage Δ Vopt needs to be calculated, and the first offset calculation function:
ΔVopt＝g(Y1,Y2,f(DR,RDC,CT,PE))
where f (DR, RDC, CT, PE) represents a coefficient function of data retention time, read disturb, cross-over temperature, and program/erase times.
If the valley portion of the normal distribution in fig. 8c is approximated to be linear, as shown in fig. 9, the offset voltage is calculated by the second offset calculation function:
the exact value of the adjustment parameter α can be obtained by the coefficient function f (DR, RDC, CT, PE) and the parameters stored in the configuration block, and the offset voltage Δ Vopt can be obtained by substituting the above equation for calculation. In general, the longer the data storage time is, the larger the included angle is; the larger the cross temperature (i.e., the temperature difference between reading and writing) is, the larger the included angle is; the more times of read disturb, the smaller the angle, but the smaller the influence of read disturb on the angle.
However, in practical applications, the value Δ Vopt needs to be calculated quickly, i.e., the value tan α needs to be obtained quickly, so as to reduce the calculation delay. The embodiment of the invention adopts a weighting sum function to quickly calculate the value of tan alpha, namely, the value of tan alpha is quickly calculated by setting different coefficients (such as weights) for data storage time, read interference, cross temperature and programming/erasing times and summing the coefficients:
tanα＝w0+w1*DR+w2*PE+w3*CT+w4*RDC
in the embodiment of the invention, in the initialization stage, a large number of tests are performed on the 3D memory to obtain a plurality of sets of tan α values corresponding to data storage time (DR), read interference (RDC), cross Temperature (CT) and programming/erasing times (PE), the values of DR, PE, CT, RDC and tan α are substituted into a weighting sum function, linear fitting is performed to obtain values of coefficients w0 to w4, and the values are stored in a configuration block. The configuration block is selected from a memory block of the memory 120, for example, and is used to store parameters or configuration information such as data retention time, read disturb, cross temperature, and program/erase times, weighting, and coefficients of a function.
When the value of tan alpha needs to be calculated, the data storage time, the read interference, the cross temperature and the programming/erasing times are obtained from the configuration block and are substituted into the weighting sum function to quickly obtain the corresponding tan alpha value
By adopting the method of calculating the weighted sum of each parameter, the value of the adjusting parameter alpha is not required to be calculated according to each parameter and a coefficient function, and then the tangent value of the adjusting parameter alpha is solved, the corresponding tangent value of the adjusting parameter alpha can be directly calculated through simple weighted sum, and the calculation time delay is effectively reduced on the premise of ensuring the precision.
Step S44: and calculating the sum of the second detection voltage V2 and the offset voltage delta Vopt to obtain the optimal reading voltage Vopt.
Vopt＝g(Y 1 ,Y 2 ,f(DR,RDC,ΔT,PE))+V 2
After the valley bottom part of the normal distribution is approximately linear
Vopt＝ΔVopt+V 2
In fig. 9, when the offset voltage Δ Vopt is less than 0, the optimum read voltage Vopt is shifted to the left with respect to the second detection voltage V2, and when the offset voltage Δ Vopt is greater than 0, the optimum read voltage Vopt is shifted to the right with respect to the second detection voltage V2.
In summary, compared with the prior art that multiple times of reading and calculation are required when the optimal reading voltage is obtained, the reading voltage optimization method for the memory cell, the controller for the 3D memory and the operation method thereof provided by the invention only need to read for a limited number of times (for example, three times), thereby effectively reducing the time delay for reading data or determining the optimal reading voltage Vopt, and improving the reliability of products and user experience.
Optionally, when calculating the offset voltage Δ Vopt of the optimal read voltage Vopt with respect to the initial read voltage Vdef, the first number Y1, the second number Y2, and the adjustment parameter α are used as dependent variables, where the adjustment parameter is related to data saving time, read disturb, cross temperature, and program/erase times, and when calculating the adjustment parameter, a plurality of parameters affecting the optimal read voltage are taken into consideration comprehensively, and the reliability and accuracy of the calculation results of the adjustment parameter α and the offset voltage Δ Vopt are higher, so as to improve the reliability and accuracy of the finally obtained optimal read voltage Vopt.
Optionally, in the initialization stage, a large number of tests are performed on the 3D memory to obtain a plurality of sets of tan α values corresponding to data storage time, read disturb, cross temperature, and program/erase times, and the sets of tan α values are substituted into the weighting sum function to be subjected to linear fitting, so that values of the coefficients w0 to w4 can be obtained and stored in the configuration block. In practical application, the tangent value of the corresponding adjusting parameter alpha can be quickly obtained by calculating the weighted sum of each parameter, and the calculation time delay is further reduced on the premise of ensuring the precision.
It should be noted that as used herein, the words "during", "when" and "when … …" in relation to circuit operation are not strict terms referring to actions that occur immediately at the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action, and the like, as will be appreciated by those of ordinary skill in the art. The words "about" or "substantially" are used herein to mean that the element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
In accordance with embodiments of the present invention, the foregoing examples are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined with reference to the appended claims and their equivalents.
Claims (11)
1. A method of read voltage optimization for a memory cell selected from a plurality of memory cells corresponding to a selected physical page; the method for optimizing the reading voltage comprises the following steps:
counting the number of memory cells having a first threshold voltage, resulting in a first number, wherein the first threshold voltage represents a threshold voltage included in a first threshold voltage range, the first threshold voltage range being defined by a first detection voltage and a second detection voltage;
counting a number of the memory cells having a second threshold voltage, resulting in a second number, wherein the second threshold voltage represents a threshold voltage included in a second threshold voltage range defined by the second detection voltage and a third detection voltage;
setting an optimal read voltage based on the first number, the second number, and an adjustment parameter; wherein,
setting different adjusting parameters according to different data storage time, read interference, cross temperature and programming/erasing times;
and substituting the data storage time, the read interference, the crossing temperature and the programming/erasing times into a corresponding function to obtain the adjusting parameter or the tangent value of the adjusting parameter, wherein the corresponding function is selected from a coefficient function or a weighted sum function.
2. The method of claim 1, wherein setting an optimal read voltage based on the first number, the second number, and a tuning parameter comprises:
substituting the first number, the second number and the tangent value of the adjusting parameter into a second offset calculation function to obtain an offset voltage; and
an optimal read voltage is derived based on an initial read voltage and the offset voltage.
3. The method of claim 2, wherein the bringing the data retention time, the read disturb, the cross temperature, and the program/erase times into corresponding functions to obtain the tuning parameters comprises:
obtaining the data retention time, the read disturb, the crossover temperature, and the program/erase times that affect threshold voltage distribution;
substituting the data retention time, the read disturb, the crossover temperature, and the program/erase times into a coefficient function to obtain the tuning parameter.
4. The method of claim 2, wherein the fitting the data retention time, the read disturb, the cross temperature, and the program/erase times into corresponding functions to obtain the tangent value of the tuning parameter comprises:
acquiring the data retention time, the read disturb, the crossing temperature, and the program/erase times that affect a threshold voltage distribution,
and the data storage time, the read interference, the crossing temperature and the programming/erasing times are substituted into a weighted sum function to obtain the tangent value of the adjusting parameter.
5. The method of claim 4, further comprising an initialization phase during which the 3D memory is tested to obtain sets of tangent values of the conditioning parameters corresponding to the data retention time, the read disturb, the crossover temperature, and the program/erase times, and fitting the weighted sum function to obtain coefficients of different parameters of the weighted sum function.
6. The method of claim 1, wherein counting the number of memory cells having the first threshold voltage to obtain the first number comprises:
applying the first detection voltage to a selected physical page, marking the memory cells with the threshold voltages smaller than the first detection voltage as a first state, and marking the memory cells with the threshold voltages larger than the first detection voltage as a second state to obtain first data;
applying the second detection voltage to the selected physical page, marking the memory cells with the threshold voltages smaller than the second detection voltage as a first state, and marking the memory cells with the threshold voltages larger than the second detection voltage as a second state to obtain second data;
and carrying out XOR operation on the first data and the second data, and counting the number of the storage units with the operation result of bit 1 to obtain a first number.
7. The method of claim 6, wherein the counting the number of memory cells having the second threshold voltage to obtain the second number comprises:
applying a third detection voltage to the selected physical page, marking the memory cell with the threshold voltage smaller than the third detection voltage as a first state, and marking the memory cell with the threshold voltage larger than the third detection voltage as a second state to obtain third data;
and carrying out exclusive OR operation on the second data and the third data, and counting the number of the storage units with the operation result of bit 1 to obtain a second number.
8. The method of claim 1, wherein the first threshold voltage range and the second threshold voltage range are the same or different.
9. A method of operating a 3D memory, comprising:
executing a read operation;
detecting an original bit-error rate of the read operation;
if the original bit error ratio is larger than a preset value, optimizing the reading voltage; wherein,
optimizing the read voltage using the method for optimizing a read voltage of a memory cell of any one of claims 1 to 8.
10. A controller for a 3D memory, for generating a control signal, controlling the memory to perform an operation corresponding to the control signal;
the controller counts a number of memory cells having a first threshold voltage in a selected physical page, resulting in a first number, wherein the first threshold voltage represents a threshold voltage included in a first threshold voltage range, the first threshold voltage range being defined by a first detection voltage and a second detection voltage;
the controller counts a number of the memory cells having a second threshold voltage in the selected physical page, resulting in a second number, wherein the second threshold voltage represents a threshold voltage included in a second threshold voltage range, the second threshold voltage range being defined by the second detection voltage and a third detection voltage;
the controller sets an optimal read voltage of a memory block where the selected physical page is located based on a difference between the first number and the second number and an adjustment parameter; wherein,
the adjusting parameters are set according to different data storage time, read interference, cross temperature and programming/erasing times.
11. The controller of the 3D memory of claim 10, comprising:
a memory interface providing an interface of the controller with a 3D memory to program data to or read data from the memory;
and the error correction decoding circuit is used for storing encoded data generated based on original data encoding into the memory in a data writing stage and correcting a certain number of error data bits by using error correction codes to obtain the original data in a data reading stage.
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