CN113162641B - Design method of 4-channel single-bit digital receiver and receiver thereof - Google Patents
Design method of 4-channel single-bit digital receiver and receiver thereof Download PDFInfo
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Abstract
The invention discloses a design method of a 4-channel single-bit digital receiver and the receiver thereof, wherein the method comprises the following steps: carrying out single-bit sampling on the signal to obtain a single-bit digital signal, and analyzing the harmonic characteristics of the single-bit digital signal in a Nyquist sampling frequency band to obtain 4 frequency bands without target harmonic components; designing a 4-channel single-bit digital receiver model according to 4 frequency bands without target harmonic components; and carrying out simulation test according to the 4-channel single-bit digital receiver model and preset test parameters to obtain a test result. The invention can effectively avoid higher harmonics through the design of the special frequency band, can effectively improve the spurious-free dynamic range of the single-bit digital signal in each channel, is further beneficial to improving the instantaneous dynamic range of the receiver and enhancing the real-time processing capability of the receiver, and the designed 4-channel single-bit digital receiver has the advantages of simple structure, strong noise resistance, high instantaneous dynamic range and the like.
Description
Technical Field
The invention belongs to the technical field of digital receivers, and particularly relates to a design method of a 4-channel single-bit digital receiver and the receiver thereof.
Background
In order to be suitable for various complicated conditions, the modern radar signal detection requires a high-performance instantaneous frequency measurement receiver to have the advantages of low cost, small volume, ultrahigh reaction speed, large instantaneous broadband and capability of simultaneously processing a plurality of signals, and the single-bit digital receiver can replace the traditional frequency measurement receiver to a certain extent and can meet the requirements. The single-bit digital receiver has the main advantages that the hardware structure is simple, multiplication operation is not needed in calculation of Discrete Fourier Transform (DFT), broadband signals can be processed quickly, resources are saved, however, the instantaneous dynamic range of the single-bit digital receiver is far lower than that of other multi-bit digital receivers, because the strongest harmonic obtained by single-bit quantization only has a difference of 9.54dB with the input signal power in terms of power, namely the quantization signal-to-noise ratio of the single-bit digital signal is very low, and the spurious-free dynamic range (SFDR) of the single-bit digital signal is not more than 7.78dB theoretically, the harmonic generated by the single-bit strong signal can block weak signal detection, and the multi-signal instantaneous dynamic range of the single-bit digital receiver is limited.
The instantaneous dynamic range of the dual signal of the existing stable available single-bit digital receiver is only 5dB, and in order to optimize the instantaneous dynamic range of the single-bit digital receiver, the method generally adopted is to increase the number of bits of an ADC and improve the kernel function of Fourier transform. For example, "Design and Performance Evaluation of a 2.5-GSPS Digital Receiver, Chien-In Henry Chen, IEEE Transactions on Instrumentation and Measurement, 2005,54 (3)" (Design and Performance Evaluation of a 2.5-GSPS Digital Receiver, Chien-In Henry Chen, IEEE instruments and Measurement exchange, published 2005, volume 54, 3), which proposes a 2.5GHz sampling rate Digital Receiver using a combination of a 4-bit Digital-to-analog converter (ADC) and a 12-point kernel, improves the instantaneous dynamic range of the Receiver by increasing the number of ADC bits and improving the kernel of the Fourier transform, and proposes a compensation matrix method to suppress harmonics to further optimize the instantaneous dynamic range of the Receiver, but has the following disadvantages: 1) although multiplication operation in the FFT calculation process can be avoided by simplifying the number of bits of the kernel function, the receiver designed in the text still has the problem of increasing the calculation complexity and further increasing the power consumption and the calculation resources compared with a single-bit sampling digital receiver because the number of bits of the ADC is increased to 4 bits; 2) the compensation matrix method is used for inhibiting harmonic waves, so that the real-time performance of frequency measurement of the receiver designed in the text is poor, a large amount of storage resources are occupied, in addition, the requirement on frequency measurement precision is high by using the compensation matrix method, if the frequency measurement precision is improved by only increasing the FFT (fast Fourier transform) scale, the resources required to be consumed are multiplied, and the current programmable chip cannot meet the requirement; if the super-resolution estimation algorithm provided in the article is used for improving the frequency measurement accuracy, the suppression effect on harmonic waves is poor under a low signal-to-noise ratio, and even new harmonic waves can be generated; 3) the current low bit ADC sampling rate has reached several or even tens of times the 4 bit ADC sampling rate used in this document, and from 2) it is known that the compensation matrix approach used in this document is no longer applicable at high sampling rates.
Based on this, how to reliably optimize the instantaneous dynamic range of the single-bit digital receiver and ensure the frequency measurement precision and the real-time performance are still the problems to be solved at present.
Disclosure of Invention
Accordingly, the present invention is directed to a method for designing a 4-channel single-bit digital receiver and a receiver thereof, so as to solve the above-mentioned problems in the prior art.
In view of the above object, in a first aspect, the present invention provides a method for designing a 4-channel single-bit digital receiver, including:
carrying out single-bit sampling on the signal to obtain a single-bit digital signal, and analyzing the harmonic characteristics of the single-bit digital signal in a Nyquist sampling frequency band to obtain 4 frequency bands without target harmonic components;
designing a 4-channel single-bit digital receiver model according to the 4 frequency bands without the target harmonic component;
and carrying out simulation test according to the 4-channel single-bit digital receiver model and preset test parameters to obtain a test result.
Preferably, the single-bit sampling of the signal to obtain a single-bit digital signal, and analyzing the harmonic characteristics of the single-bit digital signal in the nyquist sampling frequency band to obtain 4 frequency bands without a target harmonic component, includes:
carrying out mathematical description on a single-bit analog signal, and acquiring each harmonic component of the single-bit analog signal;
sampling the single-bit analog signal to obtain a single-bit digital signal, so that each harmonic component of the single-bit analog signal is folded to a Nyquist sampling frequency band after being sampled;
obtaining a first conclusion according to the harmonic characteristics of the single-bit digital signal in the Nyquist sampling frequency band; the first conclusion means that the major harmonic component affecting the spur-free dynamic range of the single-bit digital signal is a third harmonic component;
dividing the Nyquist sampling frequency band into 4 adjacent frequency bands without the third harmonic component according to the first conclusion and the frequency relation of the third harmonic component folded into the Nyquist sampling frequency band and the input signal.
Preferably, the 4 contiguous frequency bands are:
wherein, FB1、FB2、FB3And FB4A first frequency band, a second frequency band, a third frequency band and a fourth frequency band, respectively, fsIs the sampling frequency and f is the frequency of the input signal.
Preferably, the designing a 4-channel single-bit digital receiver model according to the 4 frequency bands without the target harmonic component includes:
determining a power divider according to the number of frequency bands;
determining the frequency range of a filter bank according to 4 frequency bands without target harmonic components, and designing the filter bank according to the frequency range;
dividing sampling channels of the receiver according to the 4 filter banks so that the channel bandwidth of each sampling channel meets a frequency band requirement;
designing a signal processing module in each sampling channel according to the input data of each sampling channel; the input data of each sampling channel is a digital signal obtained after an input signal entering each sampling channel is preprocessed through a filter bank and a single-bit ADC (analog to digital converter);
designing a decision output module according to the output data of each sampling channel; the output data of each sampling channel is the processing information obtained after the preprocessed digital signal is subjected to a series of processing operations through the signal processing module;
forming a 4-channel single-bit digital receiver model according to the power divider, the 4 sampling channels and the decision output module; wherein each of the sampling channels includes the filter bank, the single-bit ADC, and the signal processing module.
Preferably, the 4-channel single-bit digital receiver model comprises a signal processing module, a spectrum analysis module for adding a hanning window, and a search module, wherein the signal processing module comprises a buffer with preset digits, and the analog frequency measurement process of the 4-channel single-bit digital receiver model comprises the following steps:
dividing an input signal entering a receiver into 4 paths of signals through the power divider and outputting the signals to the 4 sampling channels;
filtering and quantizing the input signal through the filter bank and the single-bit ADC in each sampling channel to obtain a digital signal;
carrying out caching operation and windowing DFT operation on the digital signal through the cache in each signal processing module and the spectrum analysis module of the Hanning window to obtain a spectrum signal;
after the searching module in each signal processing module carries out peak value searching on the frequency spectrum signal, processing information is obtained; the processing information comprises the frequency and peak value of the first peak spectral line and the second peak spectral line;
and deciding the processing information through the decision output module, and outputting the spurious-free dynamic range or the simulation frequency measurement result of each sampling channel.
Preferably, the deciding the processing information by the decision output module and outputting a spurious-free dynamic range or an analog frequency measurement result of each sampling channel includes:
when the input signal entering each sampling channel is a single signal with random frequency, calculating the peak ratio of the first peak spectral line to the second peak spectral line through the decision output module, and outputting the peak ratio as a spurious-free dynamic range;
when the input signal entering each sampling channel is a double signal with random frequency and adjustable power, comparing the peak value of a first peak spectral line with a preset first threshold value through the decision output module, if the peak value of the first peak spectral line is larger than the first threshold value, outputting the frequency of the first peak spectral line as an analog frequency measurement result of the first signal, and comparing the peak value of a second peak spectral line with a preset second threshold value; and if the peak value of the second peak value spectral line is larger than a second threshold value, outputting the frequency of the second peak value spectral line as an analog frequency measurement result of the second signal.
Preferably, the performing a simulation test according to the 4-channel single-bit digital receiver model and preset test parameters to obtain a test result includes:
setting a first test parameter, and carrying out a spurious-free dynamic range test based on the 4-channel single-bit digital receiver model to obtain a first test result; the first test result is used for evaluating the spurious-free dynamic range performance of the 4-channel single-bit digital receiver model; and
setting a second test parameter, and carrying out an instantaneous dynamic range test based on the 4-channel single-bit digital receiver model to obtain a second test result; the second test result is used for evaluating the dual-signal instantaneous dynamic range performance of the 4-channel single-bit digital receiver model.
In a second aspect, the present invention provides a 4-channel single-bit digital receiver, where the 4-channel single-bit digital receiver is composed of a power divider, 4 sampling channels, and a decision output module; each sampling channel consists of a filter bank meeting the frequency range requirement, a single-bit ADC and a signal processing module;
the power divider is used for dividing an input signal entering the receiver into 4 paths of signals and outputting the signals to the 4 sampling channels;
the filter bank is used for filtering an input signal and outputting the filtered input signal to the single-bit ADC;
the single-bit ADC is used for performing single-bit quantization on the filtered input signal and outputting a quantized digital signal to the signal processing module;
the signal processing module is used for performing a series of processing operations on the digital signal and outputting the obtained processing information to the decision output module;
and the decision output module is used for making a decision on the processing information and outputting a real frequency measurement result of each sampling channel.
Preferably, the channel bandwidths of the 4 sampling channels are respectively:
wherein, BWCH1、BWCH2、BWCH3And BWCH4Is a first sampling channel CH1A second sampling channel CH2A third sampling channel CH3And a fourth sampling channel CH4Channel bandwidth of fsIs the sampling frequency and f is the frequency of the input signal.
Preferably, each signal processing module consists of a buffer with preset digits, a spectrum analysis module for adding a hanning window and a search module;
the buffer with the preset digit is used for carrying out buffer operation on the digital signal;
the spectrum analysis module of the Hanning window is used for carrying out windowing DFT operation on the digital signal and outputting the obtained spectrum signal to the search module;
the searching module is used for performing peak value searching on the frequency spectrum signal and outputting processing information; the processing information comprises the frequencies and peaks of the first peak spectral line and the second peak spectral line.
According to the design method of the 4-channel single-bit digital receiver and the receiver thereof, the designed special frequency band effectively avoids the target higher harmonic component of the single-bit digital signal, the spurious-free dynamic range of the signal in each channel can be effectively improved, and the instantaneous dynamic range of the receiver and the real-time processing capability of the receiver are further improved; meanwhile, the effectiveness of the receiver in improving the spurious-free dynamic range and the instantaneous dynamic range is verified through a designed 4-channel single-bit digital receiver model, the designed receiver can be guaranteed to be feasible, and the method has the advantages of being strong in anti-noise capability, high in instantaneous dynamic range and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for designing a 4-channel single-bit digital receiver according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a step S10 of a method for designing a 4-channel single-bit digital receiver according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a step S20 of a method for designing a 4-channel single-bit digital receiver according to an embodiment of the present invention;
FIG. 4 is a flow chart of an analog frequency measurement process of a 4-channel single-bit digital receiver model according to an embodiment of the invention;
fig. 5 is a functional block diagram of a 4-channel single-bit digital receiver according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In one embodiment, as shown in fig. 1, a method for designing a 4-channel single-bit digital receiver is provided, which includes the following steps:
and step S10, performing single-bit sampling on the signal to obtain a single-bit digital signal, and analyzing the harmonic characteristics of the single-bit digital signal in the Nyquist sampling frequency band to obtain 4 frequency bands without target harmonic components.
In this embodiment, first, the frequency and power relationship between each harmonic component in the single-bit analog signal and the input signal is obtained through mathematical analysis, and the strongest harmonic component in the single-bit analog signal can be obtained; then sampling the single-bit analog signal to obtain a single-bit digital signal, and after sampling, folding the strongest harmonic component in the original single-bit analog signal to a Nyquist sampling frequency band, thereby obtaining the strongest harmonic component which affects the spurious-free dynamic range of the single-bit digital signal and marking the strongest harmonic component as a target harmonic component; and finally, obtaining the frequency relation between the target harmonic component and the input signal, and constructing 4 frequency bands without the target harmonic component by utilizing the relation, wherein the signals in the 4 frequency bands have better spurious-free dynamic ranges.
Preferably, as shown in fig. 2, step S10 includes the steps of:
step S101, performing mathematical description on the single-bit analog signal, and acquiring each harmonic component of the single-bit analog signal.
In step S101, for an analog signal that is not sampled by a single bit, the analog signal is first single-bit converted and represented by an analog square wave signal, and then fourier series expansion is performed on the analog square wave signal (i.e., the single-bit analog signal), so as to obtain coefficients of each harmonic component in the single-bit analog signal, which are specifically expressed as:
in the formula (1), akIs the amplitude coefficient of each harmonic component in Fourier series, and k is an integer. As can be seen from the formula (1), the amplitude coefficient of the even harmonic component is zero, the direct current component is large, and the direct current component can be directly filtered during processing; and the odd harmonic components of the terms may be specifically expressed as:
in the formula (2), a±1Is the amplitude coefficient of the fundamental component (first harmonic component), a±3-1/3 pi is the amplitude coefficient of the third harmonic component, a±kThe amplitude coefficient of the k-th harmonic component, the frequency of the k-th coefficient and the fundamental frequencyThe relationship is k times. The strongest harmonic component in the single-bit analog signal is a third harmonic component, and the frequency of the third harmonic component is 3 times of the frequency f of the input signal, namely the frequency of the third harmonic component is 3 f.
Step S102, sampling the single-bit analog signal to obtain a single-bit digital signal, so that each harmonic component of the single-bit analog signal is folded to a Nyquist sampling frequency band after sampling.
Step S103, obtaining a first conclusion according to the harmonic characteristics of the single-bit digital signal in the Nyquist sampling frequency band; the first conclusion is that the dominant harmonic component that affects the spurious-free dynamic range of a single-bit digital signal is the third harmonic component.
For a single-bit analog signal represented by an analog square wave signal, each odd harmonic component of the single-bit analog signal is distributed in a full frequency band, and according to a sampling principle, after the analog square wave signal is sampled, each harmonic component can be folded into a Nyquist sampling frequency band, so that a complete frequency spectrum of the single-bit digital signal is formed. Furthermore, the power of the third harmonic component is the highest among the odd harmonic components, so that the influence of the third harmonic component folded into the nyquist sampling frequency band on the spurious-free dynamic range of the single-bit digital signal is the largest, and at this time, the conclusion that the spurious-free dynamic range of the single-bit digital signal is mainly influenced is that the third harmonic component is the third harmonic component.
Step S104, according to the first conclusion and the frequency relation between the third harmonic component folded into the Nyquist sampling frequency band and the input signal, the Nyquist sampling frequency band is divided into 4 adjacent frequency bands without the target harmonic component. Wherein, the 4 adjacent frequency bands are respectively:
FB1:
FB2:
FB3:
FB4:
in the formula (3), FB1、FB2、FB3And FB4A first frequency band, a second frequency band, a third frequency band and a fourth frequency band, respectively, fsIs the sampling frequency and f is the frequency of the input signal.
The frequency relationship between the third harmonic component folded into the nyquist sampling frequency band and the input signal is specifically expressed as:
in the formula (4), f3rdIs the frequency of the third harmonic component folded into the nyquist sampling band.
That is, the frequency relationship of the third harmonic component folded to the nyquist sampling band with the input signal is obtained by formula (4), and the entire nyquist sampling band is divided into FBs according to the relationship and the first conclusion1、FB2、FB3And FB4These 4 frequency bands, FB1、FB2、FB3And FB4The 77.8% Nyquist sampling frequency band can be covered, each frequency band is adjacent, and the third harmonic component is not contained in the frequency band, so that the spurious-free dynamic range of the single-bit digital signal in the sampling channel corresponding to each frequency band can be improved.
In step S20, a 4-channel single-bit digital receiver model is designed based on the 4 frequency bands not containing the target harmonic component.
In this embodiment, the designed 4-channel single-bit digital receiver model includes a power divider, 4 independent sampling channels and a decision output module, and each sampling channel includes a filter bank, a single-bit ADC and a signal processing module designed according to 4 frequency bands without target harmonic components. Preferably, as shown in fig. 3, the step S20 includes the steps of:
step S201, determining a power divider according to the number of the frequency bands.
Step S202, determining the frequency range of the filter bank according to the 4 frequency bands without the target harmonic component, and designing the filter bank according to the frequency range.
Step S203, the sampling channels of the receiver are divided according to 4 filter banks, so that the channel bandwidth of each sampling channel meets a frequency band requirement.
Step S204, designing a signal processing module in each sampling channel according to the input data of each sampling channel; the input data of each sampling channel is a digital signal obtained after an input signal entering each sampling channel is preprocessed through a filter bank and a single-bit ADC.
Step S205, designing a decision output module according to the output data of each sampling channel; the output data of each sampling channel is processing information obtained after a series of processing operations are carried out on the preprocessed digital signals through a signal processing module.
Step S206, a 4-channel single-bit digital receiver model is formed according to the 4 sampling channels and the decision output module; each sampling channel comprises a filter bank, a single-bit ADC and a signal processing module.
Preferably, the designed 4-channel single-bit digital receiver model may include 4 independent sampling channels, and the signal processing module in each sampling channel may be composed of 3 independent modules, which are respectively a buffer of a preset number of bits, a spectrum analysis module of a hanning window covering only the channel bandwidth range, and a search module.
As shown in fig. 4, the analog frequency measurement process of the 4-channel single-bit digital receiver model designed through the above steps S201 to S206 is as follows:
step S401, the input signal entering the receiver is divided into 4 paths of signals by the power divider and sent to 4 sampling channels. Wherein the input signal may be generated by a signal generator connected to the receiver.
Step S402, filtering and quantizing the input signal through the filter bank and the single-bit ADC in each sampling channel to obtain a digital signal.
Step S403, performing a buffering operation and a windowed DFT (windowed discrete fourier transform) operation on the digital signal by using the buffer in each signal processing module and the spectrum analysis module with a hanning window to obtain a spectrum signal.
The DFT operation may be expressed as:
in the formula (5), x (n) is a digital signal,
is the kernel function (kernel function) of DFT.
The windowing operation may be represented as a dot multiplication of the discrete signal x (n) with a window function panning (n). In practical application, when the kernel function of DFT is a determined value, a windowing (n) function and the kernel function may be combined to obtain a windowed kernel function, which is specifically represented as:
further, the DFT operation and the windowing operation may be combined, and the combined DFT operation and the windowing operation (that is, the windowing DFT operation) may be expressed as a cross product operation performed on a digital signal vector and a windowed kernel function matrix, specifically expressed as:
it can be understood that when the frequency ranges processed by the 4 sampling channels are independent and non-overlapping, the DFT operation of each sampling channel is performed only by covering the frequency range of the corresponding sampling channel. The frequency spectrums corresponding to the 4 sampling channels are divided as follows:
CH1:
CH2:
CH3:
CH4:
in the formula (7), λ ═ fs/N，CH1、CH2、CH3And CH4Respectively a first sampling channel, a second sampling channel, a third sampling channel and a fourth sampling channel; n is the data length of one DFT, namely the number of spectral lines; k is any one of N spectral lines in the sampling channel. As can be seen from equation (8), the calculation amount required by the whole 4-channel single-bit digital receiver to obtain the corresponding frequency spectrums of all 4 adopted channels is only 7/18 of the complete DFT operation, that is, the frequency of 7/9 within the nyquist sampling frequency band is covered. Understandably, the windowing DFT operation is carried out on the digital signal through the spectrum analysis module of the windowing DFT, so that the calculation amount can be effectively reduced, the real-time processing capability is favorably improved, and meanwhile, the stability of the signal spectrum power can be ensured while the side lobe power can be effectively reduced through the windowing DFT operation.
Step 404, after peak searching is performed on the spectrum signal through a searching module in each signal processing module, processing information is obtained; the processing information includes the frequencies and peaks of the first peak spectral line and the second peak spectral line.
Specifically, in a search module of each sampling channel, each spectral line in a frequency spectrum signal is compared with adjacent left and right spectral lines to screen out M peak spectral lines to form a peak spectral line set; then the peak value with the maximum amplitude is selected from the peak spectral line setSpectral line, marked as first peak spectral line, and recording frequency k of first peak spectral line1And peak value v1It is then removed from the peak spectral line set; screening the peak spectral line with the maximum amplitude from the peak spectral line set with the first peak spectral line removed, marking the peak spectral line with the maximum amplitude as a second peak spectral line, and recording the frequency k of the second peak spectral line2And peak value v2. Optionally, the peak spectral lines with the largest amplitude in the peak spectral line set can be compared pairwise, and the peak value v of the first peak spectral line is screened out1Peak v greater than second peak line2。
Step S405, the decision output module makes a decision on the processing information and outputs the spurious-free dynamic range or the simulation frequency measurement result of each sampling channel.
In an aspect of this embodiment, when the input signal entering each sampling channel is a single signal with random frequency, the decision output module calculates a peak ratio α between the first peak spectral line and the second peak spectral line, and outputs the peak ratio α as the spurious-free dynamic range. Wherein, the peak ratio alpha of the first peak spectral line to the second peak spectral line is:
α＝k1/k2 (9)
in another aspect of this embodiment, when the input signal entering each sampling channel is a dual signal with random frequency and adjustable power, the decision output module outputs the peak value v of the first peak spectral line1With a predetermined first threshold value Tv1By contrast, if the peak value v of the first peak spectral line is1Greater than a first threshold value Tv1The frequency k of the first peak spectral line is then calculated1As a result of the analogue frequency measurement of the first signal, and the peak value v of the second peak spectral line2And a preset second threshold value Tv2Comparing; if the peak value v of the second peak spectral line2Greater than a second threshold value Tv2The frequency k of the second peak spectral line is then determined2And outputting the analog frequency measurement result of the second signal. Wherein, the first threshold value is used for threshold detection of the first signal, and the second threshold value is used for threshold detection of the second signal; in the input dual signalThe frequency of one signal is higher than that of the second signal, and the corresponding first signal is a strong signal and the second signal is a weak signal.
Understandably, in the whole threshold detection process, the peak value v of the first peak spectral line is firstly detected1Whether the current value is larger than a preset first threshold value Tv1If v is1＞Tv1The frequency k of the first peak spectral line is then calculated1Outputting as the analog frequency measurement result of the first signal, and determining that the threshold detection of the second signal is effective, if v is1≤Tv1Determining no signal input; further, a peak value v of the second peak spectral line is detected after the threshold detection of the second signal has been effected2Whether it is greater than the second threshold value Tv2If v is2＞Tv2The frequency k of the second peak spectral line is then determined2As a result of the analog frequency measurement of the second signal, and if v2≤Tv2Then the frequency of 0 is output as the frequency measurement result, at which time the frequency measurement error can be determined.
And step S30, carrying out simulation test according to the 4-channel single-bit digital receiver model and preset test parameters to obtain a test result.
That is, a preset simulation tool such as MATLAB can be used to perform simulation test on the designed 4-channel single-bit digital receiver model to obtain a test result. Preferably, step S30 may include a spurious free dynamic range test and a transient dynamic range test. Wherein,
testing the spurious-free dynamic range: setting a first test parameter, and carrying out a spurious-free dynamic range test based on a 4-channel single-bit digital receiver model to obtain a first test result; wherein the first test parameter includes but is not limited to the number, frequency, phase, etc. of the input signals; the first test result was used to evaluate the spur-free dynamic range performance of the 4-channel single-bit digital receiver model.
Testing the instantaneous dynamic range: setting a second test parameter, and testing the instantaneous dynamic range of the 4-channel single-bit digital receiver model to obtain a second test result; wherein the first test parameters include, but are not limited to, number, frequency, phase, power ratio, etc. of input signals; the second test result was used to evaluate the dual signal instantaneous dynamic range performance of the 4-channel single-bit digital receiver model.
Taking an example of a simulation test performed by using a 4-channel single-bit digital receiver model, the simulation test process is as follows:
1) the input signal is duplicated into 4 parts which are directly input into 4 groups of filter banks to realize the function of the power divider.
2) 4 groups of filter banks meeting the frequency range requirement are designed through an analysis tool (FDATOOL) in MATLAB, coefficients of the 4 groups of filter banks are determined, and the coefficients of the 4 groups of filter banks are convolved with 4 paths of signals output by the power divider to obtain 4 input signals adopting channels.
3) The function of a single-bit ADC in the sampling channel is realized by performing single-bit quantization on the 4 input signals by equation (10). Wherein the quantization function is:
abs(x(nΔt)＞0) (10)
in the formula (10), abs is an absolute value function; x is an input signal; n is the sampling frequency, and n is a positive integer; Δ t is the sampling interval, which is the inverse of the sampling rate.
4) The function of the spectral analysis module for applying a hanning window in the sampling channel is realized by performing a windowed DFT operation on the digital signal by equation (7).
5) Setting the functions of a decision output module, including: when a spurious-free dynamic range test is carried out, namely an input signal entering each sampling channel of the receiver is a single signal with random frequency, and the current spurious-free dynamic range of each sampling channel is output, namely the peak value ratio of a first peak value spectral line and a second peak value spectral line; when the instantaneous dynamic range test is carried out, namely, the input signal entering each sampling channel of the receiver is a double signal with random frequency and adjustable power, whether the peak value of the first peak spectral line is larger than a preset first threshold value or not is detected, if so, the frequency of the first peak spectral line is output as an analog frequency measurement result of the first signal, whether the peak value of the second peak spectral line is larger than a preset second threshold value or not is further detected, and if so, the frequency of the second peak spectral line is used as an analog frequency measurement result of the second signal.
6) When a spurious-free dynamic range test is carried out, the distribution condition of spurious-free dynamic ranges of four channels under different signal-to-noise ratios is obtained through a Monte Carlo test, wherein the frequency and the initial phase of a single signal are both generated randomly, the random frequency range of an input signal in each sampling channel is determined by the frequency range of each sampling channel, the test result is shown in table 1, and the right side in table 1 is the distribution condition of the spurious-free dynamic ranges of the traditional single-channel digital receiver.
As can be seen from table 1, compared with the conventional single-channel digital receiver, the 4-channel single-bit digital receiver of the present embodiment can effectively improve the spurious-free dynamic range of the single-bit digital signal, and has strong real-time processing capability and strong anti-noise capability.
TABLE 1 proportion of the distribution of the spurious-free dynamic range in the band at different SNR (unit:%)
7) In order to ensure that each sampling channel receives only two signals when the transient dynamic range test is carried out, 8 signals are simultaneously input and divided into 4 groups of signals, wherein the signal-to-noise ratio of each group of signals is a random quantity which is more than 5dB and comprises two signals with random frequencies and random phases, the frequencies of the two signals are randomly generated in the frequency range of each sampling channel, and the power ratio (namely the transient dynamic range) is gradually increased from 0dB to 14dB in a stepping mode of 1 dB. Under the condition that the power ratio of the two signals in a single sampling channel is fixed, experiments are carried out for a plurality of times until stable test results are obtained, and the test results are shown in table 2.
As can be seen from table 2, in the 4-channel single-bit digital receiver of the present embodiment, the detection rates of the strong signals are all 100%, the instantaneous dynamic range of the dual signals can reach 11dB, the detection rates of the weak signals in this range are all greater than 85%, and the average detection rate is greater than 95%. Therefore, the design method of the 4-channel single-bit digital receiver of the embodiment is feasible, the designed 4-channel single-bit digital receiver is simple in structure, the instantaneous dynamic range of the 4 independent sampling channels is high, and the anti-noise capability is strong.
Table 2 receiver 4 sampling channels detection probability (unit:%) under different instantaneous dynamic ranges
In summary, in the design method of the 4-channel single-bit digital receiver in this embodiment, first, the channel analyzes the harmonic features of the single-bit digital signal in the nyquist sampling frequency band to obtain 4 frequency bands without the target harmonic component, then, the 4-channel single-bit digital receiver model is designed according to the 4 frequency bands without the target harmonic component, and finally, the simulation test is performed according to the 4-channel single-bit digital receiver model and the preset test parameters to obtain the test result. In the embodiment, the designed special frequency band effectively avoids the target higher harmonic of the single-bit digital signal, so that the spurious-free dynamic range of the signal in each channel can be effectively improved, and the instantaneous dynamic range of the receiver and the real-time processing capability of the receiver are favorably improved; meanwhile, the effectiveness of the receiver in improving the spurious-free dynamic range and the instantaneous dynamic range is verified through a designed 4-channel single-bit digital receiver model, the designed receiver can be guaranteed to be feasible, and the method has the advantages of being strong in anti-noise capability, high in instantaneous dynamic range and the like.
In addition, as shown in fig. 5, an embodiment of the present invention further provides a 4-channel single-bit digital receiver, where the 4-channel single-bit digital receiver is composed of a power divider 100, 4 sampling channels 200, and a decision output module 300; each sampling channel 200 consists of a set of filter banks 201 that meet the frequency range requirements, a single bit ADC (1-bit ADC)202, and a signal processing module 203. One end of each group of filter banks 201 is connected with the power divider 100 as the input end of each sampling channel 200, and the other end is connected with one end of each signal processing module 203 through a single-bit ADC 202; the other end of each signal processing module 203 is connected to the decision output module 300 as an output of each sampling channel 200. Wherein the frequency range requirement is determined by 4 frequency bands not containing the target harmonic component.
The power divider 100 is configured to divide an input signal entering the receiver into 4 paths of signals and output the signals to 4 sampling channels 200.
A filter bank 201 for filtering an input signal and outputting the filtered input signal to a single bit ADC (1-bit ADC) 202.
The single-bit ADC202 is configured to perform single-bit quantization on the filtered input signal, and output a quantized digital signal to the signal processing module 203. The single-bit quantization is expressed as zero-crossing detection in mathematical function, i.e. the input signal is compared with a zero value, and if the input signal is greater than zero, it is '1', otherwise it is '0'.
The signal processing module 203 is configured to perform a series of processing operations on the digital signal, and output the obtained processing information to the decision output module 300.
And the decision output module 300 is configured to make a decision on the processing information and output a real frequency measurement result of each sampling channel 200.
It can be understood that each sampling channel 200 is independent, and the signal processing module 203 and the decision output module 300 in the 4 sampling channels 200 are integrated in one FPGA chip, that is, the 4 signal processing modules 203 and the decision output module 300 can be simultaneously implemented in one FPGA chip.
Further, the channel bandwidths of the 4 sampling channels are:
BWCH1:
BWCH2:
BWCH3:
BWCH4:
wherein, BWCH1、BWCH2、BWCH3And BWCH4Is a first sampling channel CH1A second sampling channel CH2A third sampling channel CH3And a fourth sampling channel CH4Channel bandwidth of fsIs the sampling frequency and f is the frequency of the input signal.
Further, as shown in fig. 5, each signal processing module 203 is composed of a buffer 401 with a preset number of bits, a spectrum analysis module 402 with a hanning window, and a search module 403. One end of the buffer 401 is used as the input end of the signal processing module 203 to connect with the single-bit ADC202, the other end is connected with one end of the search module 403 through the spectral analysis module 402 with hanning window, and the other end of the search module 403 is used as the output end of the signal processing module 203 to connect with the decision output module 300.
The buffer 401 with a preset number of bits is used for buffering the digital signal. Alternatively, the buffer 401 with a preset number of bits is a 1024-bit buffer, and can store 1024 digital signals.
A spectrum analysis module 402 for applying a window DFT operation to the digital signal, and outputting the obtained spectrum signal to the search module 403.
The searching module 403 is configured to perform peak search on the spectrum signal and output processing information, where the processing information includes frequencies and peaks of the first peak spectral line and the second peak spectral line.
Understandably, the hanning window is pre-loaded in the kernel function (kernel) of DFT to form the spectrum analysis module 402 of the hanning window, which can reduce the amount of computation and delay, and simultaneously ensure the stability of the spectrum power of the digital signal.
Further, when the processing information includes the frequency and the peak value of the peak spectral line and the second peak spectral line, the decision output module 300 includes an information collection unit and an information decision unit.
The information collection unit is used for receiving the frequency and the peak value of the first peak spectral line and the second peak spectral line output by each sampling channel.
The information decision unit is used for comparing the peak value of the first peak spectral line with a preset first threshold value when the input signal entering each sampling channel is a double signal with random frequency and adjustable power, outputting the frequency of the first peak spectral line as a real frequency measurement result of the first signal if the peak value of the first peak spectral line is larger than the first threshold value, and comparing the peak value of the second peak spectral line with a preset second threshold value; and if the peak value of the second peak value spectral line is larger than the second threshold value, outputting the frequency of the second peak value spectral line as a real frequency measurement result of the second signal.
The 4-channel single-bit digital receiver of the embodiment has the advantages of simple structure, strong anti-noise capability, high instantaneous dynamic range and the like.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. A method of designing a 4-channel single-bit digital receiver, comprising:
carrying out single-bit sampling on the signal to obtain a single-bit digital signal, and analyzing the harmonic characteristics of the single-bit digital signal in a Nyquist sampling frequency band to obtain 4 frequency bands without target harmonic components; the method comprises the following steps:
carrying out mathematical description on a single-bit analog signal, and acquiring each harmonic component of the single-bit analog signal;
sampling the single-bit analog signal to obtain a single-bit digital signal, so that each harmonic component of the single-bit analog signal is folded to a Nyquist sampling frequency band after being sampled;
obtaining a first conclusion according to the harmonic characteristics of the single-bit digital signal in the Nyquist sampling frequency band; the first conclusion means that the major harmonic component affecting the spur-free dynamic range of the single-bit digital signal is a third harmonic component;
dividing the Nyquist sampling frequency band into 4 adjacent frequency bands without third harmonic component according to the first conclusion and the frequency relation of the third harmonic component folded into the Nyquist sampling frequency band and the input signal
Designing a 4-channel single-bit digital receiver model according to 4 frequency bands without third harmonic components;
and carrying out simulation test according to the 4-channel single-bit digital receiver model and preset test parameters to obtain a test result.
2. The method of claim 1, wherein the 4 contiguous frequency bands are:
wherein, FB1、FB2、FB3And FB4A first frequency band, a second frequency band, a third frequency band and a fourth frequency band, respectively, fsIs the sampling frequency and f is the frequency of the input signal.
3. The method of designing a 4-channel single-bit digital receiver according to claim 1, wherein the designing a 4-channel single-bit digital receiver model from the 4 frequency bands not containing the target harmonic component includes:
determining a power divider according to the number of frequency bands;
determining the frequency ranges of 4 filter banks according to 4 frequency bands without target harmonic components, and designing the filter banks according to the frequency ranges;
dividing 4 sampling channels of the receiver according to the 4 filter banks so that the channel bandwidth of each sampling channel meets a frequency band requirement;
designing a signal processing module in each sampling channel according to the input data of each sampling channel; the input data of each sampling channel is a digital signal obtained after an input signal entering each sampling channel is preprocessed through a filter bank and a single-bit ADC (analog to digital converter);
designing a decision output module according to the output data of each sampling channel; the output data of each sampling channel is the processing information obtained after the preprocessed digital signal is subjected to a series of processing operations through the signal processing module;
forming a 4-channel single-bit digital receiver model according to the power divider, the 4 sampling channels and the decision output module; wherein each of the sampling channels includes the filter bank, the single-bit ADC, and the signal processing module.
4. The method as claimed in claim 3, wherein the 4-channel single-bit digital receiver model comprises a signal processing module consisting of a buffer with a preset number of bits, a spectrum analysis module with a Hanning window, and a search module, and the analog frequency measurement process of the 4-channel single-bit digital receiver model is as follows:
dividing an input signal entering a receiver into 4 paths of signals through the power divider and outputting the signals to the 4 sampling channels;
filtering and quantizing the input signal through the filter bank and the single-bit ADC in each sampling channel to obtain a digital signal;
carrying out caching operation and windowing DFT operation on the digital signal through the cache in each signal processing module and the spectrum analysis module of the Hanning window to obtain a spectrum signal;
after the searching module in each signal processing module carries out peak value searching on the frequency spectrum signal, processing information is obtained; the processing information comprises the frequency and peak value of the first peak spectral line and the second peak spectral line;
and deciding the processing information through the decision output module, and outputting the spurious-free dynamic range or the simulation frequency measurement result of each sampling channel.
5. The method of claim 4, wherein the deciding the processing information by the decision output module and outputting the spurious-free dynamic range or the analog frequency measurement result of each sampling channel comprises:
when the input signal entering each sampling channel is a single signal with random frequency, calculating the peak ratio of the first peak spectral line to the second peak spectral line through the decision output module, and outputting the peak ratio as a spurious-free dynamic range;
when the input signal entering each sampling channel is a double signal with random frequency and adjustable power, comparing the peak value of a first peak spectral line with a preset first threshold value through the decision output module, if the peak value of the first peak spectral line is larger than the first threshold value, outputting the frequency of the first peak spectral line as an analog frequency measurement result of the first signal, and comparing the peak value of a second peak spectral line with a preset second threshold value; and if the peak value of the second peak value spectral line is larger than a second threshold value, outputting the frequency of the second peak value spectral line as an analog frequency measurement result of the second signal.
6. The method for designing a 4-channel single-bit digital receiver according to claim 1, wherein the performing a simulation test according to the 4-channel single-bit digital receiver model and preset test parameters to obtain a test result comprises:
setting a first test parameter, and carrying out a spurious-free dynamic range test based on the 4-channel single-bit digital receiver model to obtain a first test result; the first test result is used for evaluating the spurious-free dynamic range performance of the 4-channel single-bit digital receiver model; and
setting a second test parameter, and carrying out an instantaneous dynamic range test based on the 4-channel single-bit digital receiver model to obtain a second test result; the second test result is used for evaluating the dual-signal instantaneous dynamic range performance of the 4-channel single-bit digital receiver model.
7. A4-channel single-bit digital receiver is characterized in that the 4-channel single-bit digital receiver consists of a power divider, 4 sampling channels and a decision output module; each sampling channel consists of a filter bank meeting the frequency range requirement, a single-bit ADC and a signal processing module; wherein, the channel bandwidths of the 4 sampling channels are respectively:
wherein, BWCH1、BWCH2、BWCH3And BWCH4Is a first sampling channel CH1A second sampling channel CH2A third sampling channel CH3And a fourth sampling channel CH4Channel bandwidth of fsIs the sampling frequency, f is the frequency of the input signal;
the power divider is used for dividing an input signal entering the receiver into 4 paths of signals and outputting the signals to the 4 sampling channels;
the filter bank is used for filtering an input signal and outputting the filtered input signal to the single-bit ADC;
the single-bit ADC is used for performing single-bit quantization on the filtered input signal and outputting a quantized digital signal to the signal processing module;
the signal processing module is used for performing a series of processing operations on the digital signal and outputting the obtained processing information to the decision output module;
and the decision output module is used for making a decision on the processing information and outputting a real frequency measurement result of each sampling channel.
8. The 4-channel single-bit digital receiver of claim 7, wherein each of the signal processing modules is composed of a buffer for a predetermined number of bits, a spectrum analysis module for adding a hanning window, and a search module;
the buffer with the preset digit is used for carrying out buffer operation on the digital signal;
the spectrum analysis module of the Hanning window is used for carrying out windowing DFT operation on the digital signal and outputting the obtained spectrum signal to the search module;
the searching module is used for performing peak value searching on the frequency spectrum signal and outputting processing information; the processing information comprises the frequencies and peaks of the first peak spectral line and the second peak spectral line.
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