CN113162616A - Ring oscillator - Google Patents
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- CN113162616A CN113162616A CN202110049960.7A CN202110049960A CN113162616A CN 113162616 A CN113162616 A CN 113162616A CN 202110049960 A CN202110049960 A CN 202110049960A CN 113162616 A CN113162616 A CN 113162616A
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- 239000000758 substrate Substances 0.000 claims abstract description 41
- 230000010355 oscillation Effects 0.000 claims abstract description 22
- 101150110971 CIN7 gene Proteins 0.000 claims description 28
- 101150110298 INV1 gene Proteins 0.000 claims description 28
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 28
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 13
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 13
- 101150070189 CIN3 gene Proteins 0.000 claims description 12
- 101100508840 Daucus carota INV3 gene Proteins 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000007613 environmental effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000003745 diagnosis Methods 0.000 description 1
- 238000003306 harvesting Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention discloses a ring oscillator, which comprises a first delay unit, a second delay unit and a buffer unit, wherein the output end of the first delay unit is connected with the input end of the second delay unit, the first output end of the second delay unit is connected with the input end of the first delay unit, the input end of the buffer unit is connected with the first output end of the second delay unit or the input end of the first delay unit, the second output end of the second delay unit is connected with the substrate end of the first delay unit, the first delay unit is used for reducing the oscillation starting voltage of the ring oscillator, the second delay unit is used for improving the oscillation starting response speed of the ring oscillator, the buffer unit is used for improving the output waveform of the ring oscillator, the input end of the first delay unit is the input end of the ring oscillator, and the output end of the buffer unit is the output end of the ring oscillator; the advantage is that it has low oscillation starting voltage, low power consumption, high oscillation frequency and high stability.
Description
Technical Field
The invention relates to an oscillator, in particular to a ring oscillator.
Background
The energy is obtained by utilizing environmental factors such as vibration, temperature difference and the like, and the energy is used as a power supply of battery-free wearable electronic equipment such as medical diagnosis and the like, so that the energy obtaining solution is attractive. Although the above solution is feasible from the energy point of view, the energy generated by environmental factors such as vibration and temperature difference is weak, and the voltage collected by the collecting circuit is also low, i.e. the input voltage of the energy collecting circuit is low, which presents a special challenge to the initial starting voltage of the energy collecting circuit.
Currently, a DC-DC converter with a higher input voltage is generally started by a low-voltage oscillator in an energy harvesting circuit, so as to increase the output voltage. The CMOS ring oscillator has the characteristics of simple structure and adjustable power consumption, and is widely applied to an energy acquisition circuit. The conventional CMOS ring oscillator is generally formed by connecting odd CMOS standard inverters end to end, but the ring oscillator for the energy acquisition circuit requires lower oscillation starting voltage (namely, can generate oscillation under the condition of low voltage of the energy acquisition circuit), has higher and stable oscillation frequency, and the conventional CMOS low-frequency oscillator generally requires higher oscillation starting voltage (namely, working voltage), has the problems of high power consumption and the like, and restricts the function realization and performance optimization of the energy acquisition circuit.
Disclosure of Invention
The invention aims to provide a ring oscillator with low oscillation starting voltage, low power consumption, high oscillation frequency and high stability.
The technical scheme adopted by the invention for solving the technical problems is as follows: a ring oscillator comprises a first delay unit, a second delay unit and a buffer unit, wherein the first delay unit is provided with an input end, a substrate end and an output end, the second delay unit is provided with an input end, a first output end and a second output end, the output end of the first delay unit is connected with the input end of the second delay unit, the first output end of the second delay unit is connected with the input end of the first delay unit, the input end of the buffer unit is connected with the first output end of the second delay unit or the input end of the first delay unit, the second output end of the second delay unit is connected with the substrate end of the first delay unit, the first delay unit is used for reducing the oscillation starting voltage of the ring oscillator, and the second delay unit is used for improving the oscillation starting response speed of the ring oscillator, the buffer unit is used for improving the output waveform of the ring oscillator, the input end of the first delay unit is the input end of the ring oscillator, and the output end of the buffer unit is the output end of the ring oscillator.
The first time delay unit comprises 5 inverters INV 1-INV 5, the second time delay unit comprises 18 inverters INV 6-INV 23, the buffer unit comprises two inverters INV24 and INV25, the 5 inverters INV 1-INV 5 are laminated inverters and are sequentially cascaded together, the 18 inverters INV 6-INV 23 are standard inverters and are sequentially cascaded together, and the two inverters INV24 and INV25 are standard inverters and are cascaded together. In the ring oscillator, the first delay unit and the second delay unit combine the laminated inverter and the standard inverter, and a multi-stage lamination technology and a self-bias technology are adopted, so that the response time of starting oscillation is further improved.
The stacked inverter INV1 includes 7 standard inverters INV1-1 to INV1-7, the standard inverter INV1-1 includes a PMOS transistor M1 and an NMOS transistor M2, the standard inverter INV1-2 includes a PMOS transistor M3 and an NMOS transistor M4, the standard inverter INV1-3 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-4 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-5 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-6 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-7 includes a PMOS transistor M1 and an NMOS transistor M1, a gate of the PMOS transistor M1 is connected to a gate of the NMOS transistor M1, a connection terminal of the PMOS transistor M1 is connected to a drain of the standard inverter INV1, a drain of the PMOS transistor M1 is connected to a drain of the standard inverter INV1, and a drain of the NMOS transistor M1 is connected to a drain of the standard inverter 1 and a drain of the PMOS transistor M1, the source electrode of the PMOS transistor M1 is a power supply end of the standard inverter INV1-1, and the source electrode of the NMOS transistor M2 is a grounding end of the standard inverter INV 1-1; the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube M4, the connection end of the PMOS tube M3 is used as the input end of the standard inverter INV1-2, the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube M4, the connection end of the PMOS tube M3 is used as the output end of the standard inverter INV1-2, the source electrode of the PMOS tube M3 is the power supply end of the standard inverter INV1-2, and the source electrode of the NMOS tube M4 is the grounding end of the standard inverter INV 1-2; the grid electrode of the PMOS tube M5 is connected with the grid electrode of the NMOS tube M6, the connection end of the PMOS tube M5 is used as the input end of the standard inverter INV1-3, the drain electrode of the PMOS tube M5 is connected with the drain electrode of the NMOS tube M6, the connection end of the PMOS tube M5 is used as the output end of the standard inverter INV1-3, the source electrode of the PMOS tube M5 is the power supply end of the standard inverter INV1-3, and the source electrode of the NMOS tube M6 is the grounding end of the standard inverter INV 1-3; the grid electrode of the PMOS tube M7 is connected with the grid electrode of the NMOS tube M8, the connection end of the PMOS tube M7 is used as the input end of the standard inverter INV1-4, the drain electrode of the PMOS tube M7 is connected with the drain electrode of the NMOS tube M8, the connection end of the PMOS tube M7 is used as the output end of the standard inverter INV1-4, the source electrode of the PMOS tube M7 is the power supply end of the standard inverter INV1-4, and the source electrode of the NMOS tube M8 is the grounding end of the standard inverter INV 1-4; the grid electrode of the PMOS tube M9 is connected with the grid electrode of the NMOS tube M10, the connection end of the PMOS tube M9 is used as the input end of the standard inverter INV1-5, the drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M10, the connection end of the PMOS tube M9 is used as the output end of the standard inverter INV1-5, the source electrode of the PMOS tube M9 is the power supply end of the standard inverter INV1-5, and the source electrode of the NMOS tube M10 is the grounding end of the standard inverter INV 1-5; the grid electrode of the PMOS tube M11 is connected with the grid electrode of the NMOS tube M12, the connection end of the PMOS tube M11 is used as the input end of the standard inverter INV1-6, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12, the connection end of the PMOS tube M11 is used as the output end of the standard inverter INV1-6, the source electrode of the PMOS tube M11 is the power supply end of the standard inverter INV1-6, and the source electrode of the NMOS tube M12 is the grounding end of the standard inverter INV 1-6; the grid of PMOS pipe M13 with the grid connection of NMOS pipe M14 and its link as the input of standard inverter INV1-7, the drain of PMOS pipe M13 with the drain connection of NMOS pipe M14 and its link as the output of standard inverter INV1-7, the source of PMOS pipe M13 be the power end of standard inverter INV1-7, the source of NMOS pipe M14 be the ground terminal of standard inverter INV1-7, the substrate of PMOS pipe M13 with the substrate connection of NMOS pipe M14 and its link as the substrate end of standard inverter INV 1-7. The power supply end of the standard inverter INV1-1, the power supply end of the standard inverter INV1-3, the power supply end of the standard inverter INV1-4 and the power supply end of the standard inverter INV1-6 are respectively connected with a power supply voltage, and the grounding end of the standard inverter INV1-1, the grounding end of the standard inverter INV1-3, the grounding end of the standard inverter INV1-4 and the grounding end of the standard inverter INV1-6 are respectively grounded; an input end of the standard inverter INV1-1, an input end of the standard inverter INV1-2, an input end of the standard inverter INV1-3, an input end of the standard inverter INV1-4, an input end of the standard inverter INV1-5, an input end of the standard inverter INV1-6 and an input end of the standard inverter INV1-7 are connected, a connecting end of the input end is the input end of the laminated inverter INV1, an output end of the standard inverter INV1-1 is connected with a power supply end of the standard inverter INV1-2, an output end of the standard inverter INV1-2 is connected with a power supply end of the standard inverter INV1-7, a grounding end of the standard inverter INV1-2 is connected with an output end of the standard inverter INV1-3, the output end of the standard inverter INV1-4 is connected with the power supply end of the standard inverter INV1-5, the output end of the standard inverter INV1-5 is connected with the grounding end of the standard inverter INV1-7, the grounding end of the standard inverter INV1-5 is connected with the output end of the standard inverter INV1-6, the output end of the standard inverter INV1-7 is the output end of the laminated inverter INV1, and the substrate end of the standard inverter INV1-7 is the substrate end of the laminated inverter INV 1; the circuit structures of the laminated inverters INV 2-INV 5 are respectively identical to the circuit structure of the laminated inverter INV1, the input end of the laminated inverter INV1 is used as the input end of the first delay unit, the output end of the laminated inverter INV1 is connected with the input end of the laminated inverter INV2, the substrate end of the laminated inverter INV1 is connected with the output end of the laminated inverter INV2, the output end of the laminated inverter INV2 is connected with the input end of the laminated inverter INV3, the substrate end of the laminated inverter INV2 is connected with the output end of the laminated inverter INV3, the output end of the laminated inverter INV3 is connected with the input end of the laminated inverter INV4, the substrate end of the laminated inverter INV3 is connected with the output end of the laminated inverter INV4, and the output end of the laminated inverter INV4 is connected with the input end of the laminated inverter INV5, the substrate end of the laminated inverter INV4 is connected to the output end of the laminated inverter INV5, the connection end of the laminated inverter INV5 is the output end of the first delay unit, and the substrate end of the laminated inverter INV5 is the substrate end of the first delay unit.
In the second delay unit, the input end of the inverter INV6 is the input end of the second delay unit, the output end of the inverter INVj is connected with the input end of the inverter INV (j +1), j is 6, 7, 8, …, 22, the output end of the inverter INV23 is the first output end of the second delay unit, and the output end of the inverter INV6 is the second output end of the second delay unit.
In the buffer unit, the input end of the inverter INV24 is the input end of the buffer unit, the output end of the inverter INV24 is connected with the input end of the inverter INV25, and the output end of the inverter INV25 is the output end of the buffer unit.
Compared with the prior art, the invention has the advantages that the ring oscillator is constructed by the first delay unit, the second delay unit and the buffer unit, the output end of the first delay unit is connected with the input end of the second delay unit, the first output end of the second delay unit is connected with the input end of the first delay unit, the input end of the buffer unit is connected with the first output end of the second delay unit or the input end of the first delay unit, the second output end of the second delay unit is connected with the substrate end of the first delay unit, the first delay unit is used for reducing the oscillation starting voltage of the ring oscillator, the second delay unit is used for improving the oscillation starting response speed of the ring oscillator, the buffer unit is used for improving the output waveform of the ring oscillator, the input end of the first delay unit is the input end of the ring oscillator, the output end of the buffer unit is the output end of the ring oscillator, therefore, the invention has simple integral structure and lower power consumption, and the annular oscillator can oscillate under extremely low power supply voltage by the cooperation of the first delay unit, the second delay unit and the buffer unit, thereby improving the response time of starting oscillation of the annular oscillator, leading the annular oscillator to have higher oscillation frequency, improving the output waveform by the buffer unit, leading the output signal phase noise of the annular oscillator to be lower, leading the reliability to be higher and leading the stability to be higher.
Drawings
FIG. 1 is a schematic block diagram of the ring oscillator configuration of the present invention;
FIG. 2 is a circuit diagram of a first delay cell of the ring oscillator of the present invention;
FIG. 3 is a circuit diagram of an inverter INV1 in a first delay cell of the ring oscillator of the present invention;
FIG. 4 is a circuit diagram of a second delay cell of the ring oscillator of the present invention;
FIG. 5 is a circuit diagram of a buffer cell of the ring oscillator of the present invention;
FIG. 6 is a waveform diagram of a transient simulation of the ring oscillator of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example (b): as shown in fig. 1, a ring oscillator includes a first delay unit, a second delay unit and a buffer unit, the first delay unit has an input end, a substrate end and an output end, the second delay unit has an input end, a first output end and a second output end, the output end of the first delay unit is connected with the input end of the second delay unit, the first output end of the second delay unit is connected with the input end of the first delay unit, the input end of the buffer unit is connected with the first output end of the second delay unit or the input end of the first delay unit, the second output end of the second delay unit is connected with the substrate end of the first delay unit, the first delay unit is used for reducing the oscillation starting voltage of the ring oscillator, the second delay unit is used for increasing the oscillation starting response speed of the ring oscillator, the buffer unit is used for improving the output waveform of the ring oscillator, the input end of the first delay unit is the input end of the ring oscillator, the output end of the buffer unit is the output end of the ring oscillator.
In this embodiment, as shown in fig. 2, 4 and 5, the first delay unit includes 5 inverters INV1 to INV5, the second delay unit includes 18 inverters INV6 to INV23, the buffer unit includes two inverters INV24 and INV25, the 5 inverters INV1 to INV5 are stacked inverters and sequentially cascaded together, the 18 inverters INV6 to INV23 are standard inverters and sequentially cascaded together, and the two inverters INV24 and INV25 are standard inverters and cascaded together.
In the present embodiment, as shown in fig. 3, the stacked inverter INV1 includes 7 standard inverters INV1-1 to INV1-7, the standard inverter INV1-1 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-2 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-3 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-4 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-5 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-6 includes a PMOS transistor M1 and an NMOS transistor M1, the standard inverter INV1-7 includes a PMOS transistor M1 and an NMOS transistor M1, the gate of the PMOS transistor M1 is connected to the gate of the NMOS transistor M1, the connection terminal of the standard inverter INV1 is used as the input terminal of the standard inverter INV1, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M1, and the standard inverter 1 is used as the source terminal of the standard inverter 1, the drain of the PMOS transistor M1 is used as the source terminal of the standard inverter 1, the source of the NMOS transistor M2 is the ground terminal of the standard inverter INV 1-1; the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube M4, the connection end of the PMOS tube M3 is used as the input end of the standard inverter INV1-2, the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube M4, the connection end of the PMOS tube M3 is used as the output end of the standard inverter INV1-2, the source electrode of the PMOS tube M3 is the power supply end of the standard inverter INV1-2, and the source electrode of the NMOS tube M4 is the grounding end of the standard inverter INV 1-2; the grid electrode of the PMOS tube M5 is connected with the grid electrode of the NMOS tube M6, the connection end of the PMOS tube M5 is used as the input end of the standard inverter INV1-3, the drain electrode of the PMOS tube M5 is connected with the drain electrode of the NMOS tube M6, the connection end of the PMOS tube M5 is used as the output end of the standard inverter INV1-3, the source electrode of the PMOS tube M5 is the power supply end of the standard inverter INV1-3, and the source electrode of the NMOS tube M6 is the grounding end of the standard inverter INV 1-3; the grid electrode of the PMOS tube M7 is connected with the grid electrode of the NMOS tube M8, the connection end of the PMOS tube M7 is used as the input end of the standard inverter INV1-4, the drain electrode of the PMOS tube M7 is connected with the drain electrode of the NMOS tube M8, the connection end of the PMOS tube M7 is used as the output end of the standard inverter INV1-4, the source electrode of the PMOS tube M7 is the power supply end of the standard inverter INV1-4, and the source electrode of the NMOS tube M8 is the grounding end of the standard inverter INV 1-4; the grid electrode of the PMOS tube M9 is connected with the grid electrode of the NMOS tube M10, the connection end of the PMOS tube M3578 is used as the input end of the standard inverter INV1-5, the drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M10, the connection end of the PMOS tube M9 is used as the output end of the standard inverter INV1-5, the source electrode of the PMOS tube M9 is the power supply end of the standard inverter INV1-5, and the source electrode of the NMOS tube M10 is the grounding end of the standard inverter INV 1-5; the grid electrode of the PMOS tube M11 is connected with the grid electrode of the NMOS tube M12, the connection end of the PMOS tube M3578 is used as the input end of the standard inverter INV1-6, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12, the connection end of the PMOS tube M11 is used as the output end of the standard inverter INV1-6, the source electrode of the PMOS tube M11 is the power supply end of the standard inverter INV1-6, and the source electrode of the NMOS tube M12 is the grounding end of the standard inverter INV 1-6; the grid of the PMOS tube M13 is connected with the grid of the NMOS tube M14, the connecting end of the PMOS tube M3578 is used as the input end of a standard inverter INV1-7, the drain of the PMOS tube M13 is connected with the drain of the NMOS tube M14, the connecting end of the PMOS tube M13 is used as the output end of the standard inverter INV1-7, the source of the PMOS tube M13 is used as the power supply end of the standard inverter INV1-7, the source of the NMOS tube M14 is used as the grounding end of the standard inverter INV1-7, the substrates of the PMOS tubes M13 and M14 are connected with the substrate end of the standard inverter INV1-7, the substrates of the PMOS tubes M1, M3, M5, M7, M9 and M11 are all connected with a power supply voltage, and the substrates of the NMOS tubes M2, M4, M6, M8, M10 and 12 are all grounded; a power supply end of the standard inverter INV1-1, a power supply end of the standard inverter INV1-3, a power supply end of the standard inverter INV1-4 and a power supply end of the standard inverter INV1-6 are respectively connected to a power supply voltage VDD, and a grounding end of the standard inverter INV1-1, a grounding end of the standard inverter INV1-3, a grounding end of the standard inverter INV1-4 and a grounding end of the standard inverter INV1-6 are respectively grounded; an input end of a standard inverter INV1-1, an input end of a standard inverter INV1-2, an input end of a standard inverter INV1-3, an input end of a standard inverter INV1-4, an input end of a standard inverter INV1-5, an input end of a standard inverter INV1-6 and an input end of a standard inverter INV1-7 are connected, a connection end of the input end is an input end of a laminated inverter INV1, an output end of the standard inverter INV1-1 is connected with a power supply end of a standard inverter INV1-2, an output end of the standard inverter INV1-2 is connected with a power supply end of the standard inverter INV1-7, a ground end of the standard inverter INV1-2 is connected with an output end of the standard inverter INV1-3, an output end of the standard inverter INV1-4 is connected with a power supply end of the standard inverter INV1-5, an output end of the standard inverter INV1-5 is connected with a ground end of the standard inverter INV1-7, the ground end of the standard inverter INV1-5 is connected with the output end of the standard inverter INV1-6, the output end of the standard inverter INV1-7 is the output end of the laminated inverter INV1, and the substrate end of the standard inverter INV1-7 is the substrate end of the laminated inverter INV 1; the circuit structures of the laminated inverters INV2 to INV5 are respectively completely the same as the circuit structure of the laminated inverter INV1, the input end of the laminated inverter INV1 is used as the input end of the first delay unit, the output end of the laminated inverter INV1 is connected with the input end of the laminated inverter INV2, the substrate end of the laminated inverter INV1 is connected with the output end of the laminated inverter INV2, the output end of the laminated inverter INV2 is connected with the input end of the laminated inverter INV3, the substrate end of the laminated inverter INV2 is connected with the output end of the laminated inverter INV3, the output end of the laminated inverter INV3 is connected with the input end of the laminated inverter INV4, the substrate end of the laminated inverter INV3 is connected with the output end of the laminated inverter INV4, the output end of the laminated inverter INV4 is connected with the input end of the laminated inverter INV5, the substrate end of the laminated inverter INV4 is connected with the output end of the laminated inverter INV5, and the connection end of the first delay unit is the output end of the first delay unit, the substrate terminal of the stacked inverter INV5 serves as the substrate terminal of the first delay cell.
In this embodiment, as shown in fig. 4, in the second delay unit, an input end of the inverter INV6 is an input end of the second delay unit, an output end of the inverter INVj is connected to an input end of the inverter INV (j +1), j is 6, 7, 8, …, 22, an output end of the inverter INV23 is a first output end of the second delay unit, and an output end of the inverter INV6 is a second output end of the second delay unit.
In this embodiment, as shown in fig. 5, in the buffer unit, an input end of the inverter INV24 is an input end of the buffer unit, an output end of the inverter INV24 is connected to an input end of the inverter INV25, and an output end of the inverter INV25 is an output end of the buffer unit.
The ring oscillator of the present invention was simulated, and the waveform diagram of the transient simulation thereof is shown in fig. 6. As can be seen from the analysis of FIG. 6, the minimum input voltage required by the ring oscillator of the present invention is 80mV, the frequency of the output voltage is 400KHz, and the waveform of the output voltage is also shaped. Therefore, the ring oscillator can oscillate under extremely low power supply voltage, has quick response time and higher oscillation frequency, and greatly improves the output waveform.
Claims (5)
1. A ring oscillator is characterized by comprising a first delay unit, a second delay unit and a buffer unit, wherein the first delay unit is provided with an input end, a substrate end and an output end, the second delay unit is provided with an input end, a first output end and a second output end, the output end of the first delay unit is connected with the input end of the second delay unit, the first output end of the second delay unit is connected with the input end of the first delay unit, the input end of the buffer unit is connected with the first output end of the second delay unit or the input end of the first delay unit, the second output end of the second delay unit is connected with the substrate end of the first delay unit, the first delay unit is used for reducing the oscillation starting voltage of the ring oscillator, and the second delay unit is used for improving the oscillation starting response speed of the ring oscillator, the buffer unit is used for improving the output waveform of the ring oscillator, the input end of the first delay unit is the input end of the ring oscillator, and the output end of the buffer unit is the output end of the ring oscillator.
2. The ring oscillator according to claim 1, wherein the first delay unit comprises 5 inverters INV 1-INV 5, the second delay unit comprises 18 inverters INV 6-INV 23, the buffer unit comprises two inverters INV24 and INV25, the 5 inverters INV 1-INV 5 are all laminated inverters and are sequentially cascaded together, the 18 inverters INV 6-INV 23 are all standard inverters and are sequentially cascaded together, and the two inverters INV24 and INV25 are both standard inverters and are cascaded together.
3. The ring oscillator according to claim 2, wherein the stacked inverter INV1 comprises 7 standard inverters INV 1-1-INV 1-7, the standard inverter INV1-1 comprises a PMOS transistor M1 and an NMOS transistor M2, the standard inverter INV1-2 comprises a PMOS transistor M3 and an NMOS transistor M4, the standard inverter INV1-3 comprises a PMOS transistor M5 and an NMOS transistor M6, the standard inverter INV1-4 comprises a PMOS transistor M7 and an NMOS transistor M8, the standard inverter INV1-5 comprises a PMOS transistor M9 and an NMOS transistor M10, the standard inverter INV1-6 comprises a PMOS transistor M11 and an NMOS transistor M12, the standard inverter INV1-7 comprises a PMOS transistor M13 and an NMOS transistor M14, the gate of the PMOS transistor M1 and the gate of the NMOS transistor M2 are connected with the connection terminal of the standard inverter INV 5391-1, the drain electrode of the PMOS transistor M1 is connected with the drain electrode of the NMOS transistor M2, the connection end of the PMOS transistor M1 is used as the output end of the standard inverter INV1-1, the source electrode of the PMOS transistor M1 is the power supply end of the standard inverter INV1-1, and the source electrode of the NMOS transistor M2 is the grounding end of the standard inverter INV 1-1; the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube M4, the connection end of the PMOS tube M3 is used as the input end of the standard inverter INV1-2, the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube M4, the connection end of the PMOS tube M3 is used as the output end of the standard inverter INV1-2, the source electrode of the PMOS tube M3 is the power supply end of the standard inverter INV1-2, and the source electrode of the NMOS tube M4 is the grounding end of the standard inverter INV 1-2; the grid electrode of the PMOS tube M5 is connected with the grid electrode of the NMOS tube M6, the connection end of the PMOS tube M5 is used as the input end of the standard inverter INV1-3, the drain electrode of the PMOS tube M5 is connected with the drain electrode of the NMOS tube M6, the connection end of the PMOS tube M5 is used as the output end of the standard inverter INV1-3, the source electrode of the PMOS tube M5 is the power supply end of the standard inverter INV1-3, and the source electrode of the NMOS tube M6 is the grounding end of the standard inverter INV 1-3; the grid electrode of the PMOS tube M7 is connected with the grid electrode of the NMOS tube M8, the connection end of the PMOS tube M7 is used as the input end of the standard inverter INV1-4, the drain electrode of the PMOS tube M7 is connected with the drain electrode of the NMOS tube M8, the connection end of the PMOS tube M7 is used as the output end of the standard inverter INV1-4, the source electrode of the PMOS tube M7 is the power supply end of the standard inverter INV1-4, and the source electrode of the NMOS tube M8 is the grounding end of the standard inverter INV 1-4; the grid electrode of the PMOS tube M9 is connected with the grid electrode of the NMOS tube M10, the connection end of the PMOS tube M9 is used as the input end of the standard inverter INV1-5, the drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M10, the connection end of the PMOS tube M9 is used as the output end of the standard inverter INV1-5, the source electrode of the PMOS tube M9 is the power supply end of the standard inverter INV1-5, and the source electrode of the NMOS tube M10 is the grounding end of the standard inverter INV 1-5; the grid electrode of the PMOS tube M11 is connected with the grid electrode of the NMOS tube M12, the connection end of the PMOS tube M11 is used as the input end of the standard inverter INV1-6, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12, the connection end of the PMOS tube M11 is used as the output end of the standard inverter INV1-6, the source electrode of the PMOS tube M11 is the power supply end of the standard inverter INV1-6, and the source electrode of the NMOS tube M12 is the grounding end of the standard inverter INV 1-6; the grid of PMOS pipe M13 with the grid of NMOS pipe M14 be connected and its link as the input of standard inverter INV1-7, the drain-source resistance of PMOS pipe M13 with the drain-source resistance of NMOS pipe M14 be connected and its link as the output of standard inverter INV1-7, the source electrode of PMOS pipe M13 be the power supply end of standard inverter INV1-7, the source electrode of NMOS pipe M14 be the ground terminal of standard inverter INV1-7, the substrate of PMOS pipe M13 with the substrate of NMOS pipe M14 be connected. The power supply end of the standard inverter INV1-1, the power supply end of the standard inverter INV1-3, the power supply end of the standard inverter INV1-4 and the power supply end of the standard inverter INV1-6 are respectively connected with a power supply voltage, and the grounding end of the standard inverter INV1-1, the grounding end of the standard inverter INV1-3, the grounding end of the standard inverter INV1-4 and the grounding end of the standard inverter INV1-6 are respectively grounded; an input end of the standard inverter INV1-1, an input end of the standard inverter INV1-2, an input end of the standard inverter INV1-3, an input end of the standard inverter INV1-4, an input end of the standard inverter INV1-5, an input end of the standard inverter INV1-6 and an input end of the standard inverter INV1-7 are connected, a connecting end of the input end is the input end of the laminated inverter INV1, an output end of the standard inverter INV1-1 is connected with a power supply end of the standard inverter INV1-2, an output end of the standard inverter INV1-2 is connected with a power supply end of the standard inverter INV1-7, a grounding end of the standard inverter INV1-2 is connected with an output end of the standard inverter INV1-3, the output end of the standard inverter INV1-4 is connected with the power supply end of the standard inverter INV1-5, the output end of the standard inverter INV1-5 is connected with the grounding end of the standard inverter INV1-7, the grounding end of the standard inverter INV1-5 is connected with the output end of the standard inverter INV1-6, the output end of the standard inverter INV1-7 is the output end of the laminated inverter INV1, and the substrate end of the standard inverter INV1-7 is the substrate end of the laminated inverter INV 1; the circuit structures of the laminated inverters INV 2-INV 5 are respectively identical to the circuit structure of the laminated inverter INV1, the input end of the laminated inverter INV1 is used as the input end of the first delay unit, the output end of the laminated inverter INV1 is connected with the input end of the laminated inverter INV2, the substrate end of the laminated inverter INV1 is connected with the output end of the laminated inverter INV2, the output end of the laminated inverter INV2 is connected with the input end of the laminated inverter INV3, the substrate end of the laminated inverter INV2 is connected with the output end of the laminated inverter INV3, the output end of the laminated inverter INV3 is connected with the input end of the laminated inverter INV4, the substrate end of the laminated inverter INV3 is connected with the output end of the laminated inverter INV4, and the output end of the laminated inverter INV4 is connected with the input end of the laminated inverter INV5, the substrate end of the laminated inverter INV4 is connected to the output end of the laminated inverter INV5, the connection end of the laminated inverter INV5 is the output end of the first delay unit, and the substrate end of the laminated inverter INV5 is the substrate end of the first delay unit.
4. The ring oscillator of claim 1, wherein in the second delay unit, the input terminal of the inverter INV6 is the input terminal of the second delay unit, the output terminal of the inverter INVj is connected to the input terminal of the inverter INV (j +1), j is 6, 7, 8, …, 22, the output terminal of the inverter INV23 is the first output terminal of the second delay unit, and the output terminal of the inverter INV6 is the second output terminal of the second delay unit.
5. The ring oscillator according to claim 2, wherein the input terminal of the inverter INV24 is the input terminal of the buffer unit, the output terminal of the inverter INV24 is connected to the input terminal of the inverter INV25, and the output terminal of the inverter INV25 is the output terminal of the buffer unit.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199278A (en) * | 1997-01-09 | 1998-11-18 | 阿苏拉布股份有限公司 | Low voltage operated oscillator |
| US6081165A (en) * | 1997-07-25 | 2000-06-27 | Texas Instruments Incorporated | Ring oscillator |
| JP2000196444A (en) * | 1998-12-25 | 2000-07-14 | Mitsubishi Electric Corp | Pll circuit and dll circuit |
| US6100768A (en) * | 1997-07-25 | 2000-08-08 | Nec Corporation | Ring oscillator generating pulse signal at constant pulse period under unstable power voltage |
| US6127898A (en) * | 1997-01-13 | 2000-10-03 | Sgs-Thomson Microelectroncs S.A. | Ring oscillator using CMOS technology |
| US20060076972A1 (en) * | 2004-10-11 | 2006-04-13 | Lsi Logic Corporation | Reliability circuit for applying an AC stress signal or DC measurement to a transistor device |
| JP2009253829A (en) * | 2008-04-09 | 2009-10-29 | Nec Electronics Corp | Oscillator circuit |
| CN102072781A (en) * | 2009-11-03 | 2011-05-25 | Arm有限公司 | Operating parameter monitor for an integrated circuit |
| US20120049964A1 (en) * | 2010-08-24 | 2012-03-01 | Zhendong Guo | Low noise cmos ring oscillator |
| CN104967446A (en) * | 2015-06-29 | 2015-10-07 | 中国科学院微电子研究所 | Ring oscillator |
| US9698763B1 (en) * | 2015-12-31 | 2017-07-04 | Globalfoundries Singapore Pte. Ltd. | Ultra low voltage ring oscillator with redundant inverter |
| CN111010151A (en) * | 2019-12-13 | 2020-04-14 | 东南大学 | Ultra-low voltage cold start oscillator delay unit based on deep well MOS (metal oxide semiconductor) tube |
| KR20200090017A (en) * | 2019-01-18 | 2020-07-28 | 한국과학기술원 | Self Startup Circuit for Boost Converter Usable in Energy Harvesting |
| US20200321862A1 (en) * | 2019-04-05 | 2020-10-08 | Oregon State University | Integrated circuit for low-voltage thermoelectric energy harvesting with self-start |
-
2021
- 2021-01-14 CN CN202110049960.7A patent/CN113162616A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199278A (en) * | 1997-01-09 | 1998-11-18 | 阿苏拉布股份有限公司 | Low voltage operated oscillator |
| US6127898A (en) * | 1997-01-13 | 2000-10-03 | Sgs-Thomson Microelectroncs S.A. | Ring oscillator using CMOS technology |
| US6081165A (en) * | 1997-07-25 | 2000-06-27 | Texas Instruments Incorporated | Ring oscillator |
| US6100768A (en) * | 1997-07-25 | 2000-08-08 | Nec Corporation | Ring oscillator generating pulse signal at constant pulse period under unstable power voltage |
| JP2000196444A (en) * | 1998-12-25 | 2000-07-14 | Mitsubishi Electric Corp | Pll circuit and dll circuit |
| US20060076972A1 (en) * | 2004-10-11 | 2006-04-13 | Lsi Logic Corporation | Reliability circuit for applying an AC stress signal or DC measurement to a transistor device |
| JP2009253829A (en) * | 2008-04-09 | 2009-10-29 | Nec Electronics Corp | Oscillator circuit |
| CN102072781A (en) * | 2009-11-03 | 2011-05-25 | Arm有限公司 | Operating parameter monitor for an integrated circuit |
| US20120049964A1 (en) * | 2010-08-24 | 2012-03-01 | Zhendong Guo | Low noise cmos ring oscillator |
| CN104967446A (en) * | 2015-06-29 | 2015-10-07 | 中国科学院微电子研究所 | Ring oscillator |
| US9698763B1 (en) * | 2015-12-31 | 2017-07-04 | Globalfoundries Singapore Pte. Ltd. | Ultra low voltage ring oscillator with redundant inverter |
| KR20200090017A (en) * | 2019-01-18 | 2020-07-28 | 한국과학기술원 | Self Startup Circuit for Boost Converter Usable in Energy Harvesting |
| US20200321862A1 (en) * | 2019-04-05 | 2020-10-08 | Oregon State University | Integrated circuit for low-voltage thermoelectric energy harvesting with self-start |
| CN111010151A (en) * | 2019-12-13 | 2020-04-14 | 东南大学 | Ultra-low voltage cold start oscillator delay unit based on deep well MOS (metal oxide semiconductor) tube |
Non-Patent Citations (3)
| Title |
|---|
| M. NISHI ET AL.: "《A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting》", 《2020 18TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)》 * |
| ZUSHUAIXIE，ZHIQIANGWU，XINLI，JIANHUIWU: "《Low voltage delay element with dynamic biasing technique for fully integrated cold-start in DC energy harvesting systems》", 《AEU - INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS》 * |
| 郭俊涛: "《高清晰多媒体接口发送器内锁相环的设计》", 《中国硕博论文》 * |
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