CN113161239A

CN113161239A - Enhanced GaN HEMT annular gate lower etching device and preparation method thereof

Info

Publication number: CN113161239A
Application number: CN202110403835.1A
Authority: CN
Inventors: 朱彦旭; 李建伟; 谭张杨; 李锜轩; 王猜; 魏昭
Original assignee: Beijing University of Technology
Current assignee: Beijing University of Technology
Priority date: 2021-04-15
Filing date: 2021-04-15
Publication date: 2021-07-23

Abstract

An enhanced GaN HEMT annular grid lower etching device belongs to the field of semiconductor microelectronics. The device is divided into 10 regions, namely a source electrode opening region, a drain electrode opening region, a grid electrode opening region, a source electrode, a groove etched at the source electrode, residual P-GaN under the grid after etching, an annular grid electrode, a groove etched at the drain electrode, a drain electrode and SiO₂And a protective layer. The device isolation etching thickness is 350nm, the structure of the traditional GaN HEMT device is improved, and the structure combining the annular grid and the source-drain etching is designed, so that the on-resistance of the device is reduced, the ohmic contact performance is improved, the breakdown characteristic of the device is improved, and the edge effect of the device is avoidedAnd breakdown occurs, improving the performance of the power type switching device.

Description

Enhanced GaN HEMT annular gate lower etching device and preparation method thereof

Technical Field

The invention relates to an enhanced GaN HEMT annular gate lower etching device and a preparation method thereof, belonging to the field of semiconductor microelectronics.

Background

Gallium nitride (GaN) materials have very superior material properties as third generation semiconductors, have a wide forbidden band width, can be made to work normally at high temperatures, and can be applied to harsh environments. Due to the dual role of spontaneous polarization and piezoelectric polarization, a non-doping generated high-concentration two-dimensional electron gas (2DEG) can be formed at the heterojunction interface of the GaN HEMT, so that the GaN HEMT has high mobility and high saturation drift velocity. In addition, GaN has a higher breakdown voltage, so that GaN devices can bear higher applied voltage under the condition of the same material length. Therefore, the characteristics of high frequency, high power density and low switching loss are very suitable for manufacturing the power type switching device.

When a power type switching device is usually operated, the characteristic on-resistance of the device is required to be low in an on state, and the breakdown voltage of the device is required to be high in an off state. Breakdown voltage V_BRAnd a characteristic on-resistance R_ONAre two important parameters of the power device.

In general, the GaN HEMT device is a depletion mode device, but a negative gate voltage must be applied to the depletion mode GaN HEMT device to turn off the device, which means that once a depletion mode GaN HEMT structure exists in a circuit, the complexity of a gate drive design is increased, misconduction easily occurs, and a through potential threat exists, so that the enhancement mode HEMT device has more advantages in practical application. In addition, the grid of the traditional HEMT device is usually a strip grid, the electric field edge effect is serious, the breakdown voltage is reduced, and the device breakdown phenomenon is easy to occur.

Disclosure of Invention

In order to solve the above problems, the present invention aims to improve the device structure and provide an enhanced GaN HEMT ring gate lower etched device and a method for manufacturing the same, which improve the breakdown voltage and on-resistance of the device.

The invention relates to an enhanced GaN HEMTAnd etching the device under the annular gate. Referring to fig. 1, when viewed from the top of the device, the device is divided into 10 regions from inside to outside, a source-side opening region 101 of the device, a deposited source electrode 102, a source-side etched groove 103, P-GaN 104 left after etching, a deposited ring-shaped gate electrode 105, a drain-side etched groove 106, a deposited drain electrode 107, grown SiO₂A passivation layer 108, a drain opening region 109, and a gate opening region 110. The cross-sectional structure of the device is shown in FIG. 2, and the structure from bottom to top is Si substrate 201, AlGaN buffer layer 202, GaN channel layer 203, AlGaN barrier layer 204, GaN cap layer 205, P-GaN layer 206, SiO₂ Protective layer 108, sputtered source electrode 102, sputtered drain electrode 107, sputtered gate electrode 105, SiO₂A passivation layer 207. The epitaxial structure is shown in fig. 3.

The invention relates to an enhanced GaN HEMT ring grid lower etching device, which comprises: GaN epitaxial growth; carrying out device isolation; growing SiO₂Protecting the active region mesa; etching and thinning the AlGaN barrier layer under the source drain region of the device structure; sputtering source drain electrode, annealing to form ohmic contact; sputtering the annular gate electrode to form a Schottky contact; growing SiO₂A passivation layer; and (6) opening holes.

Compared with the traditional GaN HEMT device, the enhanced GaN HEMT ring gate lower etching device provided by the invention has some important advantages:

1. reduce the on-resistance R_on

Compared with the traditional GaN HEMT device, the device provided by the invention etches the source and drain regions, thins the AlGaN barrier layer and does not completely etch through the AlGaN barrier layer. The electron transport mechanism of the metal alloy of the traditional GaN HEMT device and heterojunction ohmic contact is two, one is a tunneling mechanism by nitrogen vacancy, and the other is a direct contact mechanism of TiN low-resistance islands. According to the invention, after the source and drain are etched, the AlGaN layer is thinned, so that the tunneling distance is shortened, the effective barrier height between metal and a barrier is reduced, and electrons are easier to tunnel to form good ohmic contact. Secondly, after the source-drain etching, the distance between the ohmic metal region and a two-dimensional electron gas (2DEG) channel is reduced, and a large number of TiN low-resistance islands are diffused to the GaN buffer layer and connected with the 2DEG channel to form a new channel. Under the action of the dual mechanism, the electron transport efficiency of the device is improved, and the ohmic contact performance of the device is further improved.

2. The breakdown voltage V is improved_BR

The conventional GaN device is a strip-shaped gate electrode, the device is an annular gate electrode, and the edge effect of the conventional strip-shaped gate can be avoided and the breakdown voltage can be improved because the annular structure has no tail end. In addition, due to the annular structure of the annular grid, compared with a traditional strip-shaped grid device with the same size, the grid length of the annular grid is greatly increased, and higher output power can be obtained.

Drawings

FIG. 1: top view of enhanced GaN HEMT annular grid lower etching device

FIG. 2: section view of enhanced GaN HEMT annular grid lower etching device

FIG. 3: epitaxial structure of enhanced GaN HEMT annular grid lower etching device

FIG. 4: first step schematic diagram of preparation method of enhanced GaN HEMT ring grid etching device

FIG. 5: step schematic diagram II of preparation method of enhanced GaN HEMT ring grid lower etching device

FIG. 6: step three schematic diagram of preparation method of enhanced GaN HEMT ring grid etching device

FIG. 7: preparation method of enhanced GaN HEMT ring grid lower etching device, step schematic diagram of fourth

FIG. 8: preparation method of enhanced GaN HEMT ring grid lower etching device and step schematic diagram of fifth step

FIG. 9: method for preparing enhanced GaN HEMT annular grid etching device

Reference numerals: si substrate 201, AlGaN buffer layer 202, GaN channel layer 203, AlGaN barrier layer 204, GaN cap layer 205, P-GaN layer 206, SiO₂A passivation layer 207. A source opening region 101, a drain opening region 109, a gate opening region 110, a source electrode 102, a source under-etching 103, P-GaN 104 left after etching, a ring-shaped gate electrode 105, a drain under-etching 106, a drain electrode 107, SiO₂A protective layer 108.

Detailed Description

As shown in FIG. 2, the enhanced GaN HEMT ring gate down-etching device comprises a Si substrate 201, an AlGaN buffer layer 202, a GaN channel layer 203, an AlGaN barrier layer 204, a GaN cap layer 205, a P-GaN layer 206, and SiO₂Passivation layer 207, source electrode 102, drain electrode 107, gate electrode 105, SiO₂A protective layer 108; the buffer layer 202, the channel layer 203, the AlGaN barrier layer 204, the GaN cap layer 205 and the P-GaN layer 206 are sequentially stacked from bottom to top to form a P-GaN HEMT heterojunction structure; the P-GaN HEMT heterojunction structure is etched longitudinally to isolate an active region, and due to the fact that the distance between the device units is tight, two-dimensional electron gas (2-DEG) or other carriers in a channel are prone to flowing mutually, and the respective work of the device units is affected, the device units need to be isolated independently and become relatively independent bodies. Growing SiO on the isolated GaN channel 203₂The protective layer 108 is used as a protective table to prevent two-dimensional electron gas from fusing between different devices and influencing the output current of the devices; the upper parts of the P-GaN layer 206, the GaN cap layer 205 and the AlGaN barrier layer 204 of the active region are longitudinally etched and removed; a source electrode 102 and a drain electrode 107 are arranged above the AlGaN barrier layer 204; the source electrode 102 and the drain electrode 107 are in ohmic contact with the AlGaN barrier layer 204, respectively; an annular gate electrode 105 is arranged above the P-GaN layer 206; the ring-shaped gate electrode 105 forms a schottky contact with the P-GaN layer 206; the SiO₂The passivation layer 207 may be grown using Plasma Enhanced Chemical Vapor Deposition (PECVD);

as shown in fig. 3 to 9, a method for manufacturing an under-etched device of an enhanced GaN HEMT ring-shaped gate according to the present invention is provided, which comprises the following steps:

step one, manufacturing a wafer of a device: as shown in fig. 3, an AlGaN buffer layer 202, a GaN channel layer 203, an AlGaN barrier layer 204, a GaN cap layer 205, and a P-GaN layer 206 are sequentially grown on a Si substrate 201 to produce a P-GaN HEMT epitaxial structure.

Step two, cleaning the epitaxial wafer: boiling with acetone and ethanol twice, ultrasonic cleaning for 3min, washing with deionized water for 30 times, and blow-drying with nitrogen gun.

Step three, device isolation: and (3) drying the cleaned epitaxial wafer for 5min in a baking machine at 100 ℃. And then, carrying out a photoetching process, hardening after photoetching, shielding a part of the P-GaN206 area by using photoresist, then carrying out etching by using a plasma inductance coupling etching (ICP) process, and longitudinally and locally removing the upper parts of the P-GaN206, the GaN cap layer 205, the AlGaN barrier layer 204 and the GaN channel layer 203. The etching depth is 350nm, so that the etching depth is below the two-dimensional electron gas, and then the photoresist is cleaned. The schematic diagram is shown in fig. 4.

Step four, growing SiO₂Protecting the table top: cleaning the device after the plasma inductively coupled etching (ICP) process, carrying out the second photoetching, shielding the active area by photoresist, and growing 200nm SiO by using an Inductively Coupled Plasma Chemical Vapor Deposition (ICPCVD) method₂Then putting the active region into stripping liquid for stripping to form an active region SiO₂Stripping off the part of the active region to retain SiO at the channel and at the edge of the active region ₂108, here grown SiO₂The table top of the active region is protected, two-dimensional electron gas among different devices is prevented from being fused to influence the output current of the devices, and source and drain electrodes which grow subsequently are protected to prevent electrode leakage from influencing the performance of the devices. The schematic diagram is shown in fig. 5.

Fifthly, etching under the source and drain: and (3) carrying out a photoetching process on the device obtained after the third step, shielding partial area on the P-GaN206 by using photoresist, and etching by using a plasma inductively coupled etching (ICP) technology to thin the AlGaN barrier layer 204 but not etch through, wherein the residual thickness is 5 nm. The photoresist is then cleaned. The AlGaN barrier layer is etched and thinned to shorten the tunneling distance, reduce the effective barrier height between metal and the barrier and enable electrons to tunnel more easily, and Ti metal and AlGaN in a local barrier layer generate displacement reaction to form TiN when a source electrode and a drain electrode are deposited due to thinning of the barrier layer. A large number of TiN low-resistance islands are diffused to the GaN buffer layer and connected with the 2DEG channel to form a conductive channel, so that the ohmic performance is improved. The schematic diagram is shown in fig. 6.

Step six, depositing source and drain electrodes: a metal, such as Ti/Al/Ni/Au, is deposited on the AlGaN thin barrier layer 204 after etching, causing the source 102 metal and the drain 107 metal to form ohmic contacts with the AlGaN barrier layer 204. The schematic diagram is shown in fig. 7.

Step seven, growing a gate electrode: a gate metal, such as Ni/Au, is deposited on the ring-shaped P-GaN206 formed after ICP etching to form a ring-shaped gate 105 electrode, which ring-shaped gate 105 electrode forms a schottky contact with the P-GaN 206. The annular gate structure can achieve longer effective gate length under the same area of the device, and due to the annular structure, edge effect breakdown can be avoided when the device breaks down, and breakdown voltage of the device is greatly improved. The schematic diagram is shown in fig. 8.

Step eight, passivation: growing a layer of SiO on the device finished in the sixth step by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) method ₂207 passivation layer for passivation protection of the device surface, as shown schematically in fig. 9.

Step nine, hole opening: and (5) carrying out an opening process on the device to expose the source electrode 101, the drain electrode 109 and the gate electrode 110, and forming a final product. The schematic diagram is shown in fig. 2.

Claims

1. a preparation technology of an enhanced GaN HEMT ring gate etched device is characterized in that comprising the following steps:

Step 1: Manufacture the wafer of the device: on the Si substrate (201) grow an AlGaN buffer layer (202), a GaN channel layer (203), an AlGaN barrier layer (204), a GaN cap layer (205), P-GaN layer (206), generating a P-GaN HEMT epitaxial structure;

Step 2, cleaning the epitaxial wafer: soak and boil with acetone and ethanol respectively, then use ultrasonic cleaning for 3 minutes, rinse with deionized water and dry with nitrogen gun;

Step 3: Device isolation: put the cleaned epitaxial wafer into a drying machine at 100°C for 5 minutes; then perform a photolithography process. After the photolithography is completed, harden the film, and use light in part of the P-GaN (206) area. The resist is blocked, and then etched by a plasma inductively coupled etching (ICP) process, and the P-GaN (206), the GaN cap layer (205), the AlGaN barrier layer (204), and the GaN channel layer are partially removed longitudinally. (203) upper part; the etching depth is 350nm, so that the etching depth is below the two-dimensional electron gas, and then the photoresist is cleaned;

Step 4. Grow SiO ₂ to protect the mesa: clean the device after the plasma inductively coupled etching (ICP) process, perform a second photolithography, cover the active area with photoresist, and use the inductively coupled plasma chemical vapor phase 200nm SiO ₂ is grown by immersion (ICPCVD) method, then put into the stripping solution for stripping, the active region SiO ₂ is stripped off to expose the active region part, and the SiO ₂ (108) at the edge of the channel and the active region is retained;

Step 5. Perform source-drain under-etching: perform a photolithography process on the device after step 3, cover part of the upper area of the P-GaN (206) with photoresist, and then use the plasma inductively coupled etching technology to etch, The AlGaN barrier layer (204) is thinned but not cut through, and the residual thickness is 5 nm; then the photoresist is cleaned;

Step 6, depositing source and drain electrodes: depositing metal, such as Ti/Al/Ni/Au, on the AlGaN thin barrier layer (204) after etching, so that the source (102) metal and the drain (107) metal are in contact with each other. The AlGaN barrier layer (204) forms an ohmic contact;

Step 7. Grow the gate electrode: deposit gate metal, such as Ni/Au, on the annular P-GaN (206) formed after ICP etching to form the annular gate (105) electrode, which is connected to the P- GaN (206) forms Schottky contacts;

Step 8, carry out passivation: utilize plasma enhanced chemical vapor deposition method to grow a layer of SiO ₂ (207) passivation layer;

Step 9. Opening: perform an opening process on the device to expose the source electrode (101), the drain electrode (109), and the gate electrode (110) to form the final product.

2. The enhancement mode GaN HEMT ring gate etched device prepared by the method according to claim 1.