CN113156679A

CN113156679A - Spatial light modulator

Info

Publication number: CN113156679A
Application number: CN202010013972.XA
Authority: CN
Inventors: 陈皇铭; 杨宙圃
Original assignee: Siyuan Foundation Of Jiaotong University
Current assignee: Siyuan Foundation Of Jiaotong University
Priority date: 2020-01-07
Filing date: 2020-01-07
Publication date: 2021-07-23

Abstract

A spatial light modulator comprising: panel and panel driver. The panel includes an ultra-high pixel density backplane including a pixel array having at least 4000PPI and a liquid crystal layer including an ultra-high quality factor liquid crystal material having a first quality factor value. The panel driver is connected to the panel for performing a panel fast driving scheme to drive the panel.

Description

Spatial light modulator

Technical Field

The invention relates to the technical field of spatial light modulators.

Background

For the current state of the art, the spatial light modulator must satisfy the conditions of low voltage driving, low liquid crystal response speed, high electric driving frequency, etc. to achieve good phase light stability. However, with the development of technology, there is a demand for faster full-phase liquid crystal response speed and higher panel pixel density for LCOS-SLM (liquid crystal on silicon spatial light modulator) applications. In addition, the spatial light modulator in the market is driven by digital driving, and the phase light stability is much lower than that of analog driving. However, it is difficult to achieve a high driving frequency in an analog driving method for a panel with an ultra-high pixel density, so that it is difficult to suppress phase timing disturbance, and it is also difficult to achieve a high phase linearity in the case of high-speed liquid crystal response in the analog driving method compared to the digital driving method.

The present invention provides an improved spatial light modulator to solve the above problems.

Disclosure of Invention

An embodiment of the invention provides a spatial light modulator, which includes a panel and a panel driver. The panel comprises a back plate and a liquid crystal layer, wherein the back plate comprises a pixel array with pixel density of at least 4000PPI, and the liquid crystal layer comprises a liquid crystal material with a first high-quality factor value; the panel driver is electrically connected to the panel and drives the panel according to the panel fast driving design; wherein the first quality factor value meets the following condition:

wherein FoM-1 is defined as the first quality factor value, Δ n is defined as the birefringence of the liquid crystal material, γ₁Defined as the rotational viscosity coefficient (k) of the liquid crystal material₁₁Defined as the modulus of elasticity of the liquid crystal material upon expansion.

Drawings

FIG. 1 is a schematic diagram of the basic structure of a spatial light modulator according to an embodiment of the present invention;

FIG. 2 is a partial cross-sectional view of the spatial light modulator of FIG. 1 taken along line A-A';

FIG. 3 is a flow chart of the main steps of a panel fast driving scheme according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating details of steps performed by a driver according to one embodiment of the present invention;

FIG. 5 is a comparison of driving parameters for different pixel densities according to one embodiment of the present invention;

fig. 6 is a diagram of experimental test comparison of a spatial light modulator according to an embodiment of the present invention and a comparative example.

In the above drawings, the reference numerals have the following meanings:

1 spatial light modulator

20 panel

21 backboard

210 pixel array

211 pixel unit

22 reflective layer

23 first alignment layer

24 liquid crystal layer

25 second alignment layer

26 transparent electrode layer

27 glass cover plate

28 semi-reflective film

30 panel driver

32 drive logic circuit

33 memory

34 driver

S11-S12

S21-S25

Detailed Description

The following will describe the embodiments and operation principles of the image test system and the image acquisition card according to the present invention by using several embodiments. Those skilled in the art can appreciate that the features and effects of the present invention from the above-described embodiments can be combined, modified, replaced or converted based on the spirit of the present invention.

The term "coupled" as used herein includes, but is not limited to, direct coupling or indirect coupling. The term "when …", "…" as used herein means "when, before or after", and is not intended to be limiting.

As used herein, the use of ordinal numbers such as "first," "second," etc., to modify a requesting element is not by itself intended to imply any previous ordinal number with respect to the requesting element, nor the order in which a requesting element is presented with another requesting element or order in a manufacturing process, but are used merely to clearly distinguish one requesting element having a certain name from another requesting element having a same name.

When a plurality of functions (or elements) are described herein, the word "or" when used between the plurality of functions (or elements) means that the functions (or elements) may exist independently, but does not exclude the case where the plurality of functions (or elements) may exist simultaneously, that is, the word "or" includes "and" as long as the described form is reasonable.

Fig. 1 is a schematic diagram of a basic structure of a spatial light modulator 1 according to an embodiment of the present invention. As shown in fig. 1, the spatial light modulator 1 comprises a panel 20 and a panel driver 30. The panel driver 30 may be disposed on a circuit board and may include a driving logic circuit 32 and a memory 33, but is not limited thereto. The panel driver 30 may be electrically connected to the panel 20 and used to drive the panel 20. The panel 20 includes a backplane 21, and the backplane 21 includes a pixel array 210. The pixel array 210 is composed of a plurality of pixel units 211, and the pixel array 210 has a pixel density of at least 4000 inches of pixels (PPIs). For clarity of illustration, in the embodiment of fig. 1, when the spatial light modulator 1 is disposed on a first plane (XY plane) formed by a first direction (X direction) and a second direction (Y direction), the display surface of the panel 20 is parallel to the first plane and faces a third direction (Z direction or display direction).

In one embodiment, the panel 20 may be, for example, but not limited to, a Liquid Crystal On Silicon (LCOS) panel. In one embodiment, the back plate 21 may be a complementary metal-oxide-semiconductor (CMOS) substrate, that is, the pixel array 210 may be a CMOS array and the pixel unit 211 may be a CMOS unit, but in another embodiment, the back plate 21 may also be a thin-film transistor (TFT) substrate or a Printed Circuit Board (PCB), and is not limited thereto. In one embodiment, the back-plate 21 may employ a transmissive back-plate technology or a reflective back-plate technology, but is not limited thereto. In one embodiment, the driving logic circuit 32 of the panel driver 30 can be, for example, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or a custom regulator chip, and the panel driver 30 has programmable characteristics.

One of the features of the present invention is that the panel driver 30 drives the panel 20 according to a panel fast driving design. Yet another feature of the present invention is that some of the elements of the panel 20 are made of special materials.

The particular structural configuration of the panel 20 will be described in detail below. Fig. 2 is a partial cross-sectional view along a line a-a' of the spatial light modulator 1 in fig. 1, which is used to illustrate the arrangement of the detailed structure of the panel 20 in the third direction (Z direction). As shown in fig. 2, the panel 20 may include a back plate 21, a reflective layer 22, a first alignment layer 23, a liquid crystal layer 24, a second alignment layer 25, a transparent electrode (e.g., ITO) layer 26, and a glass cover 27. Viewed along the Z direction, the reflective layer 22 may be disposed on the back plate 21, the first alignment layer 23 may be disposed on the reflective layer 22, the liquid crystal layer 24 may be disposed on the first alignment layer 23, the second alignment layer 25 may be disposed on the liquid crystal layer 24, the transparent electrode layer 26 may be disposed on the second alignment layer 25, and the glass cover 27 may be disposed on the transparent electrode layer 26, but is not limited thereto.

In one embodiment, the back plate 21 is an ultra-high pixel density substrate with a pixel density of at least 4000PPI (i.e., the front plate 20 of the spatial light modulator 1 of the present invention supports a resolution of at least 1920 × 1080). In one embodiment, the reflective layer 22 can be used to reflect part of the light to improve the reflectivity of the panel 20, and the reflective layer 22 can include a metal material, such as, but not limited to, aluminum, silver, copper, chromium, or titanium. In one embodiment, the first alignment layer 23 and the second alignment layer 25 may be used to control the arrangement of liquid crystal molecules in the liquid crystal layer 24, wherein the first alignment layer 23 and the second alignment layer 25 may comprise organic materials or inorganic materials, and the first alignment layer 23 and the second alignment layer 25 may comprise a Polyimide (PI) layer or a silicon oxide layer (SiOx, x is a positive integer); the term "silicon oxide" herein includes all forms of "silicon oxide", such as silicon monoxide (SiO), silicon dioxide (SiO2), and the like, and is not limited thereto. In one embodiment, the transparent electrode layer 26 can provide conductivity or light transmittance and can be used as a display electrode of the panel 20, wherein the transparent electrode layer 26 can be, for example, an ITO layer, but is not limited thereto. In one embodiment, the glass cover 27 protects the components beneath it and serves to transmit light. In addition, in some embodiments, a semi-reflective film 28 may be further disposed on the glass cover plate 27 for allowing part of the light to pass through and part of the light to reflect; the term "semi-reflection" refers to a state where part of light is transmitted and part of light is reflected, and the reflectivity is not limited to 50%.

In particular, the liquid crystal layer 24 of the present invention is a liquid crystal material having an ultra-high Figure of Merit (FoM) value. The liquid crystal material may have a first Figure of Merit (Figure of Merit-1, FoM-1), wherein the first Figure of Merit satisfies the following condition:

wherein FoM-1 is defined as the first merit factor value, Δ n is defined as the birefringence of the liquid crystal material, γ₁Defined as the rotational viscosity coefficient (k) of the liquid crystal material₁₁Defined as the modulus of elasticity (spring elastic constant) of the liquid crystal material upon expansion.

From the first condition of high-quality factor value, the liquid crystal material is preferably a liquid crystal with high birefringence (Δ n), and the liquid crystal material has a characteristic of exhibiting a highly linear electro-optical response (EO), so that the spatial light modulator 1 of the present invention has a better phase linearity.

In one embodiment, the liquid crystal material may further have a second Figure of Merit (FoM-2) value, wherein the second Figure of Merit satisfies the following condition:

where FoM-2 is defined as the second figure of merit value and Δ ∈ is defined as the dielectric anisotropy of the liquid crystal material.

As can be seen from the satisfaction condition of the first or second high quality factor value, the super high quality factor liquid crystal used by the spatial light modulator 1 has super birefringence, and the liquid crystal gap (cell gap) between the liquid crystal molecules of the panel 20 of the present invention can be reduced compared to the prior art, so as to increase the liquid crystal response speed and suppress the fringe field effect (fringing field effect). In one embodiment, the liquid crystal gap (cell gap) between the liquid crystal molecules of the panel 20 can be between 1.48 and 2.10 μm (1.48 μm < cell gap < 2.10 μm), but is not limited thereto. Since the liquid crystal gap can be reduced, the cell gap to pixel pitch (d/p) ratio of the panel 20 can also be reduced, and thus the spatial distortion of the liquid crystal can also be reduced.

In addition, since the liquid crystal material with ultra-high quality factor also has the characteristic of making the phase linearity of the liquid crystal closer to the ideal value, the spatial light modulator 1 of the present invention can maintain good phase linearity.

Next, description will be made regarding a part of the panel rapid driving design.

First, an implementation of the panel fast driving design is explained. In one embodiment, the content of the panel driver design can be implemented by a driver 34, wherein the driver 34 can be, for example, a software, a firmware, or a parameter setting file readable by a software/hardware interface. The driver 34 can be stored in the memory 33 of the panel driver 30, and when the driver 34 is executed, the driving logic 32 can drive the panel 20 according to the content of the panel fast driving scheme. In one embodiment, the driver 34 may include a plurality of instructions that enable the driver logic 32 to drive the panel 20. In one embodiment, the driver 34 may include a plurality of subroutines. In addition, when the driver 34 is software or firmware, it can be written in various programming languages, and how its program code is written is not limited; in other words, software or firmware that can realize the fast driving design of the panel is within the protection scope of the present invention. In another embodiment, the memory 33 of the panel driver 30 is provided with a changeable parameter setting file, so that part of the parameters in the driver 34 can be modified. The present invention is not limited thereto.

The contents of the panel fast driving design will be described next. Fig. 3 is a flowchart of main steps of a panel fast driving design according to an embodiment of the present invention, and please refer to fig. 1 and fig. 2 simultaneously.

As shown in fig. 3, the driver 34 includes step S11: the panel 20 is driven under a first driving condition, wherein the first driving condition is that the Input Frame Rate (Input Frame Rate) of the panel 20 satisfies the following equation:

Input Frame Rate＝[Tclks]×Repeat，

wherein the Input Frame Rate is defined as the Input Frame update Rate, which can correspond to an actual display period of the same Frame; tclks is defined as an addressing frequency (addressing frequency) or addressing time (addressing time) of a single frame, which may correspond to a driving period of the single frame; repeat is defined as the number of repeated driving of the single frame during the actual display period of the frame.

By the first driving condition, the panel 20 will repeatedly display the same single frame during the actual display period of the frame, i.e. the driving voltage of the single frame is repeatedly applied, so that the brightness of the frame can maintain a certain stability, and further the flicker (fliker) problem caused by the decrease of the driving voltage with time can be reduced, so that the phase light stability is maintained.

In addition, in order to make the first driving condition be executed smoothly, the driving program 34 also includes step S12: making the panel 20 execute a second driving condition, wherein the second driving condition is to make the addressing time of the panel 20 satisfy the following equation:

wherein the mclkperrow parameter is defined as a memory clock number (memory clocks) allocated to each row of the pixel array 210, the mclkfreq parameter is defined as a memory clock frequency (memory clocks frequency), the swp parameter is defined as a division number of all rows of the pixel array 210 (for example, all rows of the pixel array 210 will be divided into several parts), and the twgt parameter is defined as a data input weight value corresponding to an allocation situation when an image data is input to the pixel array. In addition to this, the present invention is,

may be regarded as a reading unit time of the memory corresponding to a column of pixels in the pixel array 210;

the unit time of reading the memory corresponding to one screen (screen), for example, the unit time of reading the memory before receiving image data in one frame range (i.e., the whole pixel array 210);

which may be considered a frame-wide driving time (including the process of receiving image data), where the parameter twgt is a digital addressing sequence that represents portions of image data taken from respective portions of the pixel array 210 that are divided.

In one embodiment, the pixel rows of the pixel array 210 can be divided equally, but can also be divided according to a predetermined ratio. In one embodiment, the content of the parameter twgt or how the pixel rows are divided can be designed by a sequence of bit plane driving syntax "LSB (least significant bit), binary counted bit) -STH (local thermal meter) -THM (thermal meter, linear counting) -WTB (write to black)", but is not limited thereto. For details of the sequential bit plane driving syntax, reference may be made to "r.lo, e.l.hudson, m.stock, s.y.hong, and d.c.mcdonald," System and method for pulse-width modulation a phase-only spatial light modulator, "U.S. patent,9918053 (hereinafter referred to as" document one "), which will not be described in detail herein.

It should be noted that the execution sequence of the steps S11 and S12 is only an example, and in fact, the execution sequence of the steps S11 and S12 can be changed or executed simultaneously.

Next, description will be made regarding an actual execution process of the driver 34. Fig. 4 is a flowchart illustrating details of the steps executed by the driver 34 according to an embodiment of the present invention, and please refer to fig. 1 to fig. 3. The actual execution steps of the driver 34 include steps S21 to S25. Step S21 is: the input screen update rate of the panel 20 is set. Step S22 is: the addressing time of the panel 20 is set. Step S23 is: the data input weight value (twgt) is set according to a predetermined sequential bit plane driving syntax. Step S24 is: the phase linearity of the panel 20 is adjusted by a look-up table (LUT). Step S15 is: the panel 20 is driven by the parameters set in the foregoing steps S21 to S24. The above sequence of steps is merely exemplary, and in fact, the sequence of steps may be reversed or may be performed concurrently, as long as it is reasonably possible to achieve the same.

In one embodiment, step S21 is a value for setting an input frame update rate, wherein the input frame update rate is preset to 60 hertz (Hz), but not limited thereto. In one embodiment, the input frame rate can be adjusted according to the user's requirement, for example, the setting parameters related to the input frame rate in the parameter setting file stored in the memory 33 can be adjusted, and is not limited thereto. In one embodiment, the number of pixel units 211 to be driven and the refresh rate of the input frame can be controlled by adjusting a pixel-clock frequency (pixel-clock frequency) between the signal interfaces of the panel driver 30 and the panel 20.

Regarding step S22, in one embodiment, the addressing time is set according to a second driving condition, wherein the second driving condition can be regarded as the addressing frequency of the panel 20, and the condition is also the optical fluctuation frequency (optical fluctuation frequency) of the panel 20. In one embodiment, the memory write time (i.e., parameter) of the panel 20

) Needs to be set to be less than the refresh time of a frame of the panel 20 (

Wherein the I.C. 25976 is defined as the number of clocks for updating an image in a pixel row, and the parameter I.C. freq is defined as the frequency for updating an image in a pixel row), so as to avoid the generation of unwanted noise at the panel driver 30 due to the overlap of the data writing period of the memory and the image updating period.

Regarding step S23, in one embodiment, the memory 33 may be pre-stored with a sequential bit plane driving syntax, and the driving logic 32 may find the corresponding data input weight value (twgt) from the sequential bit plane driving syntax according to the size of the panel 20, but is not limited thereto. In one embodiment, the magnitude of the data input weight value (twgt) is in a forward relationship with the pixel density of the pixel array 210. Fig. 5 is a comparison diagram of driving parameters (e.g., parameters in the second driving condition) of different pixel densities according to an embodiment of the invention, and please refer to fig. 1 to 4 simultaneously. As shown in fig. 5, the data input weight (twgt) of the slm 1 may be 1083 when the spatial light modulator 1 has a resolution of 2K, and the data input weight (twgt) of the slm 1 may be 2164 when the spatial light modulator 1 has a resolution of 4K, so that the preset data input weight (twgt) is larger when the pixel density is larger. In one embodiment, the data input weight value (twgt) is at least 1080, corresponding to a minimum pixel density (e.g., 4000PPI) of the pixel array 210.

Regarding step S24, in one embodiment, the gray level value and the phase value of the panel 20 can be in a linear relationship by using a look-up table. In an embodiment, the light intensity of each gray-scale value of the panel 20 may be measured by a photodetector (photodetector) and converted into a phase value, and the phase value corresponding to each gray-scale value may be further compared with an ideal value preset in the lookup table and corrected according to the difference, but the invention is not limited thereto. In one embodiment, the difference between the phase value corresponding to each gray level value and the ideal value of the lookup table can be evaluated by an Average Phase Accuracy Error (APAE) and a root-mean-square (RMS).

After steps S21 to S24 are performed, the driving logic circuit 32 can perform step S25 to drive the panel 20 according to the panel express drive scheme.

Accordingly, in one embodiment, by using a liquid crystal material with a high quality factor as the liquid crystal layer 24 and using a panel fast driving scheme to drive the panel 20, the spatial light modulator 1 of the present invention can achieve the effects of fast liquid crystal response speed, full phase voltage, ultra-high pixel density panel, high phase stability, high phase linearity, high phase accuracy, and applicable logic driving and digital driving. It should be noted that the products protected by the present invention are not limited to have the above functions.

One of the conditions for achieving the effect of "fast response speed of liquid crystal" is to use a liquid crystal material with a high quality factor. Due to the characteristics of the liquid crystal material with high quality factor, liquid crystal molecules can still provide the liquid crystal full-phase response speed of less than 10ms under the condition of low voltage (2V) under the condition that the liquid crystal cell gap is small. In contrast, typical commercially available spatial light modulators with liquid crystal response times of less than 10ms all need to be driven with larger voltages (> 5V). The present invention is not limited thereto.

Regarding the effect of the "full phase voltage", one of the conditions is that when the panel fast driving design is used, the driving voltage for driving the panel 20 must meet a specific condition. In one embodiment, the driving voltage comprises a high potential frame (Vw) between 2 and 8V (2V ≦ Vw ≦ 8V) and a low potential frame (Vb) between 0.1 and 3V (0.1V ≦ Vb ≦ 3V). In addition, in one embodiment, the difference between the high potential frame (Vw) and the low potential frame (Vb) should be no more than 5V (| Vw-Vb | ≦ 5V) and no less than 1V (| Vw-Vb | ≧ 1V). The present invention is not limited thereto.

One of the conditions for achieving the effect of the ultra-high pixel density panel is setting the data input weight value of the panel fast driving design, and the data input weight value is increased as the pixel density is higher, so the addressing time of the panel 20 is adjusted accordingly, and the driving of the panel 20 can meet the requirement of the pixel density, and the ultra-high pixel density is mainly called ≧ 4000PPI and the panel resolution ≧ 1920x 1080. The present invention is not limited thereto.

Regarding the effect of "high phase stability", one of the conditions for achieving the effect is that during the actual display period of the panel 20 displaying one frame, the same frame needs to be repeatedly displayed to maintain the driving voltage of the frame, i.e. the driving of the panel 20 must meet the first driving condition, so as to reduce the problem of phase instability caused by static flicker of the frame. In addition, another condition for achieving "high phase stability" is that the addressing time of the panel 20 is shorter than the fastest liquid crystal response time (i.e. Tr) at full gray level to avoid the interference of an electrical addressing procedure of the panel when the liquid crystal is dynamically switched, and the memory reading time is shorter than the operation time of switching the frame to avoid the problem of signal overlap of the electrical addressing procedure. The present invention is not limited thereto.

One of the conditions for achieving the effect of "good phase linearity" is to use a liquid crystal material with a high quality factor. By virtue of the high quality factor of the liquid crystal material, it is possible to accommodate the reduction in the cell gap to pixel pitch ratio (d/p) of the panel 20. For the liquid crystal material with a non-high quality factor, the reduction of the cell gap-to-pixel pitch ratio (d/p) is a difficult condition, because the condition requires a larger voltage condition to achieve full phase modulation, the response time is increased, the non-linear characteristic of the liquid crystal is also obvious, and therefore the liquid crystal material with a non-high quality factor is difficult to achieve high phase linearity. In contrast, the present invention can still achieve high phase linearity under this condition, wherein the relationship between the phase linearity and d/p can be described in the related literature. In addition, another achievement of "good phase linearity" is that high quality factor liquid crystal materials possess high birefringence (birefringence), which provides a more linear electro-optic response (EO). Yet another condition for achieving "good phase linearity" is that the driver 34 of the present invention performs step S24 to adjust the phase linearity by using the look-up table. The present invention is not limited thereto.

Regarding "Phase precision", since Phase precision is related to the uniformity of the panel 20, the present invention can achieve the above-mentioned effects by using a liquid crystal material with a high quality factor to achieve a thinner cell gap. Other studies have attempted to develop LCOS-SLM with thinner cell gap, but these studies cannot control the panel uniformity to the high phase accuracy standard (mSTD <0.04 π), and the above mentioned effects cannot be revealed. The invention can show the above effects, and accurately quantizes the improved LCOS-SLM data, and the high-quality LCOS-SLM pairing technology of the mechanism of the invention is used for achieving high panel uniformity, so that the interference of data analysis caused by poor phase accuracy can be eliminated. The present invention is not limited thereto.

Regarding the effect of "applicable logic driving and digital driving", one of the conditions for achieving this is to use the panel fast driving design. Through the design of fast driving of the panel, when the panel 20 is driven by digital mode, the problem of unstable phase caused by the existing product is not generated, and when the panel 20 is driven by logic mode, the high phase linearity can be still maintained under a plurality of difficult conditions, so the invention is applicable to logic driving and digital driving.

Therefore, the invention can solve the problems which can not be solved by the prior art.

With the above-mentioned effects, the panel 20 of the spatial light modulator 1 can have many application forms which can be greatly different from the existing products, and the following examples are provided for illustration.

In one embodiment, the panel 20 of the spatial light modulator 1 is designed to be driven by a liquid crystal response speed and maintain a phase stability, wherein the liquid crystal response speed of the panel 20 is not greater than 10ms, the phase stability corresponds to an average peak to peak value (Ave P-P), and the average peak to peak value is not greater than 3 percent (Ave P-P ≦ 3%), and the conventional products usually require about 3 times of response time to achieve the phase stability standard. In addition, the existing products cannot achieve the effect of high phase stability with the liquid crystal response speed lower than 10ms, and taking the LETO-VIS-017 which is an example of a fast response which is also tried to be developed by HEP company in recent years, although the liquid crystal response speed is about 6ms, the phase stability error is larger than 20 percent (Ave P-P is larger than 20%). Accordingly, the spatial light modulator 1 of the present embodiment has overcome the problems that the prior art cannot overcome.

In another embodiment, the panel 20 of the spatial light modulator 1 is designed to be driven by a full-phase operating voltage and maintain a phase stability, wherein the full-phase operating voltage includes a high-potential frame (Vw) and a low-potential frame (Vb), the high-potential frame (Vw) is between 2V and 8V (2V ≦ Vw ≦ 8V), the low-potential frame (Vb) is between 0.1V ≦ Vb ≦ 3V, in this embodiment, Vw ≦ 2.1, and when Vb ≦ 0.7, the phase stability corresponds to an average peak-to-peak value (average peak-to-peak value), and the average peak-to-peak value is not greater than 3% percent (3%). In an embodiment, the difference between the high potential frame (Vw) and the low potential frame (Vb) is no greater than 5V (| Vw-Vb | ≦ 5V). In one embodiment, the panel 20 is further designed to be driven by a digital driving method, wherein the high frame (Vw) can be a digital logic state 1, and the low frame (Vb) can correspond to a digital logic state 0, but not limited thereto. Since the conventional product cannot achieve the effects of full-phase operating voltage and high phase stability under the condition of a higher potential frame (Vw) >2.0V, the spatial light modulator 1 of the embodiment overcomes the problem that the prior art cannot overcome.

In yet another embodiment, the panel 20 is further designed to drive the panel with a liquid crystal response speed not greater than 10ms, a phase linearity corresponding to an APAE (average peak to peak) value, and a phase accuracy not greater than 1.5 percent (1.5%), a mSTD (mean standard deviation) value not greater than 0.04 pi (mSTD ≦ 0.04 pi). The conventional products cannot achieve the effects of maintaining high phase linearity, high phase accuracy and fast liquid crystal response speed, for example, the conventional products (e.g., SVGA series or SXGA series) of hmp (hmamatsu photonic) company, which can maintain phase linearity and phase accuracy, but the liquid crystal response speed is greater than 30 ms; further, taking the existing products (e.g. HSP1920 series) of mlo (meadowlark optics) company as an example, although the response speed of the liquid crystal can be improved and the high phase stability can be achieved, the phase linearity corresponds to about 10 to 15% of the APAE value, and the mSTD value corresponding to the phase accuracy is λ/20, which is not satisfactory. Accordingly, the spatial light modulator 1 of the present embodiment has overcome the problems that the prior art cannot overcome.

To further verify the effect of the present invention, an experimental result is used as a verification example. Fig. 6 is a comparison diagram of experimental tests of the spatial light modulator 1 according to the embodiment of the invention and a comparison example, and please refer to fig. 1 to fig. 5 at the same time. In fig. 6, the spatial light modulator 1 of the present embodiment is an experimental machine, and is referred to as "NCTU TKS", and the comparative examples are JDC (jasper Display corporation) 2KSRK series products and HEP (holey photonics) LETO series products, which are referred to as "JDC 2 KSRK" and "HEP LETO", respectively. In addition, experimental parameters were set as follows: the birefringence (Δ n) of the liquid crystal material of "NCTU TKS" was set to about 0.386, the dielectric anisotropy (Δ ∈) thereof was set to about 15.6, the cell gap-to-pixel pitch ratio (d/p) thereof was set to about 0.28, the high potential frame (Vw) of the driving voltage thereof was set to about 2.1V and the low potential frame (Vb) thereof was set to about 0.7V; a liquid crystal material of "JDC 2 KSRK" has a birefringence (Δ n) of about 0.202, a dielectric anisotropy (Δ ∈) of about 10.1, a liquid crystal gap-to-pitch ratio (d/p) of about 0.59, a high potential frame (Vw) of about 4.43V and a low potential frame (Vb) of about 0.84V for a driving voltage; the liquid crystal material of "HEP LETO" has a birefringence (Δ n) of about 0.217, a dielectric anisotropy (Δ ∈) of about 40.0, a liquid crystal gap-to-pitch ratio (d/p) of about 0.38, a high potential frame (Vw) of about 1.55V and a low potential frame (Vb) of about 0.45V for a driving voltage. Additional details regarding the experimental environment are within the knowledge of one skilled in the art and will not be described in detail herein.

As shown in FIG. 6, in terms of phase linearity, the APAE value of "JDC 2 KSRK" is about 0.03 π, the APAE value of "HEP LETO" is about 0.04 π, the APAE value of "NCTU TKS" is about 0.01 π, and the phase linearity of the product of the present invention is significantly better. In terms of phase accuracy, the mSTD value of "JDC 2 KSRK" is about 0.03 π, the mSTD value of "HEP LETO" is about 0.04 π, and the mSTD value of "NCTU TKS" is about 0.04 π, which are not very different. In terms of liquid crystal response time, the liquid crystal response speed of 'JDC 2 KSRK' is about 26.44ms, the liquid crystal response speed of 'HEP LETO' is about 25.88ms, the liquid crystal response speed of 'NCTU TKS' is about 7.11ms, and the liquid crystal response speed of the product is greatly superior to that of the other two products. In terms of phase stability, the P-P value of 'JDC 2 KSRK' is about 5%, the P-P value of 'HEP LETO' is about 3.3%, and the P-P value of 'NCTU TKS' is about 2.6%, so that the product has better phase stability. Therefore, the product of the invention can still have high liquid crystal response speed under the condition of having phase stability, phase accuracy and phase linearity, and achieves the effect which can not be achieved by the existing products.

In an embodiment, the spatial light modulator 1 of the present invention can be applied to products of display technology industries such as color sequential display, holographic display, VR display, or AR display and projection equipment, products of optical lithography industries such as maskless holographic lithography system or deep light 3D printing system, products of optical sensing and image processing and detecting industries such as SLM gain microscope, telescope, etc., biomedical optical tweezers (optical welding) system, 3D diffraction optical array (Tx), 3D optical field image gain (Rx), products of optical communication industries such as diffraction optical gain WSS ROADM network system, and products of optical computing industries such as diffraction optical deep neural network (all-optical computing) for performing deep learning operation, and is not limited thereto.

Therefore, the invention provides an improved spatial light modulator, and the product of the invention can solve the problem which can not be solved by the prior art through the improvement of materials and the matching of a special driving method.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A spatial light modulator, comprising:

a panel, comprising:

a backplane comprising a pixel array, wherein a pixel density of the pixel array is at least 4000 inches of pixel (PPI);

a liquid crystal layer comprising a liquid crystal material, wherein the liquid crystal material has a first Figure of Merit-1, FoM-1;

a panel driver electrically connected to the panel for driving the panel according to a panel fast driving design;

wherein the first merit factor value satisfies the following condition:

2. The spatial light modulator of claim 1, wherein the liquid crystal material further has a second figure of merit factor (FoM-2), and the second figure of merit factor satisfies the following condition:

where FoM-2 is defined as the second figure of merit and Δ ∈ is defined as the dielectric anisotropy (dielectric anisotropy) of the liquid crystal material.

3. The spatial light modulator of claim 1, wherein the panel fast driving scheme comprises an input frame rate (input frame rate) of the panel satisfying the following condition:

Input Frame Rate＝[Tclks]×Repeat，

wherein, the Input Frame Rate is defined as an actual update Rate of the Input Frame to correspond to an actual display period of a Frame, the Tclks is defined as an addressing frequency (addressing frequency) of a sub-Frame to correspond to a driving period of the sub-Frame, and the Repeat is defined as the repeated display times of the sub-Frame in the actual display period of the Frame.

4. The spatial light modulator of claim 3, wherein the addressing frequency is further set to satisfy the following condition:

wherein mclkperrow is defined as a memory clock number (memory clocks) allocated to each row of the pixel array for data writing, mclkfreq is defined as a memory clock frequency (memory clock frequency), swp is defined as a division number of all rows of the pixel array, and twgt is defined as a data input weight value corresponding to an allocation situation when an image data is input to the pixel array.

5. The spatial light modulator of claim 4, wherein the data input weight value is set in a positive relationship with the pixel density of the pixel array.

6. The spatial light modulator of claim 1, wherein the panel further comprises an alignment layer disposed on the liquid crystal layer and a glass cover disposed on the alignment layer, and the driving logic comprises a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and the alignment layer comprises a Polyimide (PI) layer.

7. The spatial light modulator of claim 1, wherein the panel is configured to be driven with a liquid crystal response speed and maintain a phase stability, wherein the liquid crystal response speed is not greater than 10ms, the phase stability corresponds to an average peak to peak value (avg peak to peak value), and the average peak to peak value is not greater than 3 percent (3%).

8. The spatial light modulator of claim 1, wherein the panel is designed to be driven by a full-phase operating voltage and maintain a phase stability, wherein the full-phase operating voltage comprises a high frame (Vw) and a low frame (Vb), the high frame is between 2-8V, the low frame is between 0.1-3V, the phase stability corresponds to an average peak-to-peak (average peak-to-peak) value, and the average peak-to-peak (average peak-to-peak) is not more than 3 percent (3%).

9. The spatial light modulator of claim 8, wherein the panel is further configured to be driven by a digital drive scheme, wherein the high frame corresponds to digital logic state 1 and the low frame corresponds to digital logic state 0.

10. The spatial light modulator of claim 1, wherein the panel is further configured to drive the panel with a liquid crystal response speed of not greater than 10ms, a phase linearity corresponding to an APAE value of not greater than 1.5 percent (1.5%), and a phase accuracy corresponding to a mSTD value of not greater than 0.04 pi.