CN113130652A - Metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN113130652A CN113130652A CN202010044859.8A CN202010044859A CN113130652A CN 113130652 A CN113130652 A CN 113130652A CN 202010044859 A CN202010044859 A CN 202010044859A CN 113130652 A CN113130652 A CN 113130652A
- Authority
- CN
- China
- Prior art keywords
- layer
- trench
- epitaxial layer
- microns
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 26
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- -1 boron ions Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- IJKVHSBPTUYDLN-UHFFFAOYSA-N dihydroxy(oxo)silane Chemical compound O[Si](O)=O IJKVHSBPTUYDLN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 241001272720 Medialuna californiensis Species 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开一种金属氧化物半导体场效晶体管及其制造方法。金属氧化物半导体场效晶体管包含基材结构、多个掺杂区域、多个沟槽氧化层、多个半导体层结构、介电质层结构及金属结构。基材结构包含基底层及磊晶层。磊晶层具有多个沟槽。每个沟槽的沟槽深度为X1微米。多个掺杂区域分别形成于多个沟槽的底部。多个沟槽氧化层分别形成于多个沟槽的内壁。每个沟槽氧化层的氧化层厚度为X2微米。X1与X2符合以下关系式：0.05X1≤X2≤0.25X1。多个半导体层结构分别形成于多个沟槽中，以形成多个沟渠式结构。介电质层结构形成于多个半导体层结构上。金属结构形成于介电质层结构上。借此，金属氧化物半导体场效晶体管能承受较高的工作电压、而不会有烧毁的情形发生。
The invention discloses a metal oxide semiconductor field effect transistor and a manufacturing method thereof. The metal oxide semiconductor field effect transistor includes a substrate structure, a plurality of doped regions, a plurality of trench oxide layers, a plurality of semiconductor layer structures, a dielectric layer structure and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer has a plurality of trenches. The trench depth of each trench is X1 microns. A plurality of doped regions are respectively formed at the bottoms of the plurality of trenches. A plurality of trench oxide layers are respectively formed on the inner walls of the plurality of trenches. The oxide layer thickness of each trench oxide layer is X2 microns. X1 and X2 conform to the following relationship: 0.05X1≤X2≤0.25X1. A plurality of semiconductor layer structures are respectively formed in a plurality of trenches to form a plurality of trench structures. The dielectric layer structure is formed on the plurality of semiconductor layer structures. The metal structure is formed on the dielectric layer structure. Thereby, the MOS transistor can withstand a higher working voltage without burning out.
Description
Technical Field
The present invention relates to a metal oxide semiconductor field effect transistor, and more particularly, to a metal oxide semiconductor field effect transistor suitable for a power supply and a method for manufacturing the same.
Background
With the progress of electronic technology and the trend of miniaturization of electronic products, more and more electronic devices are being manufactured by using integrated circuit processes. However, electronic components in the form of integrated circuits have to consider many levels, for example: high voltage resistance, mutual interference or noise resistance, especially in electronic components of power supplies. Since the power supply needs to receive high voltage input, the high voltage input may cause the integrated circuit type electronic components to burn out, and further cause the power supply to malfunction, which is a main reason why the size of the power supply cannot be reduced.
Among them, the mosfet is also commonly used in power supplies, and the mosfet is used as a converter because the mosfet has a relatively fast operation speed and excellent performance in voltage signal processing. In response to the trend of miniaturization of electronic products, the mosfet is gradually developed to be integrated into a circuit. However, when the power supply is subjected to high voltage, the integrated circuit type mosfet is also burned out due to the insufficient high voltage.
Therefore, the present inventors have found that the above-mentioned defects can be improved, and have conducted intensive studies and have applied the teaching, and finally, have proposed the present invention which is designed reasonably and effectively to improve the above-mentioned defects.
Disclosure of Invention
The present invention is directed to a metal oxide semiconductor field effect transistor and a method for fabricating the same.
In order to solve the above technical problem, one technical solution of the present invention is to provide a mosfet, including: a substrate structure, comprising: a base layer; the epitaxial layer is formed on the substrate layer and is provided with a plurality of grooves which are concavely arranged on one side surface of the epitaxial layer opposite to the substrate layer and are arranged at intervals; wherein a trench depth of each of the trenches is X1 microns, and X1 is a real number greater than zero; a plurality of doped regions respectively formed at the bottoms of the plurality of trenches and diffused toward a portion of the epitaxial layer; the bottom parts of the plurality of trench oxidation layers are respectively abutted against the plurality of doping regions, and a groove is formed around each trench oxidation layer; wherein an oxide layer thickness of each of the trench oxide layers is X2 microns, and X2 is a real number greater than zero; wherein, in each trench and the corresponding trench oxide layer, X1 and X2 satisfy the following relation: x2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1; a plurality of semiconductor layer structures which are respectively formed and filled in the grooves so as to respectively form a plurality of trench structures together with the plurality of trench oxide layers; a dielectric layer structure formed on and covering the semiconductor layer structures and located above the epitaxial layer; and a metal structure formed on a surface of the dielectric layer structure opposite to the substrate layer, and electrically connected to at least one of the trench structures; the metal oxide semiconductor field effect transistor is suitable for being switched on with a working voltage between 50 volts and 800 volts.
Preferably, in each of the trenches and its corresponding trench oxide layer, the trench depth X1 of the trench is between 4 microns and 7 microns, the oxide layer thickness X2 of the trench oxide layer is between 0.5 microns and 0.9 microns, and X1 and X2 satisfy the following relationship: x2 is more than or equal to 0.071X1 and less than or equal to 0.225X 1.
Preferably, the mosfet is adapted to pass the operating voltage of not less than 75 volts and not more than 275 volts.
Preferably, in each of the trenches and its corresponding trench oxide layer, the trench depth X1 of the trench is between 7 microns and 16 microns, the oxide layer thickness X2 of the trench oxide layer is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relationship: x2 is more than or equal to 0.075X1 and less than or equal to 0.22X 1.
Preferably, the mosfet is adapted to pass the operating voltage of not less than 275 volts and not more than 800 volts.
Preferably, the epitaxial layer further includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is formed on the base layer, and the second epitaxial layer is formed on the first epitaxial layer, so that the first epitaxial layer is located between the base layer and the second epitaxial layer; an interface is formed between the first epitaxial layer and the second epitaxial layer, and the interface is approximately positioned at the bottoms of the trenches and is extendedly connected between the doped regions; the trenches are recessed from a side surface of the second epitaxial layer opposite to the first epitaxial layer and located in the second epitaxial layer.
Preferably, the conductivity type of the base layer is the same as that of the first epitaxial layer and the second epitaxial layer; the doping concentration of the substrate layer is higher than that of the first epitaxial layer and that of the second epitaxial layer, and the doping concentration of the first epitaxial layer is different from that of the second epitaxial layer.
The embodiment of the invention also discloses a manufacturing method of the metal oxide semiconductor field effect transistor, which comprises the following steps: providing a substrate structure; the substrate structure comprises a base layer and an epitaxial layer formed on the base layer; forming a plurality of grooves in the epitaxial layer in a concave mode according to the depth of a preset groove; the grooves are alternately recessed on the surface of one side, opposite to the substrate layer, of the epitaxial layer; wherein the preset trench depth is defined as X1 microns, and X1 is a real number greater than zero; forming a plurality of doped regions at the bottoms of the trenches respectively; wherein the plurality of doped regions are respectively diffused from the bottoms of the plurality of trenches towards the part of the epitaxial layer; respectively forming a plurality of groove oxidation layers on the inner walls of the plurality of grooves according to the thickness of a preset oxidation layer; the plurality of trench oxide layers are respectively abutted against the plurality of doped regions, and each trench oxide layer is surrounded to form a groove; wherein the predetermined oxide thickness is defined as X2 microns, X2 is a real number greater than zero, and X1 and X2 satisfy the following relationship: x2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1; forming a plurality of semiconductor layer structures in the grooves respectively so that the semiconductor layer structures and the groove oxide layers can form a plurality of trench structures together; forming a dielectric layer structure on the semiconductor layer structures, so that the semiconductor layer structures are covered by the dielectric layer structure, and the dielectric layer structure is positioned above the epitaxial layer; forming a metal structure on the surface of the dielectric layer structure on the side opposite to the substrate layer to form a metal oxide semiconductor field effect transistor; wherein the metal structure is electrically connected to at least one of the trench structures.
Preferably, the value X2 and the value X1 meet one of the following conditions: if the predetermined trench depth X1 is between 4 microns and 7 microns, the predetermined oxide layer thickness X2 is between 0.5 microns and 0.9 microns, and X1 and X2 satisfy the following relationship: 0.071X1 ≦ X2.225X1, so that the finally formed metal oxide semiconductor field effect transistor is suitable for passing an operating voltage of not less than 75 volts and not more than 275 volts; if the predetermined trench depth X1 is between 7 microns and 16 microns, the predetermined oxide layer thickness X2 is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relationship: 0.075X 1X 2X1 to make the metal oxide semiconductor field effect transistor suitable for passing the working voltage not less than 275 volts and not more than 800 volts.
In summary, the technical solution provided by the present invention disclosed in the embodiments of the present invention can be implemented by "a trench depth of each trench is X1 micrometers, and X1 is a real number greater than zero" and "an oxide layer thickness of each trench oxide layer is X2 micrometers, and X2 is a real number greater than zero; wherein, in each trench and the corresponding trench oxide layer, X1 and X2 satisfy the following relation: the technical proposal that X2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1' ensures that the finally formed metal oxide semiconductor field effect transistor can bear higher working voltage without burning, thereby improving the reliability of the device.
The invention has another advantage that the finally formed metal oxide semiconductor field effect transistor can be suitable for different working voltage specification requirements by adjusting the depth of the groove and correspondingly adjusting the thickness of the oxide layer of the groove.
For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention in any way.
Drawings
Fig. 1 is a schematic diagram of a mosfet according to an embodiment of the invention.
Fig. 2A is a flow chart (one) of a process of fabricating a mosfet.
Fig. 2B is a flow chart (two) of the manufacturing process of the mosfet.
Fig. 2C is a flow chart (iii) of the mosfet manufacturing process.
Fig. 2D is a flow chart (iv) of the mosfet manufacturing process.
Fig. 2E is a flow chart (v) of the mosfet manufacturing process.
Fig. 2F is a flow chart (six) of the mosfet fabrication process.
Fig. 2G is a flow chart (seven) of the mosfet manufacturing process.
Detailed Description
The embodiments of the present invention disclosed herein are described below with reference to specific embodiments, and those skilled in the art will understand the advantages and effects of the present invention from the disclosure of the present specification. The invention is capable of other and different embodiments and its several details are capable of modification and various other changes, which can be made in various details within the specification and without departing from the spirit and scope of the invention. The drawings of the present invention are for illustrative purposes only and are not drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or from one signal to another signal. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.
[ method for manufacturing a MOSFET ]
Referring to fig. 1 and fig. 2A to fig. 2G, a method for fabricating a mosfet according to an embodiment of the present invention includes steps S110 to S170. In this embodiment, the mosfet is a power device, such as: a power supply or a transformer, but the invention is not limited thereto. It should be noted that the order of the steps and the actual operation manner described in the present embodiment can be adjusted according to the requirement, and are not limited to the description in the present embodiment.
In the following, a method for fabricating a mosfet is described, but for convenience of understanding, a cell region of the mosfet is taken as an example in the present embodiment, and a cross-sectional view is taken for a description, please refer to the drawings corresponding to each step, and refer to the drawings of other steps as needed. The specific steps of the method for fabricating the mosfet are described as follows.
As shown in fig. 2A, step S110 includes: a substrate structure 1 is provided. The substrate structure 1 includes: an underlayer 11 and an epitaxial layer 12 formed on the underlayer 11. The two surfaces of the substrate structure 1 on opposite sides are respectively defined as a top surface and a bottom surface (neither figure is labeled). The surface of the epitaxial layer 12 opposite to the base layer 11 is the top surface, and the surface of the base layer 11 opposite to the epitaxial layer 12 is the bottom surface.
More specifically, the material of the base layer 11 may be, for example, an N-type doped semiconductor or a P-type doped semiconductor, the epitaxial layer 12 may be formed on the base layer 11 by, for example, an epitaxial (epitaxiy) process, and the conductivity type of the epitaxial layer 12 may be, for example, the same as that of the base layer 11 (e.g., N-type doping or P-type doping). In the embodiment, the base layer 11 is an N-type doped semiconductor, the epitaxial layer 12 is also an N-type doped semiconductor, and the doping concentration of the base layer 11 is higher than that of the epitaxial layer 12, but the invention is not limited thereto.
Referring to fig. 2A, in the present embodiment, the epitaxial layer 12 further includes a first epitaxial layer 121 and a second epitaxial layer 122. First, the first epitaxial layer 121 is formed on the base layer 11 by an epitaxial process, and then the second epitaxial layer 122 is formed on the first epitaxial layer 121 by an epitaxial process, so that the first epitaxial layer 121 is located between the base layer 11 and the second epitaxial layer 122, and an interface 123 is formed between the first epitaxial layer 121 and the second epitaxial layer 122.
The conductivity type of the base layer 11 is the same as that of the first epitaxial layer 121 and the second epitaxial layer 122. That is, the conductivity types of the base layer 11, the first epitaxial layer 121, and the second epitaxial layer 122 are all N-type doped, but the invention is not limited thereto.
The doping concentration of the substrate layer 11 is higher than that of the first epitaxial layer 121, and the doping concentration of the substrate layer 11 is also higher than that of the second epitaxial layer 122.
In an embodiment of the present invention, the doping concentration of the substrate layer 11 is approximately between 1018/cm3To 1019/cm3The doping concentration of the first epitaxial layer 121 is approximately between 1014/cm3To 1016/cm3And the doping concentration of the second epitaxial layer 122 is also approximately between 1014/cm3To 1016/cm3In the meantime. Furthermore, the doping concentration of first epitaxial layer 121 is different from the doping concentration of second epitaxial layer 122, and the doping concentrations of first epitaxial layer 121 and second epitaxial layer 122 are uniform.
As shown in fig. 2B, step S120 includes: a plurality of trenches 13 are recessed in the epitaxial layer 12 according to a predetermined trench depth. The plurality of trenches 13 may be formed by etching, for example, but the invention is not limited thereto.
Furthermore, a plurality of trenches 13 are recessed at intervals on a side surface of the epitaxial layer 12 opposite to the substrate layer 11. Wherein the preset trench depth is defined as X1 microns, and X1 is a real number greater than zero. In the present embodiment, X1 is a real number not less than 4 and not more than 16.
Accordingly, each of the trenches 13 is formed with a trench depth of X1 μm.
Further, the bottom of the plurality of trenches 13 is not in contact with the substrate layer 11 and is spaced apart from the substrate layer 11. In other words, the plurality of trenches 13 are recessed from the top surface of the substrate structure 1 and do not contact the base layer 11 of the substrate structure 1.
More specifically, an interface 123 is formed between the first epitaxial layer 121 and the second epitaxial layer 122, and the interface 123 is substantially located at (or aligned with) the bottoms of the trenches 13 and is extendedly connected between the doped regions 2 (see fig. 2C). The trenches 13 are recessed from a side surface of the second epitaxial layer 122 opposite to the first epitaxial layer 121, and the trenches 13 are substantially located in the second epitaxial layer 122 and above the first epitaxial layer 121. In addition, the trenches 13 are not in contact with or only partially overlap the first epitaxial layer 121, but the invention is not limited thereto. It should be noted that, in the embodiment, although the interface 123 is illustrated as being cut and aligned with the bottoms of the plurality of grooves 13, the invention is not limited thereto. For example, the interface 123 may be disposed adjacent and below the bottom of the plurality of grooves 13, for example, and spaced a small distance from the bottom of the plurality of grooves 13.
It should be noted that, in fig. 2B, the trench depths X1 of the plurality of trenches 13 are illustrated as having the same depth, but the present invention is not limited thereto. For example, in an embodiment not shown in the present disclosure, the trench depths X1 of the trenches 13 may also be different from each other.
It should be noted that the trenches 13 are described with reference to the trenches 13 at different positions in the epitaxial layer 12 in a cross-sectional view. If viewed as a whole, the grooves 13 may be connected or separated from each other, and the invention is not limited thereto.
As shown in fig. 2C, step S130 includes: a plurality of doped regions 2 are formed at the bottom of the trenches 13, respectively, and the doped regions 2 are diffused from the bottom of the trenches 13 toward the epitaxial layer 12. The doped regions 2 may be formed by an ion implantation process, for example, but the invention is not limited thereto.
That is, the bottom of each trench 13 is formed with a doped region 2, and each doped region 2 is diffused from the bottom of its corresponding trench 13 toward the portion of the epitaxial layer 12. Accordingly, each of the doped regions 2 surrounds the bottom of its corresponding trench 13. Furthermore, in the present embodiment, each of the doped regions 2 only slightly diffuses from the bottom of the corresponding trench 13 toward the epitaxial layer 12 to form a half-moon structure, and each of the doped regions 2 is not in contact with the substrate layer 11 and is spaced apart from the substrate layer 11. It should be noted that, in the present embodiment, each of the doped regions 2 is partially located in the first epitaxial layer 121, and the other portion is located in the second epitaxial layer 122.
Further, in the present embodiment, the conductivity type of the doped regions 2 is different from that of the substrate layer 11 and also different from that of the epitaxial layer 12. That is, the doped regions 2 of the present embodiment are P-type doped semiconductors, and the implanted ion species may be, for example, boron ions (B +).
It should be noted that the doped regions 2 (P-type doped semiconductor) and the epitaxial layer 12 (N-type doped semiconductor) can be formed together as a P-N Junction Diode.
In an embodiment of the present invention, the doping concentration of the doped regions 2 is approximately between 1015/cm3To 1017/cm3In the meantime.
It should be noted that the doping concentrations of the first epitaxial layer 121, the second epitaxial layer 122, and the doped regions 2 need to be low (e.g., not greater than 10)17/cm3) To reduce the conductivity of these components, so that the finally formed mosfet 100 can withstand higher operating voltages. If the doping concentration of the first epitaxial layer 121, the second epitaxial layer 122, and the doped regions 2 needs to be high (e.g., greater than 10)18/cm3) The finally formed mosfet 100 may be burned out by being subjected to an excessive operating voltage.
As shown in fig. 2D, step S140 includes: an oxide layer structure 3 is formed extending on a surface of the epitaxial layer 12 opposite to the substrate layer 11 and on inner walls of the trenches 13 according to a predetermined oxide layer thickness. The oxide layer structure 3 may be formed by a low temperature oxide deposition (LTO deposition) process, for example, but the invention is not limited thereto.
More specifically, the oxide layer structure 3 includes a plurality of trench oxide layers 31 and a capping oxide layer 32. The trench oxide layers 31 are respectively formed on the inner walls of the trenches 13 and respectively abut against the doped regions 2, and each trench oxide layer 31 surrounds and forms a groove 33. Furthermore, the capping oxide layer 32 is formed on a surface of the epitaxial layer 12 opposite to the base layer 11 (i.e. a top surface of the epitaxial layer 12) and is extendedly connected between the trench oxide layers 31. In addition, the material of the oxide layer structure 3 may be, for example, a silicon compound or other dielectric materials. The above-mentioned compound of silicon may be, for example, silica or silicate, and is preferably silica, but the present invention is not limited thereto.
Wherein the predetermined oxide layer thickness is defined as X2 microns, and X2 is a real number greater than zero. In the present embodiment, X2 is a real number not less than 0.5 and not more than 1.5, but the present invention is not limited thereto. Accordingly, each of the trench oxide layers 31 is formed with an oxide thickness of X2 μm.
Furthermore, the predetermined trench depth X1 and the predetermined oxide layer thickness X2 satisfy the following relationship:
0.05X1≤X2≤0.25X1。
according to the above configuration, since the trench depth X1 of each of the trenches 13 is between 4 micrometers and 16 micrometers, the oxide layer thickness X2 of each of the trench oxide layers 31 is between 0.5 micrometers
To 1.5 microns
In between, and the material of each trench oxide layer 31 is silicon dioxide or silicate with high resistance and low conductivity, so that the finally formed mosfet 100 is suitable for applying a working voltage between 50 v and 800 v, and preferably between 200 v and 700 v.
It should be noted that the method for manufacturing the mosfet of this embodiment may adjust the numerical range of the predetermined trench depth X1 according to the predetermined specification requirement of the operating voltage, and correspondingly adjust the numerical range of the predetermined oxide layer thickness X2 according to the numerical range of the predetermined trench depth X1, so that the finally formed mosfet 100 is suitable for the predetermined specification requirement of the operating voltage, and the finally formed mosfet 100 is not burned due to the over-high voltage. Thereby, the reliability of the finally formed mosfet 100 is improved.
More specifically, in the present embodiment, the range of the predetermined trench depth X1 and the range of the predetermined oxide layer thickness X2 satisfy one of the following conditions:
if the predetermined trench depth X1 is between 4 microns and 7 microns, the predetermined oxide layer thickness X2 is between 0.5 microns
To 0.9 micron
And X1 and X2 conform to the following relationship: 0.071X1 ≦ X2 ≦ 0.225X1, so that the finally formed MOSFET 100 is suitable for passing an operating voltage of not less than 75 volts and not more than 275 volts, and preferably an operating voltage of not less than 100 volts and not more than 250 volts.
Further, if the predetermined trench depth X1 is between 7 microns and 16 microns, the predetermined oxide layer thickness X2 is between 1.2 microns
To 1.5 microns
And X1 and X2 conform to the following relationship: 0.075X 1X 2X1 to make the final MOSFET 100 suitable for charging the working voltage of not less than 275V and not more than 800VVoltage, and preferably an operating voltage of not less than 300 volts and not more than 700 volts.
If the predetermined trench depth X1 and the predetermined oxide layer thickness X2 do not satisfy one of the above conditions, the finally formed mosfet 100 may not be suitable for applying the predetermined operating voltage, and may be burned or have poor reliability. For example, if the thickness X2 of the trench oxide layer 31 is too thin, the finally formed mosfet 100 cannot withstand high voltage due to the reduced resistance, and may be burned out.
As shown in fig. 2E and also shown in fig. 1, step S150 includes: a plurality of semiconductor layer structures 4 are respectively formed in the recesses 33 surrounded by the trench oxide layers 31, so that the plurality of semiconductor layer structures 4 and the plurality of trench oxide layers 31 form a plurality of trench structures T together.
Further, the semiconductor structures 4 are respectively filled in the recesses 33 surrounded by the trench oxide layers 31, and the surfaces of the semiconductor structures 4 exposed outside (i.e., the top surfaces of the semiconductor structures 4 in fig. 2E) are lower than the outer surfaces of the capping oxide layers 32 (i.e., the surfaces of the capping oxide layers 32 opposite to the epitaxial layer 12 in fig. 2E) through an etch back step (etch back), for example, but the invention is not limited thereto. Furthermore, the exposed surfaces of the semiconductor layer structures 4 are substantially aligned with the top surface of the second epitaxial layer 122. The material of the plurality of semiconductor layer structures 4 may be, for example, doped polysilicon (polysilicon).
It should be noted that, in an embodiment of the present invention, the plurality of trenches 13 may be defined as deep trenches, and a plurality of shallow trenches (not shown) may be further formed between the plurality of deep trenches 13, and the trench depth of the shallow trenches is smaller than the trench depth of the deep trenches. The shallow trench with a smaller depth can be used to form a trench gate (gate) structure, and the deep trench with a larger depth can be used to form a trench source (source) structure. In addition, the bottom of the substrate structure 1 can be used to connect a drain (drain) wire, but the invention is not limited thereto.
As shown in fig. 2F, step S160 includes: a dielectric layer structure 5 (ILD) is formed and covered on the oxide layer structure 3 and the plurality of semiconductor layer structures 4, so that the oxide layer structure 3 and the plurality of semiconductor layer structures 4 are embedded in the dielectric layer structure 5. The dielectric layer structure 5 may be formed by chemical vapor deposition, for example, but the invention is not limited thereto. For example, the dielectric layer structure 5 may also be formed by physical vapor deposition or other suitable deposition processes. Furthermore, the material of the dielectric layer structure 5 may be, for example, a silicon compound or other dielectric materials.
Furthermore, the outer surface of the dielectric layer structure 5 may be planarized by a Chemical Mechanical Polishing (CMP) process, for example, but the invention is not limited thereto.
As shown in fig. 2G and also shown in fig. 1, step S170 includes: a metal structure 6 is formed on a surface of the dielectric layer structure 5 opposite to the substrate layer 11, and the metal structure 6 partially penetrates through the dielectric layer structure 5 to be electrically connected to at least one of the trench structures T. The metal structure 6 may be formed by deposition, for example, and the metal structure 6 is an integrated structure formed by an aluminum-silicon-copper alloy in the embodiment, but the invention is not limited thereto in practical application.
Further, the metal structure 6 includes: one conductive portion 61 and two contact plugs 62 integrally formed with the conductive portion 61. The conductive portion 61 is formed on a surface of the dielectric layer structure 5 opposite to the substrate layer 11, the two contact plugs 62 are disposed at an interval, and the two contact plugs 62 respectively penetrate through the dielectric layer structure 5, so that the conductive portion 61 can be electrically connected to two adjacent trench structures T of the plurality of trench structures T through the two contact plugs 62 respectively. In addition, the width of each contact plug 62 is smaller than the width of the corresponding trench structure T and also smaller than the width of the corresponding trench 13.
More specifically, two contact plugs 62 are respectively penetratingly formed on the dielectric layer structure 5, and two contact plugs 62 respectively partially extend into the semiconductor layer structures 4 of the two trench structures T, so that the conductive portions 61 can be electrically connected to the semiconductor layer structures 4 of the two trench structures T through the two contact plugs 62 (see fig. 1). Therefore, the semiconductor layer 4 of the two trench structures T is disposed at an equipotential level compared to the two contact plugs 62 electrically connected thereto.
In addition, in the present embodiment, the conductive portion 61 covers only a part of the outer surface of the dielectric layer structure 5, and exposes another part of the outer surface of the dielectric layer structure 5.
It should be noted that, before forming the metal structure 6, the manufacturing method of the present embodiment further includes: two contact grooves (not numbered) are formed in the dielectric layer structure 5 by etching, so as to provide the two contact plugs 62 respectively formed therein.
After the steps S110 to S170 are performed, the metal oxide semiconductor field effect transistor 100 (or trench power device) shown in fig. 1 can be completed, but in practical applications, the steps are not excluded from being replaced by reasonable variations. It is further emphasized that the above-described steps are described in terms of cross-sectional views, which, consistent with the above-described steps, do not preclude the possibility of implementing the present invention in various design layouts. In other words, the mosfet of the present embodiment may have different layout configurations when viewed from the top.
Furthermore, it should be noted that the metal structure 6 partially penetrates through the dielectric layer structure 5 to be in direct contact with and electrically connected to at least one of the trench structures T, but the present invention is not limited thereto. For example, the metal structure 6 may be electrically connected to at least one of the trench structures T by a wire without penetrating the dielectric layer structure 5. In this case, the metal structure 6 may not be in direct contact with any trench structure T.
[ Metal oxide semiconductor field Effect transistor ]
The above is a description of the method for manufacturing the mosfet according to the embodiment of the present invention, and the following is a description of a specific structure of the mosfet 100 according to the embodiment. It should be noted that, although the mosfet 100 of the present embodiment is manufactured by the above-mentioned manufacturing method, the invention is not limited thereto. That is, the mosfet of the present invention can be manufactured by other methods.
As shown in fig. 1, the present embodiment further discloses a mosfet 100, which includes a substrate structure 1, a plurality of doped regions 2, an oxide layer structure 3, a plurality of semiconductor layer structures 4, a dielectric layer structure 5, and a metal structure 6.
The substrate structure 1 includes a base layer 11 and an epitaxial layer 12. The epitaxial layer 12 is formed on the base layer 11, the epitaxial layer 12 has a plurality of trenches 13, and the plurality of trenches 13 are recessed from a surface of the epitaxial layer 12 opposite to the base layer 11 and are arranged at intervals. Wherein a trench depth of each of the trenches 13 is X1 μm, and X1 is a real number greater than zero.
The doped regions 2 are formed at the bottom of the trenches 13 and diffuse towards the epitaxial layer 12.
The oxide layer structure 3 includes a plurality of trench oxide layers 31 and a covering oxide layer 32. The trench oxide layers 31 are respectively formed on the inner walls of the trenches 13 and respectively abut against the doped regions 2, and each trench oxide layer 31 surrounds and forms a groove 33. Furthermore, the capping oxide layer 32 is formed on a surface of the epitaxial layer 12 opposite to the substrate layer 11 and is extendedly connected between the trench oxide layers 31. Wherein the oxide layer thickness of each trench oxide layer 31 is X2 micrometers, and X2 is a real number greater than zero. In each trench and the corresponding trench oxide layer, X1 and X2 satisfy the following relation: x2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1.
The plurality of semiconductor layer structures 4 are respectively formed in the plurality of recesses 33, and the plurality of semiconductor layer structures 4 can be respectively formed together with the plurality of trench oxide layers 31 as a plurality of trench structures T.
The dielectric layer structure 5 is formed and covers the oxide layer structure 3 and the plurality of semiconductor layer structures 4.
The metal structure 6 is formed on a surface of the dielectric layer structure 5 opposite to the substrate layer 11 and partially penetrates through the dielectric layer structure 5, so that the metal structure 6 can be electrically connected to at least one of the trench structures T, but the invention is not limited thereto. For example, the metal structure 6 may be electrically connected to at least one of the trench structures T by a wire without penetrating the dielectric layer structure 5.
According to the above configuration, the mosfet 100 of the present embodiment is adapted to pass an operating voltage between 50 v and 800 v, and preferably between 200 v and 700 v.
It should be noted that the mosfet 100 of the present embodiment may have different trench depths X1 according to different operating voltage specification requirements, and correspondingly adjust the oxide layer thickness X2 according to the trench depth X1, so that the mosfet 100 is suitable for the required operating voltage specification requirements, and the mosfet 100 is not burned due to too high voltage.
In an embodiment of the present invention, the trench depth X1 of the trench 13 is between 4 microns and 6 microns, the oxide thickness X2 of the trench oxide 31 is between 0.5 microns and 0.6 microns, and X1 and X2 satisfy the following relation: x2 is more than or equal to 0.08X1 and less than or equal to 0.15X 1.
Accordingly, the mosfet 100 is adapted to be energized with an operating voltage of not less than 75 volts and not more than 125 volts.
In an embodiment of the present invention, the trench depth X1 of the trench 13 is between 5 microns and 7 microns, the oxide thickness X2 of the trench oxide 31 is between 0.7 microns and 0.9 microns, and X1 and X2 satisfy the following relation: x2 is more than or equal to 0.10X1 and less than or equal to 0.18X 1.
Accordingly, the mosfet 100 is adapted to be energized with an operating voltage of not less than 125 volts and not more than 275 volts.
In an embodiment of the present invention, the trench depth X1 of the trench 13 is between 7 microns and 16 microns, the oxide thickness X2 of the trench oxide 31 is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relation: x2 is more than or equal to 0.075X1 and less than or equal to 0.22X 1.
Accordingly, the mosfet 100 is adapted to pass an operating voltage of not less than 275 v and not more than 800 v.
It should be noted that, as described in the above embodiment, the number of the plurality of trenches 13 is 5, and the number of the plurality of trench structures T is also 5 corresponding to the number of the plurality of trenches 13, but the invention is not limited thereto, and the number of the plurality of trenches 13 and the number of the trench structures T may be adjusted according to design requirements.
[ advantageous effects of the embodiments ]
One of the advantages of the present invention is that the technical solution provided by the present invention can pass "a trench depth of each trench is X1 micrometers and X1 is a real number greater than zero" and "an oxide layer thickness of each trench oxide layer is X2 micrometers and X2 is a real number greater than zero; wherein, in each trench and the corresponding trench oxide layer, X1 and X2 satisfy the following relation: the technical proposal that X2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1' ensures that the finally formed metal oxide semiconductor field effect transistor can bear higher working voltage without burning, thereby improving the reliability of the device.
The invention has another advantage that the finally formed metal oxide semiconductor field effect transistor can be suitable for different working voltage specification requirements by adjusting the depth of the groove and correspondingly adjusting the thickness of the oxide layer of the groove.
In addition, in the aspect of chip design, because the technical scheme provided by the invention can bear higher working voltage under the condition of not needing to connect the metal oxide semiconductor field effect transistor in series, the area occupied by the metal oxide semiconductor field effect transistor on the chip can be greatly reduced, other electronic components can be designed on the chip, and the functions of the chip are more diversified.
The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, so that the invention is not limited by the disclosure of the invention.
Claims (9)
1. A metal oxide semiconductor field effect transistor, comprising:
a substrate structure, comprising:
a base layer; and
an epitaxial layer formed on the substrate layer and having a plurality of trenches recessed from a surface of the epitaxial layer opposite to the substrate layer and arranged at intervals; wherein a trench depth of each of the trenches is X1 microns, and X1 is a real number greater than zero;
a plurality of doped regions respectively formed at the bottoms of the plurality of trenches and diffused toward a portion of the epitaxial layer;
the bottom parts of the plurality of trench oxidation layers are respectively abutted against the plurality of doping regions, and a groove is formed around each trench oxidation layer; wherein an oxide layer thickness of each of the trench oxide layers is X2 microns, and X2 is a real number greater than zero; wherein, in each trench and the corresponding trench oxide layer, X1 and X2 satisfy the following relation: x2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1;
a plurality of semiconductor layer structures which are respectively formed and filled in the grooves so as to respectively form a plurality of trench structures together with the plurality of trench oxide layers;
a dielectric layer structure formed on and covering the semiconductor layer structures and located above the epitaxial layer; and
a metal structure formed on a surface of the dielectric layer structure opposite to the substrate layer, and electrically connected to at least one of the trench structures;
the metal oxide semiconductor field effect transistor is suitable for being switched on with a working voltage between 50 volts and 800 volts.
2. The mosfet of claim 1 wherein, in each of the trenches and its corresponding trench oxide layer, the trench depth X1 of the trench is between 4 microns and 7 microns, the oxide layer thickness X2 of the trench oxide layer is between 0.5 microns and 0.9 microns, and X1 and X2 satisfy the following relationship: x2 is more than or equal to 0.071X1 and less than or equal to 0.225X 1.
3. The mosfet of claim 2, wherein the mosfet is adapted to pass the operating voltage at not less than 75 volts and not more than 275 volts.
4. The mosfet of claim 1 wherein, in each of the trenches and its corresponding trench oxide layer, the trench depth X1 of the trench is between 7 microns and 16 microns, the oxide layer thickness X2 of the trench oxide layer is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relationship: x2 is more than or equal to 0.075X1 and less than or equal to 0.22X 1.
5. The MOSFET of claim 4, wherein the operating voltage applied thereto is not less than 275 volts and not more than 800 volts.
6. The MOSFET of any one of claims 1-5, wherein the epitaxial layer further comprises a first epitaxial layer and a second epitaxial layer, the first epitaxial layer being formed on the base layer and the second epitaxial layer being formed on the first epitaxial layer such that the first epitaxial layer is between the base layer and the second epitaxial layer; an interface is formed between the first epitaxial layer and the second epitaxial layer, and the interface is approximately positioned at the bottoms of the trenches and is extendedly connected between the doped regions; the trenches are recessed from a side surface of the second epitaxial layer opposite to the first epitaxial layer and located in the second epitaxial layer.
7. The MOSFET of claim 6, wherein the base layer has a conductivity type that is the same as the conductivity type of the first epitaxial layer and the conductivity type of the second epitaxial layer; the doping concentration of the substrate layer is higher than that of the first epitaxial layer and that of the second epitaxial layer, and the doping concentration of the first epitaxial layer is different from that of the second epitaxial layer.
8. A method of fabricating a metal oxide semiconductor field effect transistor, the method comprising:
providing a substrate structure; the substrate structure comprises a base layer and an epitaxial layer formed on the base layer;
forming a plurality of grooves in the epitaxial layer in a concave mode according to the depth of a preset groove; the grooves are alternately recessed on the surface of one side, opposite to the substrate layer, of the epitaxial layer; wherein the preset trench depth is defined as X1 microns, and X1 is a real number greater than zero;
forming a plurality of doped regions at the bottoms of the trenches respectively; wherein the plurality of doped regions are respectively diffused from the bottoms of the plurality of trenches towards the part of the epitaxial layer;
respectively forming a plurality of groove oxidation layers on the inner walls of the plurality of grooves according to the thickness of a preset oxidation layer; the plurality of trench oxide layers are respectively abutted against the plurality of doped regions, and each trench oxide layer is surrounded to form a groove; wherein the predetermined oxide thickness is defined as X2 microns, X2 is a real number greater than zero, and X1 and X2 satisfy the following relationship: x2 is more than or equal to 0.05X1 and less than or equal to 0.25X 1;
forming a plurality of semiconductor layer structures in the grooves respectively so that the semiconductor layer structures and the groove oxide layers can form a plurality of trench structures together;
forming a dielectric layer structure on the semiconductor layer structures, so that the semiconductor layer structures are covered by the dielectric layer structure, and the dielectric layer structure is positioned above the epitaxial layer; and
forming a metal structure on a surface of the dielectric layer structure opposite to the substrate layer to form a metal oxide semiconductor field effect transistor; wherein the metal structure is electrically connected to at least one of the trench structures.
9. The method of claim 8, wherein the values X2 and X1 satisfy one of the following conditions:
if the predetermined trench depth X1 is between 4 microns and 7 microns, the predetermined oxide layer thickness X2 is between 0.5 microns and 0.9 microns, and X1 and X2 satisfy the following relationship: 0.071X1 ≦ X2 ≦ 0.225X1, so that the finally formed metal oxide semiconductor field effect transistor is suitable for being switched on with an operating voltage of not less than 75 volts and not more than 275 volts;
if the predetermined trench depth X1 is between 7 microns and 16 microns, the predetermined oxide layer thickness X2 is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relationship: 0.075X 1X 2X1 to make the metal oxide semiconductor field effect transistor suitable for passing the working voltage not less than 275 volts and not more than 800 volts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010044859.8A CN113130652A (en) | 2020-01-16 | 2020-01-16 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010044859.8A CN113130652A (en) | 2020-01-16 | 2020-01-16 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113130652A true CN113130652A (en) | 2021-07-16 |
Family
ID=76771592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010044859.8A Pending CN113130652A (en) | 2020-01-16 | 2020-01-16 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113130652A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291298B1 (en) * | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| US6710403B2 (en) * | 2002-07-30 | 2004-03-23 | Fairchild Semiconductor Corporation | Dual trench power MOSFET |
| CN102007584A (en) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | Semiconductor device structures and related processes |
| CN103579345A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | High voltage field balanced mosfet |
| US20140077287A1 (en) * | 2012-09-19 | 2014-03-20 | Vishay-Siliconix | Breakdown voltage blocking device |
| CN110289314A (en) * | 2018-03-19 | 2019-09-27 | 全宇昕科技股份有限公司 | High Voltage Metal Oxide Half Field Effect Transistor |
| CN211654829U (en) * | 2020-01-16 | 2020-10-09 | 全宇昕科技股份有限公司 | Metal oxide semiconductor field effect transistor |
-
2020
- 2020-01-16 CN CN202010044859.8A patent/CN113130652A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291298B1 (en) * | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| US6710403B2 (en) * | 2002-07-30 | 2004-03-23 | Fairchild Semiconductor Corporation | Dual trench power MOSFET |
| CN102007584A (en) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | Semiconductor device structures and related processes |
| CN103579345A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | High voltage field balanced mosfet |
| US20140077287A1 (en) * | 2012-09-19 | 2014-03-20 | Vishay-Siliconix | Breakdown voltage blocking device |
| CN110289314A (en) * | 2018-03-19 | 2019-09-27 | 全宇昕科技股份有限公司 | High Voltage Metal Oxide Half Field Effect Transistor |
| CN211654829U (en) * | 2020-01-16 | 2020-10-09 | 全宇昕科技股份有限公司 | Metal oxide semiconductor field effect transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7193262B2 (en) | Low-cost deep trench decoupling capacitor device and process of manufacture | |
| KR100363353B1 (en) | Semiconductor device and manufacturing method thereof | |
| TWI396240B (en) | Method of manufacturing a power semiconductor component | |
| US7655974B2 (en) | Semiconductor device | |
| JP4417962B2 (en) | Planarization method in the manufacture of superjunction devices | |
| CN102222695A (en) | Structure for making a top-side contact to a substrate | |
| US6921942B2 (en) | Structure of a lateral diffusion MOS transistor in widespread use as a power control device | |
| WO2015008444A1 (en) | Semiconductor device | |
| CN211654829U (en) | Metal oxide semiconductor field effect transistor | |
| CN212113728U (en) | metal oxide semiconductor field effect transistor | |
| JP4890773B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20210351292A1 (en) | Metal oxide semiconductor field effect transistor and method for manufacturing the same | |
| JP2005039057A (en) | Semiconductor device and manufacturing method thereof | |
| CN113130652A (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| TWI724717B (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| US7557429B2 (en) | Semiconductor device with resistor element and dummy active region | |
| JP3642466B2 (en) | Manufacturing method of semiconductor device | |
| KR100935770B1 (en) | Semiconductor device and manufacturing method thereof | |
| US7256462B2 (en) | Semiconductor device | |
| JP2005175297A (en) | Semiconductor device | |
| US6537893B2 (en) | Substrate isolated transistor | |
| TWI736087B (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| US11257947B2 (en) | Metal oxide semiconductor field effect transistor and method for manufacturing the same | |
| JP5003856B2 (en) | Semiconductor device | |
| CN113130651A (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |