CN113130337B - Two-step process for high-density, narrow-pitch, high-reliability flip-chip interconnection based on ACA/ACF - Google Patents

Abstract

The invention provides a two-step process method for high-reliability flip-chip interconnection of high-density narrow-pitch chips based on ACA/ACF, which comprises the following steps: step 1: coating an insulating adhesive with a height not higher than that of the bump (bump) on the chip, and enabling the insulating adhesive not to cover the top end of the bump; step 2: and coating a layer of anisotropic conductive adhesive (ACA/ACF) on the substrate, and then performing thermocompression bonding on the chip and the substrate to obtain high-reliability interconnection. The invention cuts off the connection between two adjacent bulbs, can effectively prevent conductive particles from entering between the two bulbs in the curing process, and greatly reduces the probability of short circuit between the bulbs; and the generation of cavities between bumps during flip-chip bonding is reduced, the contact thermal resistance of ACA/ACF interconnection is reduced, and the reliability of narrow-pitch chip interconnection is improved. In addition, the invention reduces the stress caused by mismatch of CTE coefficients of materials; the bonding strength of chip interconnection is improved, and the mechanical property of chip bonding is increased.

Description

Two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF

Technical Field

The invention relates to the technical field of chip flip-chip bonding using ACA/ACF interconnection, and in particular to a two-step process for high-density, narrow-pitch, high-reliability flip-chip interconnection based on ACA/ACF.

Background Art

The microelectronics industry is the largest industry in today's information age. As the foundation of the electronics industry, the manufacturing process of microelectronic devices has also been advancing with technological innovation. After entering the 21st century, microelectronic packaging technology has entered the era of ultra-large-scale integrated circuits. High-density packaging is an inevitable trend in the development of microelectronics technology. The interconnection size has been reduced from 30μm to the next, which is of great significance to the development of microelectronics sealing technology. Electronic packaging technology aims to develop the system in the direction of miniaturization, high performance, high reliability and low cost. At present, the bonding methods of bumps and pads mainly include wire bonding, automatic tape bonding and flip-chip bonding. Among them, automatic tape bonding and wire bonding technology are no longer suitable for high-density packaging of chips due to their own limitations. Flip-chip bonding technology is increasingly widely used in microelectronic packaging because of its advantages such as small pitch, simple process and low cost. Flip-chip bonding includes three main forms: controlled collapse chip connection, thermal ultrasonic welding and conductive adhesive connection. As flip-chip interconnection technology gradually becomes the mainstream of the packaging industry, the interconnection density continues to increase and the bump distance continues to decrease. New interconnection materials and technologies must be developed to meet the increasingly stringent requirements of the mechanical, thermal and electrical properties of the interconnection. The developed micro/nano interconnection technology has been adopted by the industry and can achieve high-density, multi-functional integration and packaging. However, the progress of micro/nano system technology can no longer guarantee the reliability of traditional interconnection materials. The development of electronic components is limited by the interconnection. Therefore, in order to alleviate the existing interconnection-related problems, two solutions are proposed, one is to use anisotropic conductive adhesive interconnection, and the other is to develop new interconnection materials with higher material properties.

Anisotropic conductive adhesive/paste (ACA/ACF) is considered to be one of the most promising packaging materials. ACA/ACF is a composite material consisting of a polymer matrix (epoxy resin) and conductive particles randomly distributed therein. It has the advantages of being pollution-free, having a low curing temperature, being applicable to heat-sensitive materials and non-solderable materials, being able to provide interconnections with finer pitches, having simple process steps, and having good maintenance performance. It is a very important lead-free connection material. It can be divided into paste-like anisotropic conductive adhesive (ACA) and film-like anisotropic conductive adhesive (ACF) according to its existing state. The biggest problem currently encountered by ACA/ACF is the problem of short circuits that are prone to occur in the interconnection.

Summary of the invention

The invention provides a two-step process for high-density narrow-pitch chip high-reliability flip-chip interconnection based on ACA/ACF, and its purpose is to use the two-step process of conductive glue to achieve high-density narrow-pitch chip interconnection and improve the reliability of chip packaging.

In order to achieve the above object, the present invention provides a two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF, comprising the following steps:

Step 1: Apply a layer of insulating glue on the chip that is not higher than the height of the bump, and make sure that the insulating glue does not cover the top of the bump;

Step 2: Apply a layer of anisotropic conductive adhesive (ACA/ACF) on the substrate, and then thermally bond the chip and substrate to obtain a high-reliability interconnection.

Preferably, the bump interval is less than 10 um.

Preferably, the difference between the thickness of the insulating glue and the height of the bump is no more than 0.5 um.

Preferably, the substrate is preheated before coating the ACA/ACF.

Preferably, the preheating temperature is 60-90° C., and the time is 2-5 seconds.

Preferably, the viscosity of the insulating glue is greater than the viscosity of ACA/ACF.

Preferably, the thickness of the ACA/ACF is 10-20 um, and is in full contact with the insulating glue during bonding.

Preferably, during thermocompression bonding, the chip bumps are aligned with the substrate pads, and the coverage area of the insulating adhesive is larger than the coverage area of the ACA/ACF.

Preferably, the temperature of the hot pressing bonding is 150-210° C., the pressure is 15-60 MPa, and the time is 8-15 s.

Preferably, the diameter of the conductive particles in the ACA/ACF is less than 1.5 um.

The above scheme of the present invention has the following beneficial effects:

The present invention applies insulating glue on the chip before flip-chip bonding. On the one hand, the connection between two adjacent bumps is cut off, which can effectively prevent conductive particles from entering between the two bumps during the curing process, greatly reducing the probability of short circuit between the bumps; on the other hand, the insulating glue is spread between the bumps, which reduces the generation of voids between the bumps during flip-chip bonding, reduces the contact thermal resistance of ACA/ACF interconnection, and improves the reliability of narrow-pitch chip interconnection.

The present invention applies a layer of insulating glue before using ACA/ACF, thereby reducing the stress caused by mismatch of CTE coefficients of materials, improving the bonding strength of chip interconnection, and increasing the mechanical properties of chip bonding.

The present invention is simple and efficient, can effectively improve the reliability of high-density and narrow-pitch chip interconnection, improves the quality of chip flip-chip interconnection, and is conducive to industrial production.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an interconnection chip of the present invention.

FIG. 2 is a graph showing the probability variation of short circuit and open circuit when l=10 μm, d=10 μm, Vf=0.15, and r=1 to 3 μm.

FIG3 is a graph showing the probability variation of short circuit and open circuit when l=10 μm, d=10 μm, Vf=0-0.3, r=1.5 μm.

FIG. 4 is a graph showing the probability variation of short circuit and open circuit when Vf=0.145; r=1.5 μm; d=10 μm; l=10 μm.

FIG5 is a graph showing the probability variation of short circuit and open circuit when Vf=0.145; r=1.3 μm; d=9 μm; l=9 μm.

FIG6 is a graph showing the probability variation of short circuit and open circuit when Vf=0.145; r=1.1 μm; d=8 μm; l=8 μm.

[Description of Reference Numerals]

1-chip; 2-bump; 3-insulating glue; 4-ACA/ACF; 5-substrate; 6-pad.

DETAILED DESCRIPTION

In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

Examples 1 to 10

Design chip bump spacing and insulation glue according to Table 1.

A layer of insulating glue is applied on the chip, the substrate is preheated at 60°C for 5 seconds, and then ACA/ACF is applied to the substrate. The ACA/ACF coating area is smaller than the insulating glue coating area. The chip bumps are aligned with the substrate pads, and hot pressing bonding is performed at 150°C and 15MPa for 15 seconds to deform the conductive particles to a certain extent, thereby obtaining a high-reliability, high-density, narrow-pitch chip interconnection, as shown in Figure 1.

Failure probability analysis of two-step process

Open circuit analysis

Assuming that the conductive particles in the ACF obey the Poisson distribution, then:

Among them, r is the radius of the conductive particle; l is the side length of the square bump; Vf is the volume fraction of the conductive particles in the ACF; u1 is the average number of conductive particles on the bump.

Short circuit analysis

Where d is the distance between bumps; h is the sum of the height of the bump and the diameter of the conductive particle; u2 is the average number of conductive particles between bump regions; k is the number of cubic boxes containing conductive particles between bump regions, (4πr ³ /3) is the volume of the cubic box containing conductive particles; N is the number of cubic boxes between bump regions, (2r) ³ cubic boxes have a volume;

Overall failure probability analysis

If open and short circuits are independent events then:

P _{opening∩bridging} =P _bridging ·P _opening

P _{opening∪bridging} =P _opening +P _bridging -P _{opening∩bridging}

＝P _opening +P _bridging -P _opening ·P _bridging

The present invention adopts a two-step process method, and a layer of insulating glue is applied between the bonds, which effectively prevents the entry of conductive particles. The area between the bumps that conductive particles can enter is changed from the previous h+2r to the current h=2r. From the calculation formula, it can be seen that the open circuit probability of the bump is independent of the value of h, and the open circuit mainly depends on the radius size of the conductive particles and the volume fraction of the conductive particles; the addition of insulating glue only reduces the probability of short circuit failure between the bumps.

When l = 10 μm, d = 10 μm, Vf = 0.15, r = 1-3 μm, the probability changes of short circuit and open circuit are shown in FIG2 .

When l=10μm, d=10μm; Vf=0-0.3, r=1.5μm, the probability changes of short circuit and open circuit are shown in FIG3 .

It can be seen from Figures 2 and 3 that by ensuring that the diameter of the conductive particles is less than 1.6μm and the integral fraction of the conductive particles is about 0.145, the reliable interconnection between the chip and the substrate can be guaranteed, so that the failure probabilities of short circuit and open circuit are both below 5%; as the distance between the bumps decreases, the diameter of the conductive particles should gradually decrease.

When the diameter r of the conductive particles is 1.5 μm, 1.3 μm and 1.1 μm respectively, the probability changes of short circuit and open circuit are shown in FIG4 , FIG5 and FIG6 respectively.

The failure probability analysis results are shown in Table 1:

Table 1: Probability analysis results of open circuit, short circuit and overall failure in the embodiments of the present invention

After analysis, it can be seen that when the diameter of the conductive particles is less than 1.5μm and the volume fraction of the conductive particles is 0.15±0.025, when a two-step process is used, a layer of insulating glue is applied between the bonds with a distance less than 0.5μm from the top of the bump, which reduces the size of the particles entering the bump area. When the distance between the bumps is less than 10μm, the probability of chip flip-chip interconnection failure can be effectively reduced to less than 10%, achieving reliable interconnection of high-density narrow-pitch chips.

The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims (7)

1. A two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF, characterized by comprising the following steps: Step 1: Apply a layer of insulating glue on the chip that is not higher than the height of the bumps, and make sure that the insulating glue does not cover the top of the bumps; Step 2: Coat a layer of anisotropic conductive adhesive on the substrate, and then perform thermocompression bonding on the chip and substrate to obtain a high-reliability interconnection; The pitch of the bumps is less than 10um; The diameter of the conductive particles in the anisotropic conductive adhesive is less than 1.5um The difference between the thickness of the insulating glue and the height of the bump is no more than 0.5um. 2. According to the two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF in claim 1, the substrate is preheated before coating the anisotropic conductive adhesive. 3. According to the two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF in claim 2, the preheating temperature is 60-90°C and the time is 2-5s. 4. According to the two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF as claimed in claim 1, the viscosity of the insulating adhesive is greater than the viscosity of the anisotropic conductive adhesive. 5. According to the two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF as claimed in claim 1, the thickness of the anisotropic conductive adhesive is 10-20 um and is in full contact with the insulating adhesive during bonding. 6. According to the two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF as described in claim 1, during thermocompression bonding, the chip bumps are aligned with the substrate pads, and the coverage area of the insulating adhesive is greater than the coverage area of the anisotropic conductive adhesive. 7. According to the two-step process for high-density, narrow-pitch chip and high-reliability flip-chip interconnection based on ACA/ACF as claimed in claim 1, the temperature of the thermal compression bonding is 150-210°C; the pressure is 15-60MPa; and the time is 8-15s.