CN113130312B - Method for forming semiconductor structure - Google Patents
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- CN113130312B CN113130312B CN202010048795.9A CN202010048795A CN113130312B CN 113130312 B CN113130312 B CN 113130312B CN 202010048795 A CN202010048795 A CN 202010048795A CN 113130312 B CN113130312 B CN 113130312B
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 220
- 238000005530 etching Methods 0.000 claims abstract description 97
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- 239000011241 protective layer Substances 0.000 claims abstract description 36
- 238000011049 filling Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 45
- 239000003989 dielectric material Substances 0.000 claims description 21
- 238000005498 polishing Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000005388 borosilicate glass Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims 1
- 238000001312 dry etching Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
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- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, and forming a pseudo gate structure on the substrate; forming an etching stop layer on the substrate and the pseudo gate structure; forming a protective layer on the surface of the etching stop layer; forming a sacrificial layer on the surface of the protective layer, wherein the top of the sacrificial layer is flush with the top surface of the pseudo gate structure; sequentially etching the protective layer and the etching stop layer until the top of the protective layer, the top of the etching stop layer and the top surface of the pseudo gate structure are flush; removing the sacrificial layer; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure to form an opening; and filling metal into the opening to form a metal grid. The forming method provided by the embodiment of the invention ensures that the forming height of the metal grid electrode is easier to control.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor structure.
Background
MOS transistors are one of the most important elements in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure on the surface of the semiconductor substrate, a source region in the semiconductor substrate on one side of the gate structure and a drain region in the semiconductor substrate on the other side of the gate structure. The operating principle of the MOS transistor is as follows: the switching signal is generated by applying a voltage across the gate structure, regulating the current through the channel at the bottom of the gate structure.
With the development of semiconductor technology, the control capability of a conventional planar MOS transistor on channel current becomes weak, resulting in serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, and generally includes a Fin protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall surface of the Fin, a source region in the Fin on one side of the gate structure, and a drain region in the Fin on the other side of the gate structure.
Whether the semiconductor device is a planar MOS transistor or a fin field effect transistor, the height control of the gate structure is poor.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which can effectively control the forming height of a metal grid.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, and forming a pseudo gate structure on the substrate; forming an etching stop layer on the substrate and the pseudo gate structure; forming a protective layer on the surface of the etching stop layer; forming a sacrificial layer on the surface of the protective layer, wherein the top of the sacrificial layer is flush with the top surface of the pseudo gate structure; sequentially etching the protective layer and the etching stop layer until the top of the protective layer, the top of the etching stop layer and the top surface of the pseudo gate structure are flush; removing the sacrificial layer; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure to form an opening; and filling metal into the opening to form a metal grid.
Optionally, the material of the sacrificial layer is carbon-containing organic matter.
Alternatively, the method of forming the sacrificial layer includes spin coating.
Optionally, the step of forming the sacrificial layer includes: forming a sacrificial material layer on the surface of the protective layer, wherein the sacrificial material layer covers the top surface and the side wall surface of the protective layer; and etching the sacrificial material layer until the top of the sacrificial material layer is flush with the top of the pseudo gate structure, and forming a sacrificial layer.
Optionally, the method of etching back the sacrificial material layer is dry etching, and the process parameters of the dry etching include: etching atmosphereComprising O 2 The O is 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-200 millitorr, and the etching power is 100-2000 watts.
Optionally, the method for forming the protective layer includes a chemical vapor deposition method or an atomic layer deposition method.
Optionally, the method for etching the protective layer is a Certas etching process, wherein the Certas etching process comprises remote etching and in-situ annealing after the remote etching, and the process parameters of the remote etching comprise: the etching atmosphere comprises NH 3 And HF 5 The NH is 3 The flow rate of the gas is 5-100 sccm, the HF 5 The flow of the gas is 5-100 sccm, and the etching temperature is 20-80 ℃; the annealing temperature of the in-situ annealing is 100-250 ℃.
Optionally, the step of forming the interlayer dielectric layer includes: forming a dielectric material layer on the substrate, wherein the top of the dielectric material layer is higher than the top surface of the pseudo gate structure; and carrying out chemical mechanical polishing on the dielectric material layer until the top surface of the pseudo gate structure is exposed, so as to form an interlayer dielectric layer.
Optionally, the material of the protective layer is the same as the material of the interlayer dielectric layer.
Optionally, the material of the protective layer and the interlayer dielectric layer includes one or more of silicon oxide, borosilicate glass, borophosphosilicate glass or tetraethyl orthosilicate.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
before forming the interlayer dielectric layer, etching the etching stop layer until the top of the etching stop layer is flush with the top surface of the pseudo gate structure, forming an interlayer dielectric layer exposing the top surface of the pseudo gate structure, and controlling the forming height of the metal gate by taking the heights of the etching stop layer and the interlayer dielectric layer as the basis. Compared with the technical scheme that the interlayer dielectric layer and the etching stop layer are ground at the same time, the method and the device have the advantages that the grinding selection ratio of the interlayer dielectric layer and the etching stop layer is not needed to be considered, the heights of the etching stop layer and the interlayer dielectric layer are easier to control, and therefore the height of the metal grid is more effectively controlled.
Drawings
FIGS. 1-3 are schematic diagrams illustrating a semiconductor structure formation process in one embodiment;
fig. 4 to 12 are schematic views illustrating steps in the formation of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, the control of the metal gate height is unstable in the current process of forming a semiconductor structure.
Fig. 1-3 are schematic diagrams illustrating a semiconductor structure forming process in an embodiment.
Referring to fig. 1, a semiconductor substrate 10 is provided, and a dummy gate structure 20 is formed on the semiconductor substrate 10; forming an etch stop layer 30 covering the dummy gate structure 20 on the semiconductor substrate 10; a dielectric layer 40 is formed on the surface of the etch stop layer 30.
Referring to fig. 2, the dielectric layer 40 and the etching stop layer 30 are chemically and mechanically polished, and the surface of the dummy gate structure 20 is used as a stop layer, so that the surface of the dielectric layer 40 and the etching stop layer 30 are flush with the surface of the dummy gate structure 20.
Referring to fig. 3, the dummy gate structure 20 is removed to form an opening (not shown), the opening is filled with a metal layer (not shown), the metal layer is polished by chemical mechanical polishing, and the dielectric layer 40 is used as a stop layer to form a metal gate 50.
The inventor finds that in the method for forming the semiconductor structure, when the surface of the pseudo gate structure is taken as a stop layer and the dielectric layer and the etching stop layer are polished chemically and mechanically, the polishing selection ratio among the dielectric layer, the etching stop layer and the pseudo gate structure is difficult to control, the dielectric layer and the etching stop layer are easy to be excessively polished during polishing, uneven polishing surfaces can be caused, and the height control of the metal gate is not facilitated and the height uniformity of the metal gate is also affected when the metal gate is formed by removing the pseudo gate structure subsequently.
In order to solve the above problems, the inventors have studied to provide a method of forming a semiconductor structure,
in order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 12 are schematic views illustrating steps in the formation of a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 100 is provided, and a dummy gate structure 110 is formed on the substrate 100.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is used to form a finfet, and thus, discrete fins (not shown) are also formed on the substrate 100. In other embodiments, the substrate is used to form a planar transistor, and correspondingly, the substrate is a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The dummy gate structure 110 is a single-layer structure or a stacked-layer structure. The dummy gate structure 110 includes a dummy gate layer 111; or the dummy gate structure 110 includes a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer. In this embodiment, the dummy gate structure 110 is a stacked structure, and the dummy gate structure 110 includes a dummy oxide layer (not shown) and a dummy gate layer 111 on the dummy oxide layer.
In this embodiment, the material of the dummy oxide layer is silicon oxide, the material of the dummy gate layer 111 is polysilicon, and the metal gate formed by removing the dummy gate structure 110 may be a metal gate of an NMOS transistor or a metal gate of a PMOS transistor.
Specifically, the step of forming the dummy gate structure 110 includes: forming a dummy oxide layer on the substrate 100, wherein the dummy oxide layer spans across the fin portion and covers the top surface and the side wall surface of the fin portion; forming a dummy gate film on the dummy oxide layer; forming a hard mask structure 120 on the surface of the pseudo gate film, wherein the hard mask structure 120 defines a pattern of the pseudo gate structure 110 to be formed; and patterning the dummy gate film by using the hard mask structure 120 as a mask to form the dummy gate structure 110.
In this embodiment, after the dummy gate structure 110 is formed, the hard mask structure 120 located on the top of the dummy gate structure 110 may be first retained, where the hard mask structure 120 includes a first hard mask layer 121 located on the top surface of the dummy gate structure 110, and a second hard mask layer 122 located on the first hard mask layer 121, and the hard mask structure 120 is used to protect the top of the dummy gate structure 110 in a subsequent process.
In this embodiment, the material of the first hard mask layer 121 is silicon nitride; in other embodiments, the material of the first hard mask layer may also be silicon oxynitride, silicon carbide, or boron nitride.
In this embodiment, the material of the second hard mask layer 122 is silicon oxide.
In this embodiment, a sidewall 112 is further formed on the sidewall of the dummy gate structure 110, and the top of the sidewall 112 is flush with the top surface of the hard mask structure 120, i.e., flush with the top surface of the second hard mask layer 122.
In this embodiment, the material of the side wall 112 is a low-K dielectric material (the low-K dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.5 and less than 3.9), and the material of the side wall 112 is SiCN; in other embodiments, the material of the sidewall 112 may also be silicon nitride.
With continued reference to fig. 4, an etch stop layer 200 is formed over the substrate 100 and the dummy gate structure 110.
In this embodiment, the etching stop layer 200 covers the surface of the substrate 100, the surface of the sidewall 112, and the top surface of the second hard mask layer 122.
In this embodiment, the material of the etching stop layer 200 is silicon nitride; in other embodiments, the material of the etch stop layer 200 may also be silicon oxynitride, silicon carbide, or boron nitride.
Referring to fig. 5, a protective layer 210 is formed on the surface of the etch stop layer 200.
In this embodiment, the material of the protective layer 210 is silicon dioxide; in other embodiments, the material of the protective layer 210 may be one or more of borosilicate glass, borophosphosilicate glass, or tetraethyl orthosilicate.
In this embodiment, the method for forming the protection layer 210 is a chemical vapor deposition method; in other embodiments, the protective layer 210 may also be formed using atomic layer deposition.
In this embodiment, the protection layer 210 may protect the etching stop layer 200 from being damaged in the subsequent process, so that the height of the etching stop layer 200 may not be changed, and thus the height of the formed metal gate may be stable.
With continued reference to fig. 5, a sacrificial layer 300 is formed on the surface of the protective layer 210, and the top of the sacrificial layer 300 is flush with the top surface of the dummy gate structure 110.
In this embodiment, the step of forming the sacrificial layer 300 specifically includes: forming a sacrificial material layer on the surface of the protective layer 210, wherein the sacrificial material layer covers the top surface and the side wall surface of the protective layer 210; the sacrificial material layer is etched back until the top of the sacrificial material layer is flush with the top of the dummy gate structure, forming a sacrificial layer 300.
In this embodiment, the material of the sacrificial material layer is a carbon-containing organic matter; in other embodiments, the material of the sacrificial material layer may also be a bottom antireflective layer.
In this embodiment, the sacrificial material layer is formed by spin coating.
In this embodiment, the method of etching back the sacrificial material layer is dry etching, and the process parameters of the dry etching include: the etching atmosphere comprises O 2 The O is 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-200 mTorr, and the etching is performedThe etching power is 100-2000W.
In this embodiment, the top of the sacrificial layer 300 is flush with the top of the dummy gate structure 110, and when the protective layer 210 and the etching stop layer 200 are etched later, the protective layer 210 and the etching stop layer 200 below the dummy gate structure 110 can be protected from being etched, so that the heights of the protective layer 210 and the etching stop layer 200 are consistent with the height of the dummy gate structure 110, and when an interlayer dielectric layer and a metal gate are formed later, the height of the metal gate is controlled more easily based on the height of the etching stop layer 200.
Referring to fig. 6, the protective layer 210 and the etch stop layer 200 are etched sequentially until the top of the protective layer 210, the top of the etch stop layer 200 and the top surface of the dummy gate structure 110 are flush.
In this embodiment, the protection layer 210 is etched first until the top of the protection layer 210 is flush with the top of the dummy gate structure 110, and then the etching stop layer 200 is etched until the top of the etching stop layer 200 is flush with the top of the dummy gate structure 110.
In this embodiment, the method of etching the protection layer 210 is a Certas etching process (gas chemical etching based on atomic layer etching). The Certas etching process comprises remote etching and in-situ annealing after the remote etching, wherein the process parameters of the remote etching comprise: the etching atmosphere comprises NH 3 And HF 5 The NH is 3 The flow rate of the gas is 5-100 sccm, the HF 5 The flow of the gas is 5-100 sccm, and the etching temperature is 20-80 ℃; the annealing temperature of the in-situ annealing is 100-250 ℃.
In this embodiment, the method for etching the etching stop layer 200 is dry etching, and the process parameters of the dry etching include: the etching atmosphere comprises CH 3 F and O 2 The CH is 3 The flow rate of the F gas is 10-500 sccm, the O 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-100 millitorr, and the etching power is 100-2000 watts.
In this embodiment, the material of the etching stop layer 200 is the same as that of the first hard mask layer 121, and the second hard mask layer 122 protects the first hard mask layer 121 from being damaged when the etching stop layer 200 is etched.
In this embodiment, the method further includes: etching the side wall 112 until the top of the side wall 112 is flush with the top of the dummy gate structure 110, wherein the method for etching the side wall 112 is dry etching, and the process parameters of the dry etching include: the etching atmosphere comprises CH 3 F and O 2 The CH is 3 The flow rate of the F gas is 10-500 sccm, the O 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-100 millitorr, and the etching power is 100-2000 watts.
In this embodiment, before the interlayer dielectric layer is formed, the etching stop layer 200 and the side wall 112 are etched respectively until the top of the etching stop layer 200, the top of the side wall 112 and the top of the dummy gate structure 110 are flush, so that the heights of the etching stop layer 200 and the side wall 112 are easy to control, the phenomenon of uneven surface grinding occurring when the etching stop layer and the side wall are simultaneously ground is avoided, the height uniformity of the etching stop layer and the side wall is increased, and stable height reference is provided for the subsequent formation of the metal gate.
Referring to fig. 7, the sacrificial layer 300 is removed.
In this embodiment, the sacrificial layer 300 is removed by an ashing process.
After the sacrificial layer 300 is removed, an interlayer dielectric layer is formed on the substrate 100, and the interlayer dielectric layer exposes the top of the dummy gate structure 110.
Specifically, the step of forming the interlayer dielectric layer includes:
referring to fig. 8, a dielectric material layer 400 is formed on the substrate 100, and the top of the dielectric material layer 400 is higher than the top surface of the dummy gate structure 110.
In this embodiment, the dielectric material layer 400 covers the surface of the protection layer 210, the surface of the etching stop layer 200, the surface of the sidewall 112, and the surface of the hard mask structure 120.
In this embodiment, the material of the dielectric material layer 400 is the same as the material of the protection layer 210 and the material of the second hard mask layer 122, and is silicon oxide, so that the process steps of removing the protection layer 210 or removing the second hard mask layer 122 can be reduced, and the process flow is simplified.
In other embodiments, the material of the dielectric material layer may be one or more of borosilicate glass, borophosphosilicate glass, and tetraethyl orthosilicate.
In this embodiment, the method for forming the dielectric material layer 400 is a chemical vapor deposition method. In other embodiments, the dielectric material layer 400 may also be formed using atomic layer deposition.
Referring to fig. 9 to 10, after the dielectric material layer 400 is formed, the dielectric material layer 400 is chemically and mechanically polished until the top surface of the dummy gate structure 110 is exposed, thereby forming an interlayer dielectric layer 410.
In this embodiment, the chemical mechanical polishing is performed on the dielectric material layer 400 until the top surface of the first hard mask layer 121 is exposed; and performing chemical mechanical polishing on the first hard mask layer 121 and the dielectric material layer 400, removing the first hard mask layer 121, and exposing the top surface of the dummy gate structure 110.
In this embodiment, the method of performing the chemical mechanical polishing on the dielectric material layer 400 and the first hard mask layer 121 is a conventional process, and will not be described herein.
Referring to fig. 11, the dummy gate structure 110 is removed to form an opening 500.
In this embodiment, the dummy gate layer 111 and the dummy oxide layer of the dummy gate structure 110 are removed.
In this embodiment, the method for removing the dummy gate structure 110 is a dry etching process; in other embodiments, a wet etch process may also be used to remove the dummy gate structure 110.
Referring to fig. 12, after the opening 500 is formed, the opening 500 is filled with metal, and a metal gate 510 is formed.
The metal gate 510 is formed by the following steps: filling the opening with a metal layer (not shown), wherein the metal layer covers the surface of the interlayer dielectric layer 410; the metal layer is chemically and mechanically polished until the top of the metal layer is flush with the top surface of the interlayer dielectric layer 410, forming a metal gate 510.
When forming the metal gate 510, the height of the interlayer dielectric layer 410 is used as a reference, the metal layer is directly polished to be level with the interlayer dielectric layer 410, and the polishing selection ratio among the interlayer dielectric layer, the etching stop layer, the side wall layer and the metal layer is not needed to be considered, so that the height of the formed metal gate is easier to control.
The metal gate 510 is made of one or more of aluminum, copper, tungsten, cobalt, and platinum.
In this embodiment, before forming the metal gate 510, a diffusion barrier layer (not shown) is also formed at the bottom and the sidewalls of the opening 500. The diffusion barrier layer is used to prevent metal ions in the metal gate 610 from diffusing into the interlayer dielectric layer 410, which affects the stability of the device. The diffusion barrier layer is made of TiN or TaN.
According to the method for forming the semiconductor structure, before the interlayer dielectric layer is formed, the etching stop layer and the side wall are etched respectively until the tops of the etching stop layer and the side wall are flush with the top of the pseudo gate structure, then the interlayer dielectric layer is formed, the top of the formed interlayer dielectric layer is flush with the top of the pseudo gate structure, the grinding ratio among the interlayer dielectric layer, the etching stop layer, the side wall layer and the pseudo gate structure does not need to be considered, the heights of the interlayer dielectric layer, the etching stop layer and the side wall layer are kept consistent more easily, and then when the metal gate is formed by taking the height of the interlayer dielectric layer or the etching stop layer as a reference, the height of the metal gate is controlled more easily, so that the formed metal gate is more stable.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, and forming a pseudo gate structure on the substrate;
forming an etching stop layer on the substrate and the pseudo gate structure;
forming a protective layer on the surface of the etching stop layer;
forming a sacrificial layer on the surface of the protective layer, wherein the top of the sacrificial layer is flush with the top surface of the pseudo gate structure;
sequentially etching the protective layer and the etching stop layer until the top of the protective layer, the top of the etching stop layer and the top surface of the pseudo gate structure are flush;
removing the sacrificial layer;
forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer exposes the top of the pseudo gate structure;
removing the pseudo gate structure to form an opening;
and filling metal into the opening to form a metal grid.
2. The method of claim 1, wherein the sacrificial layer is formed of a carbon-containing organic material.
3. The method of forming a semiconductor structure of claim 2, wherein the method of forming the sacrificial layer comprises spin coating.
4. The method of forming a semiconductor structure of claim 1, wherein the step of forming the sacrificial layer comprises:
forming a sacrificial material layer on the surface of the protective layer, wherein the sacrificial material layer covers the top surface and the side wall surface of the protective layer;
and etching the sacrificial material layer until the top of the sacrificial material layer is flush with the top of the pseudo gate structure, and forming a sacrificial layer.
5. The method of forming a semiconductor structure of claim 4, wherein the method of etching back the sacrificial material layer is a dry etch, and wherein the process parameters of the dry etch include: the etching atmosphere comprises O 2 The O is 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-200 millitorr, and the etching power is 100-2000 watts.
6. The method of forming a semiconductor structure of claim 1, wherein the method of forming the protective layer comprises chemical vapor deposition or atomic layer deposition.
7. The method of claim 1, wherein the method of etching the protective layer is a Certas etching process comprising a remote etch and an in-situ anneal after the remote etch, wherein the process parameters of the remote etch comprise: the etching atmosphere comprises NH 3 And HF 5 The NH is 3 The flow rate of the gas is 5-100 sccm, the HF 5 The flow of the gas is 5-100 sccm, and the etching temperature is 20-80 ℃; the annealing temperature of the in-situ annealing is 100-250 ℃.
8. The method of forming a semiconductor structure of claim 1, wherein the step of forming the interlayer dielectric layer comprises:
forming a dielectric material layer on the substrate, wherein the top of the dielectric material layer is higher than the top surface of the pseudo gate structure;
and carrying out chemical mechanical polishing on the dielectric material layer until the top surface of the pseudo gate structure is exposed, so as to form an interlayer dielectric layer.
9. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer and a material of the interlayer dielectric layer are the same.
10. The method of claim 9, wherein the material of the protective layer and the interlayer dielectric layer comprises one or more of silicon oxide, borosilicate glass, borophosphosilicate glass, or tetraethyl orthosilicate.
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