CN113130297A - Silicon-gallium nitride composite substrate, composite device and preparation method - Google Patents
Silicon-gallium nitride composite substrate, composite device and preparation method Download PDFInfo
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Abstract
The invention provides a silicon-gallium nitride composite substrate, a composite device and a preparation method, wherein the silicon-gallium nitride composite substrate comprises a silicon substrate, a shallow trench isolation structure, a III-N family epitaxial structure and a second silicon layer; the silicon substrate includes a first silicon layer; the shallow trench isolation structure is positioned on the silicon substrate and penetrates through the first silicon layer; the III-N family epitaxial structure is positioned on the surface of the first silicon layer, comprises a GaN channel layer and an AlGaN barrier layer and is positioned on the outer side of the shallow trench isolation structure; the second silicon layer is located on the surface of the first silicon layer and located on the inner side of the shallow trench isolation structure. The invention can integrate the silicon-based and gallium nitride-based composite substrates on the same plane, and further can prepare a coplanar integrated silicon-gallium nitride composite device, thereby realizing the coplanar and small-spacing interconnection of the silicon device and the gallium nitride device at the wafer manufacturing stage, solving the problem of parasitic effect of interconnection of different material devices, saving the occupied board area and improving the integration level and the performance of the integrated device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a silicon-gallium nitride composite substrate, a composite device and a preparation method.
Background
As a representative third generation semiconductor material, gallium nitride (GaN) has many excellent characteristics such as wide band gap, excellent radiation noise resistance, high avalanche breakdown electric field, good thermal conductivity, and high electron drift rate under a strong field, and is widely used in the fields such as laser, LED, microwave, and radio frequency.
The existing power semiconductor market mainly comprises silicon power devices, and in the past 20 years, the power density of the silicon power devices is increased by 5-6 times every 10 years, but the power density of the silicon power devices is close to the theoretical limit, and the performance is difficult to be further improved. Compared with silicon or gallium arsenide, the GaN power semiconductor has the advantages of wide band gap, excellent thermal stability, high breakdown voltage, high electron saturation drift velocity and excellent radiation resistance, and compared with the silicon power semiconductor, the GaN power semiconductor also has low-temperature resistance, so that the GaN power semiconductor can reduce power conversion loss caused by the power semiconductor, and the power system and the power loss are minimized.
At present, the GaN device is mainly based on a discrete device, and the GaN integrated circuit has obvious advantages, but because the GaN material cannot randomly define a p-type region or an n-type region through ion implantation or diffusion, the development of the GaN integrated circuit is limited. At present, the mainstream is to adopt a device cascade method, namely, a silicon-based metal oxide semiconductor field effect transistor device (Si MOSFET) and a GaN device are interconnected in an external routing interconnection or flip-chip ball-planting interconnection mode, but the packaging interconnection method can introduce extra parasitic, reduce the performance of the whole integrated device and increase the system integration area.
Therefore, it is necessary to provide a silicon-gallium nitride composite substrate, a composite device and a preparation method thereof, especially in the field of high-frequency and high-speed GaN integrated circuits.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a silicon-gallium nitride composite substrate, a composite device and a manufacturing method, which are used for solving the problem that the GaN integrated circuit is difficult to manufacture in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a method for preparing a silicon-gallium nitride composite substrate, comprising the steps of:
providing a silicon substrate, wherein the silicon substrate comprises a first silicon layer;
forming a III-N epitaxial structure on the surface of the first silicon layer, wherein the III-N epitaxial structure comprises a GaN channel layer and an AlGaN barrier layer;
forming a first hard mask layer covering the III-N family epitaxial structure, and patterning the first hard mask layer;
etching the III-N family epitaxial structure to form a groove exposing the first silicon layer;
forming an isolation side wall in the groove, wherein the isolation side wall covers the side wall of the III-N family epitaxial structure;
forming a second silicon layer, wherein the second silicon layer fills the groove;
exposing the first hard mask layer;
removing the first hard mask layer to form a second hard mask layer, and patterning the second hard mask layer;
removing the isolation side wall to form a shallow trench;
forming a shallow trench isolation structure, wherein the shallow trench isolation structure fills the shallow trench and penetrates through the first silicon layer;
and exposing the second hard mask layer.
Optionally, the surface of the second silicon layer is made flush with the surface of the shallow trench isolation structure by a CMP process.
Optionally, the silicon substrate includes a SOI substrate or a silicon substrate formed by a bonding method and having the first silicon layer on a surface thereof; the first silicon layer is a Si (111) layer; the second silicon layer is a Si (111) layer.
Optionally, the III-N epitaxial structure further comprises one or a combination of a buffer layer between the first silicon layer and the GaN channel layer and a cap layer between the AlGaN barrier layer and the first hard mask layer.
Optionally, the first hard mask layer includes one or a combination of a silicon nitride layer and a silicon oxide layer; the second hard mask layer comprises one or a combination of a silicon nitride layer and a silicon oxide layer; the shallow trench isolation structure comprises one or a combination of a silicon nitride layer and a silicon oxide layer.
The present invention also provides a silicon-gallium nitride composite substrate, including:
a silicon substrate comprising a first silicon layer;
the shallow trench isolation structure is positioned on the silicon substrate and penetrates through the first silicon layer;
a III-N epitaxial structure on the surface of the first silicon layer, the III-N epitaxial structure including a GaN channel layer and an AlGaN barrier layer, and the III-N epitaxial structure being outside the shallow trench isolation structure;
and the second silicon layer is positioned on the surface of the first silicon layer, and the second silicon layer is positioned on the inner side of the shallow trench isolation structure.
Optionally, a surface of the second silicon layer is flush with a surface of the shallow trench isolation structure.
Optionally, the silicon substrate comprises a SOI substrate; the first silicon layer is a Si (111) layer; the second silicon layer is a Si (111) layer; the shallow trench isolation structure comprises one or a combination of a silicon nitride layer and a silicon oxide layer.
The invention also provides a preparation method of the silicon-gallium nitride composite device, which comprises the step of preparing the silicon-gallium nitride composite device by adopting any one preparation method of the silicon-gallium nitride composite substrate.
The invention also provides a silicon-gallium nitride composite device, which comprises any one of the silicon-gallium nitride composite substrates.
As described above, the silicon-gallium nitride composite substrate, the composite device and the preparation method of the invention can prepare the composite substrate integrating silicon-based and gallium nitride-based on the same plane, and further can prepare the coplanar integrated silicon-gallium nitride composite device, thereby realizing interconnection of the silicon device and the gallium nitride device on a coplanar and small-pitch wafer in the wafer manufacturing stage, solving the problem of parasitic effect of interconnection of different material devices, saving the board occupation area, improving the integration level and improving the performance of the integrated device.
Drawings
Fig. 1 is a schematic view showing a process flow of preparing a silicon-gallium nitride composite substrate according to the present invention.
FIG. 2a is a schematic diagram of a silicon substrate according to the present invention.
FIG. 2b is a schematic structural diagram of another silicon substrate according to the present invention.
FIG. 3 is a schematic diagram of a III-N epitaxial structure formed according to the present invention.
Fig. 4 is a schematic structural diagram after forming the isolation sidewall spacers in the present invention.
Fig. 5 is a schematic structural view of the second silicon layer formed in the present invention.
FIG. 6 is a schematic structural diagram of the present invention after a second hard mask layer is formed.
FIG. 7 is a schematic diagram of the structure after forming the shallow trench in the present invention.
FIG. 8 is a schematic diagram of a shallow trench isolation structure according to the present invention.
Description of the element reference numerals
100 silicon substrate
101 first silicon layer
111 second silicon layer
102 silicon oxide insulating layer
103 silicon substrate
200 III-N epitaxial structure
301 first hard mask layer
302 second hard mask layer
400 groove
500 isolating side wall
600 shallow trench
700 shallow trench isolation structure
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a method for preparing a silicon-gallium nitride composite substrate, including the following steps:
providing a silicon substrate, wherein the silicon substrate comprises a first silicon layer;
forming a III-N epitaxial structure on the surface of the first silicon layer, wherein the III-N epitaxial structure comprises a GaN channel layer and an AlGaN barrier layer;
forming a first hard mask layer covering the III-N family epitaxial structure, and patterning the first hard mask layer;
etching the III-N family epitaxial structure to form a groove exposing the first silicon layer;
forming an isolation side wall in the groove, wherein the isolation side wall covers the side wall of the III-N family epitaxial structure;
forming a second silicon layer, wherein the second silicon layer fills the groove;
exposing the first hard mask layer;
removing the first hard mask layer to form a second hard mask layer, and patterning the second hard mask layer;
removing the isolation side wall to form a shallow trench;
forming a shallow trench isolation structure, wherein the shallow trench isolation structure fills the shallow trench and penetrates through the first silicon layer;
and exposing the second hard mask layer.
The embodiment can prepare the composite substrate integrating the silicon substrate and the gallium nitride substrate on the same plane, and further can be used for integrally preparing the coplanar silicon-gallium nitride composite device, thereby realizing interconnection of the silicon device and the gallium nitride device on the coplanar and small-spacing piece in the wafer manufacturing stage, solving the problem of parasitic effect of interconnection of different material devices, saving the occupied board area, improving the integration level and improving the performance of the integrated device.
Specifically, referring to fig. 2a to 8, schematic structural diagrams of the silicon-gallium nitride composite substrate prepared in this embodiment are shown.
Referring to fig. 2a and 2b, a silicon substrate 100 is first provided, wherein the silicon substrate 100 includes a first silicon layer 101.
Specifically, in the present embodiment, a silicon-on-insulator (SOI) is used as the silicon substrate 100, that is, the silicon substrate 100 includes a first silicon layer 101, an intermediate silicon oxide insulating layer 102 and a silicon substrate 103, but the type and structure of the silicon substrate 100 are not limited thereto, as shown in fig. 2b, the silicon substrate 100 may also adopt a silicon substrate having the first silicon layer 101 on the surface, for example, the upper layer is the first silicon layer 101, the lower layer is a silicon substrate of the silicon substrate 103 or a silicon carbide layer, and the first silicon layer 101 is a Si (111) layer, so as to facilitate epitaxial growth of the GaN layer. The silicon substrate 100 may be purchased directly or prepared by a bonding and peeling method, and the material, structure, size, and the like of the silicon substrate 100 may be specifically selected according to the requirement, which is not limited herein.
Next, referring to fig. 3, a III-N epitaxial structure 200 is formed on the surface of the first silicon layer 101, wherein the III-N epitaxial structure 200 includes a GaN channel layer and an AlGaN barrier layer.
As an example, the III-N epitaxial structure 200 may further include a buffer layer between the first silicon layer 101 and the GaN channel layer, and the buffer layer 200 is preferably a buffer stack structure.
Specifically, when the GaN channel layer is heteroepitaxially grown on the first silicon layer 101, the first silicon layer 101 and the GaN material have lattice mismatch and thermal expansion coefficient mismatch problems, so that after the buffer layer is introduced between the first silicon layer 101 and the GaN channel layer, the buffer layer can be used for adjusting stress, and then the GaN channel layer, the AlGaN barrier layer and the like are sequentially epitaxially grown on the buffer layer. Wherein the buffer layer may be AlxGa1-xN buffer stacks, where x is 0. ltoreq. x.ltoreq.1, i.e. the buffer layer may compriseAlN layer and Al with gradually changed components which are sequentially superposed from bottom to topxGa1-xN layers, e.g. Al0.3Ga0.7N layer, Al0.5Ga0.5N layers, etc., and the specific choice may be made according to the needs, and is not limited herein. It should be noted that the III-N epitaxial structure 200 is not limited to the above example, because the functional layers may be arranged as needed to facilitate the subsequent fabrication of integrated silicon-gallium nitride composite devices with different functions.
Next, referring to fig. 4, a first hard mask layer 301 is formed overlying the III-N epitaxial structure 200, and the first hard mask layer 301 is patterned.
As an example, a cap layer may be included between the AlGaN barrier layer and the first hard mask layer 301, wherein the cap layer may include a p-GaN cap layer, but is not limited thereto, and may be specifically configured and selected as needed.
By way of example, the first hard mask layer 301 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
Specifically, an etching window of the groove 400 may be formed by patterning the first hard mask layer 301, so that the III-N epitaxial structure 200 may be protected by the first hard mask layer 301 in a subsequent etching process. In this embodiment, the first hard mask layer 301 is a silicon nitride layer, but not limited thereto, and a stack of a silicon oxide layer and a silicon nitride layer or only a silicon oxide layer may also be used, which is not limited herein.
Then, etching the III-N epitaxial structure 200 to form the groove 400 exposing the first silicon layer 101; and forming an isolation sidewall 500 in the groove 400, wherein the isolation sidewall 500 covers the sidewall of the III-N group epitaxial structure 200.
As an example, the material of the isolation sidewall spacer 500 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
Specifically, the exposed III-N group epitaxial structure 200 may be protected by the isolation sidewall 500, the isolation sidewall 500 may play a supporting role, and when the isolation sidewall 500 subsequently forms the shallow trench isolation structure 700, the shallow trench 600 may be prepared based on the isolation sidewall 500, so that damage to the III-N group epitaxial structure 200 and the first silicon layer 101 may be reduced.
Next, referring to fig. 5, a second silicon layer 111 is formed, and the second silicon layer 111 fills the groove 400.
As an example, the material of the second silicon layer 111 is preferably the same as that of the first silicon layer 101, that is, the second silicon layer 111 is a Si (111) layer.
Specifically, the method for preparing the second silicon layer 111 includes selective epitaxy, but is not limited thereto, and the material and the preparation method of the second silicon layer 111 may be selected according to specific needs. After the second silicon layer 111 is formed, a planarization process is performed to expose the first hard mask layer 301, so as to obtain a flat surface, thereby facilitating subsequent process preparation.
Next, referring to fig. 6, the first hard mask layer 301 is removed, a second hard mask layer 302 is formed, and the second hard mask layer 302 is patterned.
As an example, the second hard mask layer 302 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
Specifically, an etching window of the shallow trench 600 may be formed by patterning the second hard mask layer 302, so that the III-N group epitaxial structure 200 may be protected by the second hard mask layer 302 during a subsequent etching process. In this embodiment, the second hard mask layer 302 is a silicon nitride layer, but not limited thereto, and a stack of a silicon oxide layer and a silicon nitride layer or only a silicon oxide layer may also be used, which is not limited herein.
Next, as shown in fig. 7, the isolation spacers 500 are removed to form the shallow trenches 600.
Specifically, after the isolation sidewall 500 is removed, the first silicon layer 101 is continuously etched until the first silicon layer 101 penetrates, so that after the shallow trench isolation structure 700 is formed subsequently, a silicon-based device region and a GaN device region can be partitioned by the shallow trench isolation structure 700, and devices with different functions can be completely isolated by the shallow trench isolation structure 700, thereby avoiding crosstalk and improving the performance of an integrated device.
Next, as shown in fig. 8, the shallow trench isolation structure 700 is formed, the shallow trench isolation structure 700 fills the shallow trench 600, and the shallow trench isolation structure 700 penetrates through the first silicon layer 101.
As an example, the shallow trench isolation structure 700 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
Specifically, the size, the specific type, and the like of the shallow trench isolation structure 700 may be selected according to the requirement, and are not limited herein. In this embodiment, it is preferable that the shallow trench isolation structure 700 is formed by depositing a silicon oxide material by using a high density plasma process (HDP) to fill the shallow trench 600 to form the shallow trench isolation structure 700 with high quality. After filling the shallow trench 600, a planarization process is performed to expose the second hard mask layer 302, so as to obtain a planar surface, which is convenient for the subsequent process preparation.
As an example, the planarization process of the shallow trench isolation structure 700 is preferably performed by using a Chemical Mechanical Polishing (CMP) method to obtain a flat surface with a small surface roughness, so that the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700.
Specifically, when the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700, a sufficient substrate space can be provided for the subsequent preparation of a silicon-based device, and the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700, so that the height difference between the subsequently prepared silicon-based device and a GaN device during interconnection can be reduced, additional parasitic is reduced, and the performance of an integrated device is improved.
As shown in fig. 8, the present embodiment further provides a silicon-gallium nitride composite substrate, which can be prepared by the above preparation process, but is not limited thereto, and in the present embodiment, the silicon-gallium nitride composite substrate is directly prepared by the above preparation method, so that reference can be made to the above embodiments regarding the material, structure, preparation process, beneficial effects, and the like of the silicon-gallium nitride composite substrate.
Specifically, the silicon-gallium nitride composite substrate includes a silicon substrate 100, a shallow trench isolation structure 700, a III-N epitaxial structure 200, and a second silicon layer 111. Wherein the silicon substrate 100 includes a first silicon layer 101; the shallow trench isolation structure 700 is located on the silicon substrate 100, and the shallow trench isolation structure 700 penetrates through the first silicon layer 101; the III-N epitaxial structure 200 is located on the surface of the first silicon layer 101, the III-N epitaxial structure 200 includes a GaN channel layer and an AlGaN barrier layer, and the III-N epitaxial structure 200 is located outside the shallow trench isolation structure 700; the second silicon layer 111 is located on the surface of the first silicon layer 101, and the second silicon layer 111 is located inside the shallow trench isolation structure 700.
As an example, the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700. And the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700, so that the height difference between the subsequently prepared silicon-based device and the GaN device during interconnection can be reduced, extra parasitic is reduced, and the performance of the integrated device is improved.
As an example, the silicon substrate 100 includes a SOI substrate; the first silicon layer is a Si (111) layer; the second silicon layer is a Si (111) layer; the shallow trench isolation structure 700 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
The embodiment also provides a preparation method of the silicon-gallium nitride composite device, and the preparation method of the silicon-gallium nitride composite device comprises the step of preparing the silicon-gallium nitride composite device by adopting the preparation method of the silicon-gallium nitride composite substrate. The preparation method, structure, material and the like of the silicon-gallium nitride composite substrate are not described in detail herein.
Specifically, after the silicon-gallium nitride composite substrate is prepared, for example, the source electrode, the gate electrode, the drain electrode, the interconnection structure, and the like may be prepared as required to form a composite device such as an integrated GaN HEMT device and a Si MOS device, but not limited thereto, the formed silicon-gallium nitride composite device may further include a composite device such as an integrated GaN laser and a Si MOS device or a composite device such as an integrated GaN LED device and a Si MOS device, and the III-N group epitaxial structure 200 may be adaptively selected and replaced according to the type of the integrated device required
The embodiment also provides a silicon-gallium nitride composite device, which comprises the silicon-gallium nitride composite substrate. The preparation method, structure, material and the like of the silicon-gallium nitride composite substrate are not described in detail herein.
Specifically, the silicon-gallium nitride composite device may include a composite device integrating a GaN HEMT device and a Si MOS device, the composite device may achieve higher efficiency, and the parasitic capacitance of the composite device may be reduced by 20% as compared to a case code structure gallium nitride device packaged and interconnected. However, the silicon-gallium nitride composite device is not limited thereto, and the silicon-gallium nitride composite device may further include a composite device integrating a GaN laser and a Si MOS device, or a composite device integrating a GaN LED device and a Si MOS device, and the like, and only the III-N group epitaxial structure 200 needs to be adaptively selected and replaced according to the kind of the desired integrated device.
In summary, the silicon-gallium nitride composite substrate, the composite device and the preparation method of the invention can prepare the composite substrate integrating silicon base and gallium nitride base on the same plane, and further can prepare the coplanar integrated silicon-gallium nitride composite device, thereby realizing the coplanar and small-pitch on-chip interconnection of the silicon device and the gallium nitride device in the wafer manufacturing stage, solving the parasitic effect problem of interconnection of different material devices, saving the board occupation area, improving the integration level, shortening the interconnection path and improving the performance of the integrated device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a silicon-gallium nitride composite substrate is characterized by comprising the following steps:
providing a silicon substrate, wherein the silicon substrate comprises a first silicon layer;
forming a III-N epitaxial structure on the surface of the first silicon layer, wherein the III-N epitaxial structure comprises a GaN channel layer and an AlGaN barrier layer;
forming a first hard mask layer covering the III-N family epitaxial structure, and patterning the first hard mask layer;
etching the III-N family epitaxial structure to form a groove exposing the first silicon layer;
forming an isolation side wall in the groove, wherein the isolation side wall covers the side wall of the III-N family epitaxial structure;
forming a second silicon layer, wherein the second silicon layer fills the groove;
exposing the first hard mask layer;
removing the first hard mask layer to form a second hard mask layer, and patterning the second hard mask layer;
removing the isolation side wall to form a shallow trench;
forming a shallow trench isolation structure, wherein the shallow trench isolation structure fills the shallow trench and penetrates through the first silicon layer;
and exposing the second hard mask layer.
2. The method for producing a silicon-gallium nitride composite substrate according to claim 1, characterized in that: and through a CMP process, the surface of the second silicon layer is flush with the surface of the shallow trench isolation structure.
3. The method for producing a silicon-gallium nitride composite substrate according to claim 1, characterized in that: the silicon substrate comprises an SOI substrate or a silicon substrate which is formed by a bonding method and provided with the first silicon layer on the surface; the first silicon layer is a Si (111) layer; the second silicon layer is a Si (111) layer.
4. The method for producing a silicon-gallium nitride composite substrate according to claim 1, characterized in that: the III-N epitaxial structure further includes one or a combination of a buffer layer between the first silicon layer and the GaN channel layer and a cap layer between the AlGaN barrier layer and the first hard mask layer.
5. The method for producing a silicon-gallium nitride composite substrate according to claim 1, characterized in that: the first hard mask layer comprises one or a combination of a silicon nitride layer and a silicon oxide layer; the second hard mask layer comprises one or a combination of a silicon nitride layer and a silicon oxide layer; the shallow trench isolation structure comprises one or a combination of a silicon nitride layer and a silicon oxide layer.
6. A silicon-gallium nitride composite substrate, comprising:
a silicon substrate comprising a first silicon layer;
the shallow trench isolation structure is positioned on the silicon substrate and penetrates through the first silicon layer;
a III-N epitaxial structure on the surface of the first silicon layer, the III-N epitaxial structure including a GaN channel layer and an AlGaN barrier layer, and the III-N epitaxial structure being outside the shallow trench isolation structure;
and the second silicon layer is positioned on the surface of the first silicon layer, and the second silicon layer is positioned on the inner side of the shallow trench isolation structure.
7. The silicon-gallium nitride composite substrate according to claim 6, wherein: the surface of the second silicon layer is flush with the surface of the shallow trench isolation structure.
8. The silicon-gallium nitride composite substrate according to claim 6, wherein: the silicon substrate includes an SOI substrate; the first silicon layer is a Si (111) layer; the second silicon layer is a Si (111) layer; the shallow trench isolation structure comprises one or a combination of a silicon nitride layer and a silicon oxide layer.
9. A preparation method of a silicon-gallium nitride composite device is characterized by comprising the following steps: the method for preparing the silicon-gallium nitride composite substrate comprises the step of preparing the silicon-gallium nitride composite device by using the method for preparing the silicon-gallium nitride composite substrate as defined in any one of claims 1 to 5.
10. A silicon-gallium nitride composite device, characterized by: the silicon-gallium nitride composite device comprises the silicon-gallium nitride composite substrate according to any one of claims 6 to 8.
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| CN202110313173.9A CN113130297A (en) | 2021-03-24 | 2021-03-24 | Silicon-gallium nitride composite substrate, composite device and preparation method |
| PCT/CN2022/077459 WO2022199310A1 (en) | 2021-03-24 | 2022-02-23 | Silicon-gallium nitride composite substrate and composite device, and preparation methods therefor |
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