CN113129805A

CN113129805A - Pixel circuit and display panel

Info

Publication number: CN113129805A
Application number: CN202110441662.2A
Authority: CN
Inventors: 洪嘉泽; 林振祺
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-12-08
Filing date: 2021-04-23
Publication date: 2021-07-16
Anticipated expiration: 2041-04-23
Also published as: TWI742956B; CN113129805B; TW202223863A

Abstract

A pixel circuit comprises a driving circuit, a light-emitting unit, a first transistor, a second transistor, a third transistor, a modulation circuit and a writing circuit. The driving circuit is used for providing a driving current. The first transistor is coupled to the driving circuit and is used for receiving the driving current. The second transistor is coupled between the light emitting unit and the first transistor and is selectively turned on according to the light emitting signal. The third transistor is coupled between the driving circuit and the light emitting unit. The modulation circuit is coupled to the control terminal of the first transistor and configured to output a first control voltage to the control terminal of the first transistor, so as to continuously switch the on/off state of the first transistor within a predetermined time period. The write circuit is coupled to the modulation circuit and outputs a second control voltage to the modulation circuit according to the periodic pulse signal and the first data voltage to determine the magnitude of the first control voltage.

Description

Pixel circuit and display panel

Technical Field

The present disclosure relates to a pixel circuit and a display panel, and more particularly, to a pixel circuit and a display panel for a tiled display.

Background

The pixel circuits of the display in the market are widely used as the driving and switching elements. However, in different semiconductor processes, the thin film transistor device may suffer from device characteristic degradation, such as variation or drift of threshold voltage, due to process errors or long-term operation. These problems may cause the uniformity of the panel brightness to be reduced, thereby affecting the picture quality.

In addition, when the pixel circuit is driven by a Simultaneous Emission Driving (simultaneousdisplay Driving) method, the transient current is too large, and the interval between the brightness and the darkness of each frame of the display image is long, which causes the problem of image flicker.

Disclosure of Invention

The present disclosure provides a pixel circuit including a driving circuit, a light emitting unit, a first transistor, a second transistor, a third transistor, a modulation circuit, and a writing circuit. The driving circuit is used for providing a driving current. The first transistor is coupled to the driving circuit and is used for receiving the driving current. The second transistor is coupled between the light emitting unit and the first transistor and is selectively turned on according to the light emitting signal. The third transistor is coupled between the driving circuit and the light emitting unit. The modulation circuit is coupled to the control terminal of the first transistor and configured to output a first control voltage to the control terminal of the first transistor, so as to continuously switch the on/off state of the first transistor within a predetermined time period. The write circuit is coupled to the modulation circuit and outputs a second control voltage to the modulation circuit according to the periodic pulse signal and the first data voltage to determine the magnitude of the first control voltage.

The present disclosure provides a display panel including a plurality of pixel circuits forming a pixel matrix having N columns, each of the pixel circuits including a driving circuit, a light emitting unit, a first transistor, a second transistor, a third transistor, a modulation circuit, and a write circuit. The driving circuit is used for providing a driving current. The first transistor is coupled to the driving circuit and is used for receiving the driving current. The second transistor is coupled between the light emitting unit and the first transistor and is selectively turned on according to the light emitting signal. The third transistor is coupled between the driving circuit and the light emitting unit. The modulation circuit is coupled to the control terminal of the first transistor and configured to output a first control voltage to the control terminal of the first transistor, so as to continuously switch the on/off state of the first transistor within a predetermined time period. The write circuit is coupled to the modulation circuit and outputs a second control voltage to the modulation circuit according to the periodic pulse signal and the first data voltage to determine the magnitude of the first control voltage.

One of the advantages of the pixel circuit and the display panel is that the flicker generated between bright and dark of the display frame is reduced by the progressive light emission.

Another advantage of the pixel circuit and the display panel is that the influence of the variation or the drift of the threshold voltage is reduced by the internal compensation.

Drawings

Fig. 1 is a functional block diagram of a pixel circuit according to some embodiments of the present disclosure.

Fig. 2 is a schematic diagram of a pixel circuit according to an embodiment of the disclosure.

Fig. 3 is a waveform diagram illustrating signal timing of a pixel circuit according to an embodiment of the disclosure.

Fig. 4A-4C are schematic diagrams illustrating an operation of a pixel circuit according to an embodiment of the disclosure.

Fig. 5 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

Fig. 6 is a schematic diagram of a display panel according to some embodiments of the present disclosure.

Description of reference numerals:

100,500: pixel circuit

110,510: driving circuit

120,520: modulation circuit

130,530: write circuit

EU: light emitting unit

T1-T13: transistor with a metal gate electrode

CV1, CV 2: control voltage

Sweet: pulse signal

EM, EM [ n +1 ]: luminous signal

DATA1, DATA 2: data voltage

I: drive current

PVDD, PVSS: driving voltage

SPAM [ n ], SPAM [ n +1 ]: control signal

SPWM [ n ], SPWM [ n +1 ]: control signal

C1, C2: capacitor with a capacitor element

N1-N5: node point

V_GH: first voltage

V_GL: second voltage

V_REF: reference voltage

D1-D4: time period

D4': time period

600: display panel

Detailed Description

The following embodiments are described in detail with reference to the drawings, but the embodiments are only for explaining the present invention and not for limiting the present invention, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure with equivalent technical effects produced by the recombination of elements is within the scope of the present disclosure.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each term used in the art, in the disclosure herein, and in the specific context, unless otherwise indicated. Certain words used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the disclosure.

The numbers of elements and the indices [1] to [ n ] in the signal numbers used in the specification and drawings of the present disclosure are for convenience only to refer to individual elements and signals, and the number of the aforementioned elements and signals is not intended to be limited to a specific number. In the present disclosure and the accompanying drawings, if a component number or a signal number index is not specified when the component number or the signal number is used, the component number or the signal number index is referred to as any unspecified component or signal in the component group or the signal group.

Fig. 1 is a functional block diagram of a pixel circuit 100 according to some embodiments of the present disclosure. As shown in fig. 1, the pixel circuit 100 includes a driving circuit 110, a modulation circuit 120, a writing circuit 130, a light emitting unit EU, a first transistor T1, a second transistor T2, and a third transistor T3.

Structurally, the driving circuit 110 is coupled to the first transistor T1. The second transistor T2 is coupled between the light emitting unit EU and the first transistor T1 and selectively turned on according to the emission signal EM [ n ]. The third transistor T3 is coupled between the light emitting unit EU and the driving circuit 110, and is selectively turned on according to the control signal SPWM [ n ]. The light emitting unit EU is configured to receive a driving voltage PVSS. The modulation circuit 120 is coupled between the control terminal of the first transistor T1 and the write circuit 130.

In operation, the driving circuit 110 is configured to provide a driving current I to the first transistor T1. The first transistor T1 is turned on or off according to the control voltage CV1 output by the modulation circuit 120, wherein the first transistor T1 is continuously switched to its on/off state by the control voltage CV1 for a predetermined period of time. The write circuit 130 outputs the control voltage CV2 to the modulation circuit 120 via the periodic pulse signal SWEEP and the DATA voltage DATA1 to determine the magnitude of the control voltage CV 1.

In this way, when the first transistor T1 is turned on by the control voltage CV1 and the second transistor T2 is also turned on according to the emission signal EM [ n ], the light emitting unit EU receives the driving current I of the driving circuit 110 and starts emitting light.

Fig. 2 is a schematic diagram of a pixel circuit 100 according to an embodiment of the disclosure.

In some embodiments, the driving circuit 110 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, a seventh transistor T7, and an eighth transistor T8. The fourth transistor T4 includes a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor T4 is configured to receive the driving voltage PVDD, the second terminal of the fourth transistor T4 is coupled to the first terminal of the first transistor T1, and the control terminal of the fourth transistor T4 is coupled to the first node N1. The fifth transistor T5 is coupled between the first node N1 and the first terminal of the first transistor T1, and the control terminal of the fifth transistor T5 is for receiving a control signalNumber SPAM [ n ]]. The sixth transistor T6 includes a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor T6 is coupled to the first terminal of the fourth transistor T4, the second terminal of the sixth transistor T6 is coupled to the second node N2, and the control terminal of the sixth transistor T6 is configured to receive the control signal SPWM [ N [ ]]. The first capacitor C1 is coupled between the first node N1 and the second node N2. The seventh transistor T7 includes a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor T7 is coupled to the second node N2, the second terminal of the seventh transistor T7 is for receiving a reference voltage V_REFA control terminal of the seventh transistor T7 for receiving the emission signal EM [ n ]]. The eighth transistor T8 includes a first terminal for receiving the DATA voltage DATA2, a second terminal coupled to the second node N2, and a control terminal for receiving a control signal SPAM [ N ] through a first terminal of an eighth transistor T8, a second terminal of an eighth transistor T8, and a control terminal of an eighth transistor T8]。

In some embodiments, the modulation circuit 120 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The ninth transistor T9 includes a first terminal, a second terminal and a control terminal, the first terminal of the ninth transistor T9 is for receiving a first voltage V_GHA second terminal of the ninth transistor T9 is coupled to the third node N3, and a control terminal of the ninth transistor T9 is coupled to the fourth node N4. A tenth transistor T10, a first terminal of the tenth transistor T10 is coupled to the third node N3, and a second terminal of the tenth transistor T10 is for receiving a second voltage V_GL. An eleventh transistor T11 coupled between the third node N3 and the fourth node N4 for generating a control signal SPAM [ N ]]And selectively conducting.

In some embodiments, the write circuit 130 includes a twelfth transistor T12, a thirteenth transistor T13, and a second capacitor C2. The twelfth transistor T12 includes a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth transistor T12 is coupled to the fifth node N5, the second terminal of the twelfth transistor T12 is for receiving the DATA voltage DATA1, and the control terminal of the twelfth transistor T12 is for receiving the control signal SPWM [ N ]. The thirteenth transistor T13 includes a first terminal, a second terminal, and a control terminal, the first terminal of the thirteenth transistor T13 is coupled to the fifth node N5, the second terminal of the thirteenth transistor T13 is coupled to the pulse signal SWEEP, and the control terminal of the thirteenth transistor T13 is configured to receive the emission signal EM [ N ]. The second capacitor C2 is coupled between the fourth node N4 and the fifth node N5.

In some embodiments, the first voltage V_GHGreater than the second voltage V_GLAnd the DATA voltage DATA1 is between the first voltage V_GHAnd a second voltage V_GLIn the meantime.

Fig. 3 is a signal timing waveform diagram of the pixel circuit 100 according to an embodiment of the disclosure. The control signals SPAM [ n ], SPWM [ n ] and the emission signal EM [ n ] have the same pulse width and a fixed phase difference with the control signals SPAM [ n +1], SPWM [ n +1] and EM [ n +1], respectively. In some embodiments, the signal may be generated by a gate driving circuit 601 of fig. 6. For example, the first column scanning signal S [1] generated by the gate driving circuit 601 may include control signals SPAM [1], SPWM [1] and emission signal EM [1], while the second column scanning signal S [2] generated by the gate driving circuit 601 may include control signals SPAM [2], SPWM [2] and emission signal EM [2], and so on.

In addition, the pulse signal sweet is used to provide a periodically varying triangular wave. In some embodiments, when the emission signals EM [ n ], EM [ n +1] are changed from a high level to a low level, the pulse signal sweet is changed from a high level to a low level.

Fig. 4A-4C are schematic diagrams illustrating the operation of the pixel circuit 100 according to an embodiment of the disclosure. The operation of the pixel circuit 100 of fig. 2 will be described with reference to fig. 3 in conjunction with fig. 4A-4C.

Please refer to fig. 4A. In the first period D1, the control signal SPWM [ n ] provides a Logic High level (e.g., a low voltage that can turn on the P-type transistor) to turn on the corresponding third transistor T3, sixth transistor T6, eleventh transistor T11, and twelfth transistor T12. The control signal SPAM [ n ] and the emission signal EM [ n ] provide a Logic Low level (e.g., a high voltage that turns off the P-type transistor) to turn off the corresponding second transistor T2, fifth transistor T5, seventh transistor T7, eighth transistor T8, and thirteenth transistor T13.

At this time, the first node N1 andthe second node N2 receives the driving voltage PVSS and the driving voltage PVDD through the third transistor T3 and the sixth transistor T6, respectively. The third node N3 and the fourth node N4 commonly receive a first voltage V_GHAnd a second voltage V_GLThe voltage of the control voltage CV1 is equal to the voltage of the control voltage CV 2. The fifth node N5 receives the DATA voltage DATA1 through the twelfth transistor T12.

Since the control terminal (i.e., the first node N1) of the fourth transistor T4 receives the low-voltage driving voltage PVSS, the driving circuit 110 can transmit the driving voltage PVDD to the first terminal of the first transistor T1 when the fourth transistor T4 is turned on during the first period D1.

Please refer to fig. 4B. In the second period D2, the control signal SPWM [ n ] and the emission signal EM [ n ] provide logic low level to turn off the corresponding second transistor T2, third transistor T3, sixth transistor T6, seventh transistor T7, eleventh transistor T11, twelfth transistor T12 and thirteenth transistor T13. The control signal SPAM [ n ] provides a logic high level to turn on the corresponding fifth transistor T5 and eighth transistor T8.

At this time, a charging path is formed between the first node N1 and the second terminal of the fourth transistor T4, such that the high voltage (i.e., the driving voltage PVDD) at the second terminal of the fourth transistor T4 continuously discharges the first node N1 through the fifth transistor T5 until the difference between the voltage at the first node N1 and the voltage at the fourth transistor T4 reaches the threshold voltage of the fourth transistor T4. The second node N2 receives the DATA voltage DATA2 through the eighth transistor T8.

In other words, the voltages at the first node N1 and the second node N2 have the following levels shown in equation 1 and equation 2, respectively:

V_N1＝PVDD-Vth+(V_REFDATA2 equation 1

V_N2DATA2 equation 2

V in formula 1 and formula 2_N1、V_N2The voltage levels of the first node N1 and the second node N2 are represented, and Vth represents the threshold voltage of the fourth transistor T4.

Please refer to fig. 3. In the third period D3, the control signals SPWM [ n ], SPWM [ n ] and the emission signal EM [ n ] are maintained at the same level as the second period D2.

Please refer to fig. 4C. In the fourth period D4, the control signals SPWM [ n ], SPAM [ n ] provide logic low level to turn off the corresponding third transistor T3, fifth transistor T5, sixth transistor T6, eighth transistor T8, eleventh transistor T11 and twelfth transistor T12. The emission signal EM [ n ] provides a logic high level to turn on the corresponding second transistor T2, seventh transistor T7, and thirteenth transistor T13.

At this time, the reference voltage V_REFCoupled to the first node N1 through the first capacitor C1, the voltage level of the first node N1 drops to turn on the fourth transistor T4. In some embodiments, the reference voltage V_REFWill be less than the DATA voltage DATA 2.

In more detail, the voltages at the first node N1 and the second node N2 have the following levels shown in equation 3 and equation 4, respectively:

V_N1＝PVDD-Vth+(V_REFDATA2 equation 3

V_N2＝V_REFEquation 4

As a result, in the fourth period D4, the fourth transistor T4 is turned on, so that the driving circuit 110 provides the driving current I with a magnitude shown in the following formula 5 to the first transistor T1.

In equation 5, k represents the product of the carrier mobility (carrier mobility), the gate unit capacitance (gate unit capacitance), and the aspect ratio of the fourth transistor T4. In addition, since the above formula 5 does not include the threshold voltage Vth of the fourth transistor T4, the magnitude of the driving current I is hardly affected by the variation of the threshold voltage of the fourth transistor T4.

Please continue to refer to fig. 4C. The pulse signal SWEEP is coupled to the fourth node N4 through the second capacitor C2, such that the control voltage CV2 of the fourth node N4 periodically rises or falls within the fourth period D4. In the embodiment, the ninth transistor T9 is a P-type metal oxide semiconductor (PMOS) transistor, the tenth transistor T10 is an N-type metal oxide semiconductor (NMOS) transistor, and the ninth transistor T9 and the tenth transistor T10 are turned on or off according to the magnitude of the control voltage CV 2.

For example, when the pulse signal SWEEP decreases from the first level V1 to the second level V2, the control voltage CV2 continuously decreases until the ninth transistor T9 turns on and the tenth transistor T10 turns off, such that the control voltage CV1 at the third node N3 and the first voltage V2_GHAre substantially the same.

On the other hand, when the pulse signal sweet rises from the second level V2 to the first level V1, the control voltage CV2 rises until the ninth transistor T9 turns off and the tenth transistor T10 turns on, so that the control voltage CV1 at the third node N3 and the second voltage V3583_GLAre substantially the same.

That is, the write circuit 130 can adjust the control voltage CV2 output to the modulation circuit 120 by the periodic pulse signal SWEEP to determine the magnitude of the control voltage CV1, so that the first transistor T1 continuously switches its switching state in the fourth period D4. In this embodiment, the magnitude of the control voltage CV1 is negatively correlated to the control voltage CV 2.

In some embodiments, the periodic pulse signal SWEEP may complete one oscillation within the period D4 '(i.e., the periodic pulse signal SWEEP rises back to the first level V1 after falling from the first level V1 to the second level V2), and the fourth period D4 may include a plurality of periods D4'.

In the present embodiment, the first transistor T1 is an nmos conductor, so when the control voltage CV1 rises to turn on the first transistor T1, the driving current I drives the light emitting unit EU to emit light through the first transistor T1 and the second transistor T2. On the contrary, when the control voltage CV1 drops to turn off the first transistor T1, the driving current I cannot enable the light emitting unit EU to emit light.

In other words, the duration of the light emission of the light emitting unit EU positively correlates to the time when the first transistor T1 is turned on. Therefore, the modulation circuit 120 can determine the gray scale of the pixel circuit 100 by adjusting the magnitude of the control voltage CV 1.

Fig. 5 is a schematic diagram of a pixel circuit 500 according to another embodiment of the disclosure. The pixel circuit 500 includes a driving circuit 510, a modulation circuit 520, a writing circuit 530, a light emitting unit EU, a first transistor T1, a second transistor T2, and a third transistor T3. The driving circuit 510 and the writing circuit 530 can be implemented by the driving circuit 110 and the writing circuit 130 of fig. 2, respectively.

Structurally, the coupling relationship among the driving circuit 210, the modulation circuit 220, the writing circuit 230, the light emitting unit EU, the first transistor T1, the second transistor T2 and the third transistor T3 in fig. 2 is also applicable to the driving circuit 510, the modulation circuit 520, the writing circuit 530, the light emitting unit EU, the first transistor T1, the second transistor T2 and the third transistor T3 in fig. 5, and will not be described herein again.

The modulation circuit 520 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The aforementioned connection relationship between the ninth transistor T9 and the eleventh transistor T11 in the modulation circuit 120 of fig. 2 is also applicable to the modulation circuit 520 of fig. 5, and is not repeated herein.

It is noted that the first transistor T1 of the pixel circuit 500 is a pmos conductor, the tenth transistor T10 is a pmos conductor, and the control terminal of the tenth transistor T10 is coupled to the second terminal of the tenth transistor T10.

In the embodiment of fig. 5, the difference from the embodiment of fig. 2 is that in the fourth period D4, when the control voltage CV2 rises to turn off the ninth transistor T9, the control voltage CV1 falls to turn on the first transistor T1. On the contrary, when the control voltage CV2 falls to turn on the ninth transistor T9, the control voltage CV1 rises to turn off the first transistor T1.

Fig. 6 is a schematic diagram of a display panel 600 shown in accordance with some embodiments of the present disclosure. The display panel 600 includes a gate driver circuit 601, a source driver circuit 602, and N-column pixel matrices r [1] to r [ N ] formed by a plurality of pixel circuits PX. In some embodiments, each pixel circuit PX in the pixel matrix r [1] -r [ N ] may be implemented by either the pixel circuit 100 or the pixel circuit 500 described previously.

The gate driving circuit 601 transmits scanning signals S [1] to S [ N ] to corresponding ones of the N pixel rows r [1] to r [ N ] via a plurality of gate lines. For example, the gate driving circuit 601 transmits the scan signal S [1] to the first row of pixels r [1], transmits the scan signal S [2] to the second row of pixels r [2], and so on.

In some embodiments, the display panel 600 enables the light emitting units (not shown) in the pixel circuits from the first row to the nth row in a row-by-row manner to achieve the effect of gradual light emission. For example, after the display panel 600 enables the first row of pixel rows r [1], the second row of pixel matrix r [2] and the third row of pixel rows r [3] are sequentially enabled until the Nth row of pixel rows r [ N ] is enabled. That is, pixels in the same column are illuminated at the same time, while pixels in different columns are sequentially illuminated.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the present disclosure, and therefore, the scope of the present disclosure should be determined by that of the appended claims.

Claims

1. A pixel circuit, comprising:

a driving circuit for providing a driving current;

a light emitting unit;

a first transistor coupled to the driving circuit for receiving the driving current;

a second transistor coupled between the light emitting unit and the first transistor for selectively turning on according to a light emitting signal;

a third transistor coupled between the driving circuit and the light emitting unit;

a modulation circuit coupled to a control terminal of the first transistor for outputting a first control voltage to the control terminal of the first transistor to continuously switch the on/off state of the first transistor within a predetermined time period; and

and the write circuit is coupled with the modulation circuit and used for outputting a second control voltage to the modulation circuit according to a periodic pulse signal and a first data voltage so as to determine the magnitude of the first control voltage.

2. A pixel circuit as claimed in claim 1, wherein the driving circuit comprises:

a fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is configured to receive a driving voltage, the second terminal of the fourth transistor is coupled to the first terminal of the first transistor, and the control terminal of the fourth transistor is coupled to a first node;

a fifth transistor coupled between the first node and the first end of the first transistor;

a sixth transistor, wherein a first terminal of the sixth transistor is coupled to the first terminal of the fourth transistor, and a second terminal of the sixth transistor is coupled to a second node;

a first capacitor coupled between the first node and the second node;

a seventh transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is coupled to the second node, the second terminal of the seventh transistor is configured to receive a reference voltage, and the control terminal of the seventh transistor is configured to receive the light emitting signal; and

a first terminal of the eighth transistor is coupled to the second node and a second terminal of the eighth transistor is coupled to the second node.

3. A pixel circuit as claimed in claim 1, wherein the modulation circuit further comprises:

a ninth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the ninth transistor is configured to receive a first voltage, the second terminal of the ninth transistor is coupled to the third node, and the control terminal of the ninth transistor is coupled to a fourth node;

a tenth transistor, a first terminal of which is coupled to the third node, and a second terminal of which is configured to receive a second voltage; and

an eleventh transistor coupled between the third node and the fourth node.

4. A pixel circuit as claimed in claim 3, wherein when said first transistor is an nmos conductor, said tenth transistor is an nmos conductor, and said control terminal of said tenth transistor is coupled to said fourth node.

5. A pixel circuit as claimed in claim 3, wherein when said first transistor is a pmos conductor, said tenth transistor is a pmos conductor, and said control terminal of said tenth transistor is coupled to said second terminal of said tenth transistor.

6. A pixel circuit as claimed in claim 1, wherein said write circuit comprises:

a twelfth transistor, a first end of the twelfth transistor being coupled to a fifth node, a second end of the twelfth transistor being configured to receive the first data voltage;

a thirteenth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the thirteenth transistor is coupled to the fifth node, the second terminal of the thirteenth transistor is coupled to the pulse signal, and the control terminal of the thirteenth transistor is configured to receive the light emitting signal; and

and a second capacitor coupled between the modulation circuit and the fifth node.

7. The pixel circuit according to claim 1, wherein the pulse signal is for providing a triangular wave, and the pulse signal changes from high level to low level when the light-emitting signal changes from high level to low level.

8. A pixel circuit as claimed in claim 1, wherein the first voltage is greater than the second voltage.

9. A display panel comprising a plurality of pixel circuits forming a pixel matrix having N rows, each of the pixel circuits comprising:

a driving circuit for providing a driving current;

a light emitting unit;

10. The display panel of claim 9, wherein the display panel sequentially enables the light emitting units of the pixel circuits from a first row to an Nth row.